CN104102058A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN104102058A CN104102058A CN201410313220.XA CN201410313220A CN104102058A CN 104102058 A CN104102058 A CN 104102058A CN 201410313220 A CN201410313220 A CN 201410313220A CN 104102058 A CN104102058 A CN 104102058A
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- pixel cell
- grid
- array base
- base palte
- source electrode
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Abstract
The invention provides an array substrate, a display panel and a display device. The array substrate comprises a first edge and a second edge which are opposite, wherein grid lines and data lines which are mutually crossed are formed on the array substrate and form multiple pixel units arranged in sequence along the length direction of the grid lines, the relative area of a grid and a source in each first pixel unit is greater than that of a grid and a source in each second pixel unit, and the distance between each first pixel unit and the first edge is greater than that between each second pixel unit and the first edge. The array substrate can be used for solving the problem that in the prior art, due to delay in signal receiving at one end of each grid line of an array substrate, an residual image occurs on a display panel.
Description
Technical field
The present invention relates to technical field of liquid crystal display, refer in particular to a kind of array base palte, display panel and display device.
Background technology
Fig. 1 is the structural representation of the array base palte of prior art liquid crystal display.Described array base palte comprises a plurality of grid lines that are arranged in parallel 1 and a plurality of data line being arranged in parallel 2, and grid line 1 intersects with data line 2, mutually intersect form region and form pixel cell, in each pixel cell, be provided with pixel electrode.In addition, each grid line 1 is all connected with scanning drive chip 3, by scanning drive chip 3 to grid line 1 input control signal; Each data line 2 is all connected with data driving chip 4, by data driving chip 4 to data line 2 input control signals.
Common described scanning drive chip 3 is arranged at a side of array base palte, for large scale liquid crystal panel, when scanning drive chip 3 is during to each grid line 1 input control signal, because one end of grid line 1 approaches scanning drive chip 3, and the other end extends to the direction away from scanning drive chip 3, and two ends is distant, grid line 1 has delay (RC Delay) near scanning drive chip 3 one end away from scanning drive chip 3 one end institute picked up signal.
As the electrical block diagram of Fig. 2 equivalent electrical circuit that is pixel cell, the sequential chart that Fig. 3 is input control signal, those skilled in the art can understand principle and the structure of the circuit in Fig. 2 and Fig. 3, at this, the implication of these two figure are not elaborated.According to Fig. 2 and Fig. 3, when grid institute input signal is low-voltage from high-voltage variable, due to the existence of Cgs (stray capacitance of grid and source electrode in TFT), produce Δ Vp, for making the generating positive and negative voltage of pixel electrode symmetrical, need to be by the voltage V of public electrode
combe set as:
By above-mentioned formula, guarantee the symmetry of the generating positive and negative voltage of pixel electrode, yet because grid line 1 has delay near scanning drive chip 3 one end away from scanning drive chip 3 one end institute picked up signal, these are different with the Δ Vp voltage of the pixel cell of locating away from scanning drive chip 3 one end near the pixel cell at scanning drive chip 3 places, one end by causing on grid line 1, as shown in the comparison diagram of Fig. 4.Single V
comsetting value cannot corresponding different Δ Vp, from the pixel cell near scanning drive chip 3 to the pixel cell away from scanning drive chip 3, Δ Vp diminishes gradually, causes the situation of the positive-negative polarity asymmetrical voltage of pixel electrode, as shown in Figure 5, produce DC stress (direct current (DC) bias), as shown in Figure 6, liquid crystal molecule is subject to the residual impact of direct current (DC) bias, can not deflect to normal condition, cause image retention as shown in Figure 7 to occur, affect display effect.
Summary of the invention
The object of technical solution of the present invention is to provide a kind of array base palte, display panel and display device, solves on prior art array base palte and has delay because grid line one end receives signal, causes the problem of display panel generation image retention.
The invention provides a kind of array base palte, comprise the first relative edge and the second edge, on described array base palte, be formed with grid line and data line arranged in a crossed manner mutually, length direction along grid line, cross one another grid line and data line form a plurality of pixel cells that are arranged in order, wherein in the first pixel cell, the relative area of grid and source electrode is greater than the relative area of grid and source electrode in the second pixel cell, and wherein the distance between the first pixel cell and described the first edge is greater than the distance between described the second pixel cell and described the first edge.
Preferably, array base palte described above, described pixel cell forms along the length direction of grid line a plurality of pixel cell groups that are arranged in order, and each pixel cell group comprises at least two pixel cells; In each pixel cell group, grid is identical with the relative area of source electrode, and wherein said the first pixel cell is arranged in the first pixel cell group, and described the second pixel cell is arranged in the second pixel cell group.
Preferably, array base palte described above, a wherein edge of described the first pixel cell group and described the first coincident, a wherein edge of described the second pixel cell group and described the second coincident, length direction along grid line, each pixel cell group from described the second pixel cell group to described the first pixel cell group, the relative area of grid and source electrode increases successively.
Preferably, array base palte described above, a plurality of described pixel cells form the multiple row pixel cell perpendicular with grid line, are positioned at the pixel cell of same row, and grid is identical with the relative area of source electrode.
Preferably, array base palte described above, the grid in described the first pixel cell and described the second pixel cell measure-alike, and in described the first pixel cell, the size of source electrode is greater than the size of source electrode in described the second pixel cell.
Preferably, array base palte described above, described pixel cell group comprises the 3rd pixel cell group, the quantity of the pixel cell in wherein said the 3rd pixel cell group is different from the quantity of the pixel cell of other pixel cell groups.
The present invention also provides a kind of display panel, comprises the array base palte described in as above any one.
The present invention also provides a kind of display device, comprises display panel as above.
At least one in specific embodiment of the invention technique scheme has following beneficial effect:
Described in the embodiment of the present invention, on array base palte, in pixel cell, grid is different from the relative area of source electrode, relative area away from grid and source electrode in first pixel cell at the first edge, be greater than the relative area of grid and source electrode in the second pixel cell that approaches the first edge, can compensate Δ Vp, make range sweep on each grid line drive the Δ Vp size of the far and near different pixel cell of chip to reach evenly, avoid the generation of image retention.
Accompanying drawing explanation
Fig. 1 represents the structural representation of common array base palte;
Fig. 2 represents the equivalent circuit structure figure of pixel cell;
Fig. 3 represents the sequential chart of pixel cell institute input control signal;
Fig. 4 represents the Δ Vp comparison diagram of the pixel electrode of prior art grid line near-end and the pixel electrode of grid line far-end;
Fig. 5 represents to produce the sequential chart of bias current voltage;
Fig. 6 represents that liquid crystal molecule is in the view being subject under the residual impact of direct current (DC) bias;
Comparison diagram when Fig. 7 represents image retention occurs;
Fig. 8 represents the schematic cross-section of thin-film transistor structure in each pixel cell of common array base palte;
Fig. 9 represents the planar structure schematic diagram of thin-film transistor structure;
Figure 10 represents described in first embodiment of the invention in array base palte, the planar structure schematic diagram of thin-film transistor structure;
Figure 11 represents described in second embodiment of the invention in array base palte, the planar structure schematic diagram of thin-film transistor structure;
Figure 12 represents to adopt the structure of array base palte of the present invention and the C that structure obtains of prior art array base palte
gscomparison diagram;
Figure 13 represents to adopt the structure of array base palte of the present invention and the structure of prior art array base palte to obtain the comparison diagram of Δ Vp.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
Array base palte described in the specific embodiment of the invention, comprise the first relative edge and the second edge, on described array base palte, be formed with grid line and data line arranged in a crossed manner mutually, length direction along grid line, cross one another grid line and data line form a plurality of pixel cells that are arranged in order, wherein in the first pixel cell, the relative area of grid and source electrode is greater than the relative area of grid and source electrode in the second pixel cell, and the distance between the first pixel cell and described the first edge is greater than the distance between described the second pixel cell and described the first edge.
In prior art array base palte, in each pixel cell, grid is all identical with the relative area of source electrode, make to arrive the pixel cell away from scanning drive chip near the pixel cell of scanning drive chip, the structure that Δ Vp diminishes gradually, described in the embodiment of the present invention, on array base palte, in pixel cell, grid is different from the relative area of source electrode, make the relative area away from grid and source electrode in first pixel cell at the first edge, be greater than the relative area of grid and source electrode in the second pixel cell that approaches the first edge, even also C
gs1be greater than C
gs2, C wherein
gs1be source electrode and the overlapping formed electric capacity of grid in the first pixel cell, C
gs2be source electrode and the overlapping formed electric capacity of grid in the second pixel cell, like this when the scanning drive chip for to grid line input control signal is arranged to the first edge, compared to the Δ Vp on prior art the first pixel cell
1be less than the Δ Vp on the second pixel cell
2result, by making C
gs1be greater than C
gs2, to Δ, Vp compensates, and makes range sweep on each grid line drive the Δ Vp size of the far and near different pixel cell of chip to reach evenly, avoids the generation of image retention.
Fig. 8 is the cross section structure schematic diagram of thin-film transistor structure in the pixel cell of array base palte, the planar structure schematic diagram that Fig. 9 is thin-film transistor structure.Consult Fig. 8 and Fig. 9, and in conjunction with the planar structure schematic diagram of the array base palte of Fig. 1, thin film transistor (TFT) in each pixel cell comprises glass substrate 10 and is formed at successively grid 11, gate insulation layer 12, active layer 13, ohmic contact layer 14, source-drain electrode 15 (comprising relative source electrode 151 and drain electrode 152) and the passivation layer 16 on glass substrate 10, grid 11 is connected with grid line 1, and drain electrode 152 is connected with data line 2.Wherein source electrode 151 and drain electrode 152 have with grid 11 part facing respectively, are also to have C between grid 11 and source electrode 151
gs, in conjunction with Fig. 2 and Fig. 3, with signal, do not have situation about postponing to give an example, Δ Vp and C
gsbetween there is following corresponding relation formula:
Wherein: C
stfor memory capacitance, C
lcfor liquid crystal capacitance, C
gsfor the stray capacitance of grid in TFT and source electrode, V
ghfor signal high voltage, C
glfor signal low-voltage.
According to above formula, the size of Δ Vp and C
gssize relevant, owing to being greater than the Δ Vp away from scanning drive chip 3 one end pixel cells near the Δ Vp of scanning drive chip 3 one end pixel cells, therefore as the C that make near scanning drive chip 3 one end pixel cells
gsbe less than the C away from scanning drive chip 3 one end pixel cells
gstime, can compensate due to the receiving signal delayed inhomogeneous phenomenon of Δ Vp of bringing on grid.
Figure 10 is described in first embodiment of the invention in array base palte, the planar structure schematic diagram of relation between grid 11 and source electrode 151, drain electrode 152.Consult shown in Figure 10, and in conjunction with Fig. 1, array base palte comprises the first relative edge 5 and the second edge 6, and on array base palte, form cross one another grid line 1 and data line 2, length direction along grid line 1, cross one another grid line 1 and data line 2 form a plurality of pixel cells that are arranged in order, example pixel cell A to G as shown in figure 10.In the first embodiment, different pixel cell A and the pixel cell G in the first edge 5 of distance arrays substrate, wherein grid is different from the relative area of source electrode, pixel cell G (the first pixel cell) is compared to pixel cell A (the second pixel cell) away from the first edge 5, and in pixel cell G, the relative area of grid 11 and source electrode 151 is greater than the relative area of grid 11 and source electrode 151 in pixel cell A.
Best, array base palte described in employing first embodiment of the invention, 5 to second edges 6, the first edge from array base palte, length direction along grid line 1, in each pixel cell, grid 11 increases successively with the relative area of source electrode 151, also from the pixel cell A shown in Fig. 1 and Figure 10 to pixel cell G, grid 11 increases successively with the relative area of source electrode 151, makes C
gsincrease successively.
In addition, particularly, a plurality of described pixel cells form the multiple row pixel cell perpendicular with grid line 1, best, in the present embodiment, are positioned at the pixel cell of same row, and grid 11 is identical with the relative area of source electrode 151.
Further, the above-mentioned pixel cell A that makes is to pixel cell G, and the mode that the relative area of grid 11 and source electrode 151 increases successively, is specifically as follows: in each pixel cell, grid is measure-alike, by changing the size of source electrode, to change the size of part relative to grid; As, make measure-alike to each grid in pixel cell G of pixel cell A, pixel cell A is increased successively to the size of source electrode in pixel cell G, as shown in figure 10, pixel cell A increases successively to the width of source electrode in pixel cell G, like this from pixel cell A to pixel cell G, C
gsincrease successively.
It will be appreciated by those skilled in the art that, except the mode that adopts the above-mentioned relative area that makes grid 11 and source electrode 151 to increase successively, the mode that also can make the size of grid, source electrode in each pixel cell increase respectively, as long as guarantee that the relative area of grid and source electrode increases successively.
By said structure, the Δ Vp on whole array base palte has good homogeneity, thereby avoids the generation of image retention.
The present invention also provides the array base palte of the second embodiment, identical with the first embodiment, in conjunction with Fig. 1, array base palte comprises the first relative edge 5 and the second edge 6, on array base palte 1, form cross one another grid line 1 and data line 2, along the length direction of grid line 1, cross one another grid line 1 and data line 2 form a plurality of pixel cells that are arranged in order.
Particularly, as shown in figure 11, each pixel cell of array base palte forms along the length direction of grid line 1 a plurality of pixel cell group a to g that are arranged in order, each pixel cell group comprises at least one pixel cell, in each pixel cell group, grid is identical with the relative area of source electrode, and wherein in the first pixel cell group, the grid of each pixel cell (the first pixel cell) and the relative area of source electrode are greater than the grid of each pixel cell in the second pixel cell group (the second pixel cell) and the relative area of source electrode.
Best, a wherein edge of described the first pixel cell group and described the first coincident, a wherein edge of described the second pixel cell group and described the second coincident, length direction along grid line, each pixel cell group from described the second pixel cell group to described the first pixel cell group, the relative area of grid and source electrode increases successively; Also as shown in figure 11,, from 5 to second edges 6, the first edge of array base palte, along the length direction of grid line 1, from pixel cell group a to pixel cell group g, the grid in each pixel cell group and the relative area of source electrode increase successively.
In above-mentioned each pixel cell group, the number of included pixel cell can be the same or different.While all only including a pixel cell in each pixel cell group, described in second embodiment of the invention, the structure of array base palte is identical with the structure of array base palte described in the first embodiment.When the number of included pixel cell is different in each pixel cell group, have at least the quantity of the pixel cell in a pixel cell group (the 3rd pixel cell group) different from the quantity of the pixel cell of other pixel cell groups.
Take the first embodiment as example, adopt the structure of array base palte of the present invention and the C that structure obtains of prior art array base palte
gsresult and the contrast of Δ Vp result, as shown in Figure 12 and Figure 13, can know according to Figure 12 and Figure 13, compared to traditional array substrate, and from pixel cell A to pixel cell G, the C of each pixel cell
gsidentical, but the Δ Vp of corresponding each pixel cell can reduce successively, and adopt the structure of array base palte of the present invention, and from pixel cell A to pixel cell G, C
gsincrease successively, to Δ, Vp compensates, and it is consistent that the Δ Vp of corresponding each pixel cell reaches basic unification, has good homogeneity, thereby avoid the generation of image retention.
Contrast table the following table is array base-plate structure described in employing first embodiment of the invention and each parameter of prior art array base-plate structure:
According to upper table, and in conjunction with Figure 13, apparently, the Δ Vp maximal value of prior art pixel cell and the deviation of minimum value are 0.029V; And by technical solution of the present invention, the Δ Vp maximal value of pixel cell and the deviation of minimum value are 0.004V, compared with prior art, significantly reduce.Therefore the Δ Vp of each pixel cell reaches basic uniformity, can avoid the generation of image retention.
The present invention also provides a kind of display panel and display device with above-mentioned array base palte on the other hand, and those skilled in the art should be able to understand the employing display panel of array base palte of the present invention and the structure of display device, at this, are not described in detail.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. an array base palte, comprise the first relative edge and the second edge, on described array base palte, be formed with grid line and data line arranged in a crossed manner mutually, length direction along grid line, cross one another grid line and data line form a plurality of pixel cells that are arranged in order, it is characterized in that, in the first pixel cell, the relative area of grid and source electrode is greater than the relative area of grid and source electrode in the second pixel cell, and wherein the distance between the first pixel cell and described the first edge is greater than the distance between described the second pixel cell and described the first edge.
2. array base palte as claimed in claim 1, is characterized in that, described pixel cell forms along the length direction of grid line a plurality of pixel cell groups that are arranged in order, and each pixel cell group comprises at least two pixel cells; In each pixel cell group, grid is identical with the relative area of source electrode, and wherein said the first pixel cell is arranged in the first pixel cell group, and described the second pixel cell is arranged in the second pixel cell group.
3. array base palte as claimed in claim 2, it is characterized in that, a wherein edge of described the first pixel cell group and described the first coincident, a wherein edge of described the second pixel cell group and described the second coincident, length direction along grid line, each pixel cell group from described the second pixel cell group to described the first pixel cell group, the relative area of grid and source electrode increases successively.
4. array base palte as claimed in claim 1, is characterized in that, a plurality of described pixel cells form the multiple row pixel cell perpendicular with grid line, is positioned at the pixel cell of same row, and grid is identical with the relative area of source electrode.
5. array base palte as claimed in claim 1, is characterized in that, the grid in described the first pixel cell and described the second pixel cell measure-alike, and in described the first pixel cell, the size of source electrode is greater than the size of source electrode in described the second pixel cell.
6. array base palte as claimed in claim 2, is characterized in that, described pixel cell group comprises the 3rd pixel cell group, and the quantity of the pixel cell in wherein said the 3rd pixel cell group is different from the quantity of the pixel cell of other pixel cell groups.
7. a display panel, is characterized in that, comprises the array base palte as described in claim 1 to 6 any one.
8. a display device, is characterized in that, comprises display panel as claimed in claim 7.
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| CN105742295A (en) * | 2016-03-23 | 2016-07-06 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN106896606A (en) * | 2017-04-24 | 2017-06-27 | 武汉华星光电技术有限公司 | A kind of display panel and display device |
| CN106896607A (en) * | 2017-04-27 | 2017-06-27 | 武汉华星光电技术有限公司 | A kind of array base palte and display device |
| CN107037651A (en) * | 2017-04-26 | 2017-08-11 | 武汉华星光电技术有限公司 | A kind of array base palte and light shield, display device |
| CN107037658A (en) * | 2017-06-16 | 2017-08-11 | 武汉华星光电技术有限公司 | A kind of array base palte |
| CN107272291A (en) * | 2017-07-25 | 2017-10-20 | 武汉华星光电技术有限公司 | A kind of preparation method of array base palte, display panel and the array base palte |
| CN107290913A (en) * | 2017-07-31 | 2017-10-24 | 武汉华星光电技术有限公司 | Display panel, array base palte and forming method thereof |
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Application publication date: 20141015 |
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