CN101702065B - Pixel array - Google Patents
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- CN101702065B CN101702065B CN 200910189925 CN200910189925A CN101702065B CN 101702065 B CN101702065 B CN 101702065B CN 200910189925 CN200910189925 CN 200910189925 CN 200910189925 A CN200910189925 A CN 200910189925A CN 101702065 B CN101702065 B CN 101702065B
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Abstract
The invention discloses a pixel array, comprising a plurality of scanning lines, data lines and pixel structures which are connected with the scanning lines and the data lines in a coupled manner and are in pixel arrangement. Each pixel structure comprises a switch element, a pixel unit, a compensation capacitor and a diode. In each pixel structure of the pixel structures in ith column, the control end and first end of the switch element are respectively coupled with the ith scanning line and one of data lines, a pixel unit is coupled with a second end of the switch element, the compensation capacitor is connected with the pixel unit in a coupled manner, and the anode end and the cathode end of the diode are respectively coupled with the compensation capacitor and the (i+1)th scanning line.
Description
[technical field]
The present invention relates to a kind of pel array, and be particularly related to a kind of pel array that improves feedthrough effect (feed through effect).
[background technology]
Along with the evolution of photoelectricity and semiconductor technology, it has driven the flourish of display panel.In many display panels, display panels (Liquid Crystal Display panel, LCD panel) be widely used recently, and (Cathode Ray Tube CRT) becomes one of the main flow of display panel of future generation to replace the cathode-ray tube display panel.
Figure 1A illustrates a kind of equivalent circuit diagram of pel array of available liquid crystal display panel.Please refer to Figure 1A, pel array 100 comprises many sweep trace GL parallel to each other
I-1, GL
i, GL
I+1..., many data line DL parallel to each other and with sweep trace GL
I-1, GL
i, GL
I+1... with a plurality of dot structures 110 that data line DL couples, wherein each dot structure 110 comprises thin film transistor (TFT) 110T and pixel cell 110P.Wherein each pixel cell 110P comprises the electric capacity that links to each other with pixel electrode, and the sweep trace that is connected to infrabasal plate or the memory capacitance Cst ' of common electrode line are arranged, and is connected to the liquid crystal capacitance C of the common electrode of upper substrate
LC'.
Hold above-mentionedly, sweep and arrange line GL
I-1, GL
i, GL
I+1... and data line DL intersects each other, and define the dot structure 110 of arrayed, wherein the grid of each thin film transistor (TFT) 110T and source electrode are coupled to corresponding scanning line and corresponding data line respectively, and drain electrode is coupled to corresponding pixel electrode.In more detail, the grid of the thin film transistor (TFT) 110T in the i row dot structure 110 is coupled to i bar sweep trace GL
i, so analogize the dot structure 110 of all the other row and the relation that couples of corresponding scanning line.
Figure 1B is according to the drive waveforms figure that one of them dot structure illustrated that is coupled to i bar sweep trace among Figure 1A.Please refer to Figure 1B, during ta, i bar sweep trace GL
iActivation, scanning voltage SG at this moment
i' voltage level be high level, and the data voltage V that transmitted of data line DL
Data' can be sent in the pixel electrode in the corresponding pixel cell 110P by thin film transistor (TFT) 110T, and the action of charging.By Figure 1B as can be known, the pixel voltage waveform such as the V of Dui Ying pixel electrode
Pixel' institute illustrates pixel voltage waveform V wherein
Pixel' voltage level be the voltage level of node N1 among Figure 1A.
Subsequently, the moment that finishes during the ta, sweep trace GL
iStop activation, this moment is because of the gate-to-drain stray capacitance C in the dot structure 110
GdExistence, make pixel voltage V
Pixel' be subjected to scanning voltage SG
iThe influence of negative edge and the feed-trough voltage that thereupon descends (feed through voltage) Δ V
FT'.General this phenomenon of title is called feedthrough effect (feed through effect), and it can make pixel voltage V
Pixel' generation off-line data voltage V
Data' situation.
Yet the feedthrough effect can cause display panels to produce flicker bad pictures such as (flicker).In addition, when the size of display panels was big more, the feedthrough effect of different pixels unit was not quite similar, and the uneven situation of display frame is become seriously, and so phenomenon of picture flicker just more is difficult to solve.
[summary of the invention]
Technical matters to be solved by this invention provides a kind of pel array, and it can reduce the feedthrough phenomenon, and then makes the scintillation of display frame obtain significantly to improve.
The present invention proposes a kind of pel array, and it comprises multi-strip scanning line, many data lines and couples with sweep trace and data line and a plurality of dot structures of arrayed.Each dot structure comprises on-off element, pixel cell, building-out capacitor and diode.In each dot structure in i row dot structure, the control end of on-off element and first end couple i bar sweep trace and data line wherein respectively, pixel cell couples second end of on-off element, and building-out capacitor couples pixel cell, and the anode tap of diode and cathode terminal couple (i+1) bar sweep trace and building-out capacitor respectively.
In one embodiment of this invention, each pixel cell comprises liquid crystal capacitance.One end of liquid crystal capacitance couples second end and the building-out capacitor of on-off element, and its other end couples common voltage.In one embodiment, each pixel cell in the i row dot structure also comprises storage capacitors, and wherein an end of storage capacitors couples second end and the building-out capacitor of on-off element, and its other end couples (i+1) bar sweep trace.
In one embodiment of this invention, each diode is a thin film transistor (TFT), wherein the source electrode of thin film transistor (TFT) and drain electrode one of among both the grid of person and thin film transistor (TFT) couple.
In one embodiment of this invention, when the activation of (i+1) bar sweep trace, the diode current flow that couples with (i+1) bar sweep trace, and building-out capacitor charged.
In one embodiment of this invention, when (i+1) bar sweep trace forbidden energy, close with the diode that (i+1) bar sweep trace couples, the building-out capacitor voltage level remains unchanged.
In one embodiment of this invention, each pixel cell comprises pixel electrode, and wherein pixel electrode couples second end and the building-out capacitor of on-off element.In one embodiment, when coupling the diode current flow of (i+1) bar sweep trace, corresponding building-out capacitor provides corresponding pixel electrode bucking voltage.
In one embodiment of this invention, building-out capacitor is made up of pixel electrode and the conductive material that constitutes the cathode terminal of diode.
In one embodiment of this invention, building-out capacitor is made up of pixel electrode and conductive structure.In one embodiment, the material of conductive structure is identical with the material of pixel electrode.In another embodiment, the material of conductive structure is identical with the material of sweep trace.In another embodiment, the material of conductive structure is identical with the material of data line.
Based on above-mentioned, the present invention's pel array by building-out capacitor setting and each dot structure in on-off element and diode be coupled to the ingenious configuration of two adjacent sweep traces respectively, make feed-trough voltage obtain compensation, and then the bad picture that the feedthrough effect is produced is improved.
State feature and advantage on the present invention and can become apparent for allowing, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
[description of drawings]
Figure 1A illustrates a kind of equivalent circuit diagram of pel array of available liquid crystal display panel.
Figure 1B is according to the drive waveforms figure that one of them dot structure illustrated that is coupled to i bar sweep trace among Figure 1A.
Fig. 2 illustrates the equivalent circuit diagram of the pel array of one embodiment of the invention.
Fig. 2 A illustrates another equivalent circuit diagram of the pel array of one embodiment of the invention.
Fig. 3 A～Fig. 6 A illustrates the schematic top plan view of four kinds of pel arrays of one embodiment of the invention respectively.
Fig. 3 B～Fig. 6 B is respectively the diagrammatic cross-section according to Fig. 3 A～Fig. 6 A section line A-A ', B-B ', C-C ' and D-D ' are illustrated.
Fig. 7 illustrates the drive waveforms figure of one embodiment of the invention.
[embodiment]
Fig. 2 illustrates the equivalent circuit diagram of the pel array of one embodiment of the invention.Please refer to Fig. 2, the pel array 200 of present embodiment comprises many sweep trace GL parallel to each other
I-1, GL
i, GL
I+1..., many data line DL parallel to each other and with sweep trace GL
I-1, GL
i, GL
I+1... and a plurality of dot structures 210 of coupling of data line DL.Wherein, sweep trace GL
I-1, GL
i, GL
I+1... and data line DL intersects each other, with the dot structure 210 that further defines these arrayed.
Specifically, each dot structure 210 of present embodiment comprises on-off element SW, pixel cell PIX, building-out capacitor C
CAnd diode D.Further say, with regard to each member in the i row dot structure 210, the control end E of on-off element SW
CAnd the first end E
1Couple i bar sweep trace GL respectively
iAnd data line DL wherein, pixel cell PIX couples the second end E of on-off element SW
2, and building-out capacitor C
CCouple the second end E of pixel cell PIX and on-off element SW
2, and the anode tap of diode D+and cathode terminal-couple respectively (i+1) bar sweep trace GL
I+1And building-out capacitor C
CIn like manner, can learn the configuration relation of each member in other row dot structures 210.
From the above, on-off element SW in each dot structure 210 and diode D are coupled to same sweep trace, but are coupled to two adjacent sweep traces respectively.
In the present embodiment, each on-off element SW for example is a thin film transistor (TFT), wherein the control end E of on-off element SW
CBe the grid of thin film transistor (TFT), and first, second end E of on-off element SW
1, E
2Two ends can be used as source electrode, the drain electrode of thin film transistor (TFT).In the following embodiments, main to describe by the on-off element SW that thin film transistor (TFT) was constituted, first, second end E wherein
1, E
2Two ends for example are first, second source/drain electrode.
The pel array 210 of present embodiment is applied in the display panels, and then pixel cell PIX comprises liquid crystal capacitance C
LCAs shown in Figure 2, the liquid crystal capacitance C of present embodiment
LCAn end be coupled to the second end E of on-off element SW
2(second source/drain electrode) and building-out capacitor C
C, its other end then is coupled to common voltage Vcom.
On the practice,, can in each pixel cell PIX, storage capacitors C be set further usually in order to promote the display quality of display panels
St, for example, present embodiment adopts storage capacitors C
StBe positioned at the design of grid top (Cs on gate).Specifically, with regard to each the storage capacitors C in the i row dot structure 210
St, the one end couples the second end E of on-off element SW
2(second source/drain electrode) and building-out capacitor C
C, and its other end is coupled to (i+1) bar sweep trace GL
I+1Yet the present invention does not limit the kenel of storage capacitors, in other embodiments, can adopt storage capacitors to be positioned at the design of common electrode top (Cs on common) yet.
Special one carry be, the diode D of present embodiment can realize by thin film transistor (TFT) T, shown in the equivalent circuit diagram of Fig. 2 A, wherein the grid of the source electrode of thin film transistor (TFT) T and one of drain among both person and thin film transistor (TFT) T couples.
The equivalent circuit diagram that is illustrated according to Fig. 2 and Fig. 2 A, the topological design of the pel array 200 of present embodiment can illustrate as Fig. 3 A～Fig. 6 A and Fig. 3 B～Fig. 6 B, and wherein Fig. 3 B～Fig. 6 B is respectively the diagrammatic cross-section according to Fig. 3 A～Fig. 6 A section line A-A ', B-B ', C-C ' and D-D ' are illustrated.In addition, the thin film transistor (TFT) that constitutes the diode D of present embodiment can be taked graphic middle T
A, T
B, T
CAnd T
DFour kinds of forms, but the present invention is not as limit.
In the present embodiment, liquid crystal capacitance C
LC(being illustrated in Fig. 2 and Fig. 2 A) can establish liquid crystal layer (not illustrating) by two electrode holders and be constituted, and one of them electrode can be coupled to the second end E of on-off element SW by setting in pixel cell PIX
2(second source/drain electrode) and building-out capacitor C
CPixel electrode 212 (for example Fig. 3 A, Fig. 4 A, Fig. 5 A and Fig. 6 A illustrate) realize that another electrode (not illustrating) is then for being coupled to the common electrode of common voltage Vcom in the upper plate (not illustrating).
By Fig. 3 A～Fig. 6 A as can be known, in order to form the control end E of on-off element SW
CThe conductive layer M1 of (grid) and in order to form the second end E of on-off element SW
2The conductive layer M2 of (second source/drain electrode) overlaps each other, thereby control end E
C(grid) and the second end E
2There is gate-to-drain stray capacitance (parasitic capacitor) C between (second source/drain electrode)
Gd
In addition, by Fig. 3 A and Fig. 3 B as can be known, thin film transistor (TFT) T
ABy contact hole H
AElectrically connect with conductive structure (being conductive layer M1), and conductive layer M1 and pixel electrode 212 form building-out capacitor C because of capacitive coupling between the two
C, the wherein material of conductive layer M1 and sweep trace GL
I-1, GL
i, GL
I+1Material identical.
And by Fig. 4 A and Fig. 4 B as can be known, thin film transistor (TFT) T
BBy contact hole H
BElectrically connect with conductive structure (being conductive layer ITO), and conductive layer ITO and pixel electrode 212 form building-out capacitor C because of capacitive coupling between the two
CWherein, the material of conductive layer ITO is also for constituting the material of pixel electrode 212.
Hold above-mentioned, by Fig. 5 A and Fig. 5 B as can be known, thin film transistor (TFT) T
CElectrically connect with conductive structure (being conductive layer M2), and conductive layer M2 and pixel electrode 212 form building-out capacitor C because of capacitive coupling between the two
C, wherein the material of conductive layer M2 is identical with the material of data line DL.Yet the layout that Fig. 5 A and Fig. 5 B are illustrated also can further be reduced to the form of Fig. 6 A and Fig. 6 B, that is thin film transistor (TFT) T
DBy the extra conductive structure that is provided with, and directly the conductive characteristic by its source/drain electrode and pixel electrode 212 capacitive coupling with formation building-out capacitor C
C, also can regard thin film transistor (TFT) T as
DDirectly with the anode tap that constitutes diode D+conductive material, the thin film transistor (TFT) T of present embodiment wherein
DSource/drain electrode and form the anode tap of diode D+conductive material can be constituted by conductive layer M2.
Need to prove that at this above-mentioned Fig. 3 A～Fig. 6 A and the layout that Fig. 3 B～Fig. 6 B is illustrated only illustrate present embodiment in order to convenient, and unrestricted the present invention.That is to say that the topological design of pel array of the present invention can also be other forms.Yet actual topological design should be decided on the demand of product, thereby does not illustrate one by one at this.
Fig. 7 illustrates the drive waveforms figure of one embodiment of the invention, and wherein only to illustrate the voltage waveform that i is listed as one of them pixel electrode 212 be example to Fig. 7.Please be simultaneously with reference to Fig. 2～Fig. 7, in the present embodiment, during t1, i bar sweep trace GL
iActivation, scanning voltage SG at this moment
iVoltage level be high level.Simultaneously, the data voltage V that transmitted of data line DL
DataCan be sent in the pixel electrode 212 by on-off element SW, and the action of charging.Wherein, the pixel voltage waveform such as the V of pixel electrode 212
PixelInstitute illustrates, wherein pixel voltage waveform V
PixelVoltage level be the voltage level of node N2 among Fig. 2.
Then, the moment that finishes during the t1, sweep trace GL
iStop activation, this moment is because of the gate-to-drain stray capacitance C in the dot structure 210
GdExistence, make the pixel voltage V of pixel electrode 212
PixelBe subjected to scanning voltage SG
iThe influence of negative edge and to a certain degree the voltage level of thereupon descending.As shown in Figure 7, pixel voltage V
PixelOff-line data voltage V
DataFeed-trough voltage (feed through voltage) Δ V
FT, claim that generally this phenomenon is feedthrough effect (feed through effect).
Yet present embodiment is at (i+1) bar sweep trace GL next
I+1The moment of activation is promptly during t2, with (i+1) bar sweep trace GL
I+1The diode D conducting that couples, and to building-out capacitor C
CCharge.At this moment, scanning voltage SG
I+1Rising edge can make the pixel voltage V of pixel electrode 212
PixelThe rising bucking voltage, wherein said bucking voltage and feed-trough voltage Δ V
FTNumerical value about equally.Thus, pixel voltage V
PixelJust return back to and be equal to data voltage V
Data
More specifically, treat (i+1) bar sweep trace GL
I+1During forbidden energy, promptly during t3, with (i+1) bar sweep trace GL
I+1The diode D that couples can present closed condition, and building-out capacitor C
CVoltage level remain unchanged.At this moment, scanning voltage SG
I+1Negative edge just can be to pixel voltage V
PixelImpact, and make pixel voltage V
PixelLevel remain unchanged substantially.So, couple sweep trace GL so far
I+1Diode D self closing to conduction period next time, pixel voltage V
PixelLevel just can remain unchanged substantially.
From the above, in the present embodiment, because of the feedthrough effect that feed-trough voltage caused can achieve a solution.In addition, when the size of display panels is big more, is subjected to resistance capacitance and postpones the influence of (RC delay) and the rising edge of scanning voltage and the amplitude of negative edge are not quite similar, and then panel feed-trough voltage everywhere is not quite similar.Yet, the feed-trough voltage that each bar sweep trace of present embodiment is caused when stopping activation can be immediately moving by the activation of next bar sweep trace and obtains equivalent in fact bucking voltage, thus make display panel everywhere the feedthrough effect that differs of occurrence degree achieve a solution.In brief, no matter the size of display panels why, and the pel array of present embodiment all can improve.
In sum, pel array of the present invention by building-out capacitor setting and each dot structure in the ingenious arrangement of on-off element and diode, can compensate feed-trough voltage.Thus, the unequal bad picture of film flicker, picture that is produced by the feedthrough effect just can obtain to improve significantly.
In the above-described embodiments, only the present invention has been carried out exemplary description, but those skilled in the art can carry out various modifications to the present invention after reading present patent application under the situation that does not break away from the spirit and scope of the present invention.
Claims (13)
1. pel array, it comprises multi-strip scanning line, many data lines and couples with described sweep trace and described data line and a plurality of dot structures of arrayed, it is characterized in that each dot structure in the i row dot structure comprises:
On-off element, its control end couples i bar sweep trace, and its first end couples wherein data line;
Pixel cell couples second end of described on-off element;
Building-out capacitor couples described pixel cell; And
Diode, its anode tap couples (i+1) bar sweep trace, and its cathode terminal couples described building-out capacitor.
2. pel array according to claim 1 is characterized in that, each pixel cell comprises:
Liquid crystal capacitance, one end couple described second end and the described building-out capacitor of described on-off element, and its other end couples common voltage.
3. pel array according to claim 2 is characterized in that, each pixel cell in the i row dot structure also comprises:
Storage capacitors, one end couple described second end and the described building-out capacitor of described on-off element, and its other end couples (i+1) bar sweep trace.
4. pel array according to claim 1 is characterized in that, each diode is a thin film transistor (TFT), and the grid of the source electrode of described thin film transistor (TFT) and one of drain among both person and described thin film transistor (TFT) couples.
5. pel array according to claim 1 is characterized in that, when the activation of (i+1) bar sweep trace, and the described diode current flow that couples with described (i+1) bar sweep trace, and building-out capacitor charged.
6. pel array according to claim 1 is characterized in that, when (i+1) bar sweep trace forbidden energy, closes with the described diode that described (i+1) bar sweep trace couples, and the building-out capacitor voltage level remains unchanged.
7. pel array according to claim 1 is characterized in that, each pixel cell comprises:
Pixel electrode couples described second end and the described building-out capacitor of described on-off element.
8. pel array according to claim 7 is characterized in that, when coupling the described diode current flow of described (i+1) bar sweep trace, the building-out capacitor of described correspondence provides the pixel electrode bucking voltage of described correspondence.
9. pel array according to claim 1 is characterized in that, described building-out capacitor is made up of pixel electrode and the conductive material that constitutes the described cathode terminal of described diode.
10. pel array according to claim 1 is characterized in that described building-out capacitor is made up of pixel electrode and conductive structure.
11. pel array according to claim 10 is characterized in that, the material of described conductive structure is identical with the material of described pixel electrode.
12. pel array according to claim 10 is characterized in that, the material of described conductive structure is identical with the material of described sweep trace.
13. pel array according to claim 10 is characterized in that, the material of described conductive structure is identical with the material of described data line.
Priority Applications (1)
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|---|---|---|---|
| CN 200910189925 CN101702065B (en) | 2009-09-01 | 2009-09-01 | Pixel array |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910189925 CN101702065B (en) | 2009-09-01 | 2009-09-01 | Pixel array |
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| Publication Number | Publication Date |
|---|---|
| CN101702065A CN101702065A (en) | 2010-05-05 |
| CN101702065B true CN101702065B (en) | 2011-07-13 |
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| CN 200910189925 Active CN101702065B (en) | 2009-09-01 | 2009-09-01 | Pixel array |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI459349B (en) * | 2012-05-16 | 2014-11-01 | Innocom Tech Shenzhen Co Ltd | Display devices and pixel driving methods |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105182643B (en) * | 2015-09-24 | 2019-04-09 | 深超光电（深圳）有限公司 | Base plate of array in active mode and display panel |
| CN106527006A (en) * | 2016-12-30 | 2017-03-22 | 惠科股份有限公司 | Pixel structure |
| CN109243391B (en) * | 2018-10-17 | 2020-07-10 | 深圳市华星光电技术有限公司 | Pixel driving circuit and display panel |
| CN110491326A (en) * | 2019-08-28 | 2019-11-22 | 深圳市华星光电半导体显示技术有限公司 | Pixel circuit, display panel and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991964A (en) * | 2005-12-30 | 2007-07-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and driving method thereof |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1991964A (en) * | 2005-12-30 | 2007-07-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and driving method thereof |
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| Title |
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| JP特开2003-186050A 2003.07.03 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI459349B (en) * | 2012-05-16 | 2014-11-01 | Innocom Tech Shenzhen Co Ltd | Display devices and pixel driving methods |
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