CN101770125A - Dual scanning line pixel array substrate - Google Patents
Dual scanning line pixel array substrate Download PDFInfo
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- CN101770125A CN101770125A CN201010000457A CN201010000457A CN101770125A CN 101770125 A CN101770125 A CN 101770125A CN 201010000457 A CN201010000457 A CN 201010000457A CN 201010000457 A CN201010000457 A CN 201010000457A CN 101770125 A CN101770125 A CN 101770125A
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Abstract
The invention provides a dual scanning line pixel array substrate, which comprises a substrate, a first conductive layer, a grid insulation layer, a semiconductor layer, a second conductive layer, a protective layer and a transparent electrode layer. The first conductive layer consists of a plurality of grids and a plurality of scanning lines. The grid insulation layer is covered on the first conductive layer. The semiconductor layer is arranged on the grid insulation layer; the semiconductor layer consists of a plurality of channel areas, a plurality of first common wires and a plurality of capacitance electrodes; and the first common wires are crossed with the scanning lines and connected with the capacitance electrodes. The second conductive layer is arranged on a part of the semiconductor layer and the grid insulation layer and consists of a plurality of sources, a plurality of drains and a plurality of data wires, wherein the first common wires are parallel to the data wires. The transparent electrode layer is electrically connected with each drain through each contact window of the protective layer; and the transparent electrode layer is overlapped with the protective layer and the capacitance electrodes of the semiconductor layer to form a storage capacitor.
Description
[technical field]
The present invention relates to a kind of array of display substrate, and particularly relate to a kind of dual scanning line pixel array substrate.
[background technology]
Along with the development of large scale display panel, in the middle of the pel array of display panels (pixelarray) structure, a kind of half source drive (half source driving is designated hereinafter simply as HSD) framework that is called as is arranged now.The HSD framework can be so that the number of data line reduces by half, so the price of source electrode driver (source driver) also can relatively reduce.In more detail, in the pel array of HSD framework, two adjacent sub-pixels (sub-pixel) are shared data lines, thereby get so that the number of data lines order reduces by half.
Though adopt the display panel of HSD framework can allow the driving port number of source electrode driver reduce by half, but because odd number of pixels and even number pixel in the same row pixel are connected with different sweep trace respectively, therefore the sweep trace quantity in the HSD framework doubles, so the image element array substrates of HSD framework is called dual scanning line pixel array substrate again.Thus, in the pel array of HSD framework, in order to keep the same frame (frame) frequency, source electrode driver reduces by half and can cause reduce by half the turnaround time of each pixel voltage level.Specifically, in the pel array of HSD framework in order to transmit common voltage (common voltage, Vcom) relation that common electrode doubles because of sweep trace, and the time of replying after making it be coupled only is general framework half, therefore be easy to generate transverse crosstalk (cross-talk), and influence the display quality of whole picture.
[summary of the invention]
The invention provides a kind of dual scanning line pixel array substrate, it can reduce the resistance value of shared distribution, solves the cross-talk phenomenon in the HSD framework.
The present invention proposes a kind of dual scanning line pixel array substrate, and it comprises substrate, first conductive layer, gate insulation layer, semiconductor layer, second conductive layer, protective seam and transparent electrode layer.First conductive layer is arranged on the substrate, and it constitutes a plurality of grids and multi-strip scanning line.Gate insulation layer is covered on first conductive layer.Semiconductor layer is arranged on the gate insulation layer, and semiconductor layer constitutes a plurality of channel regions, many first bridging lines and a plurality of capacitance electrode, and wherein channel region is positioned on the grid, and first bridging line and sweep trace intersect, and first bridging line is connected with capacitance electrode.Second conductive layer is arranged on part semiconductor layer and the gate insulation layer, and second conductive layer constitutes a plurality of source electrodes, a plurality of drain electrode and many data lines, and wherein each source electrode and each drain electrode are positioned at the both sides of each channel region, and first bridging line is parallel with data line.Protective seam covering gate insulation course, second conductive layer and semiconductor layer, wherein protective seam is provided with a contact hole in each drain electrode.Transparent electrode layer is arranged on the protective seam, and transparent electrode layer is electrically connected with each drain electrode by each contact hole, and each capacitance electrode of transparent electrode layer and protective seam and semiconductor layer is overlapping and constitute a storage capacitors.
In one embodiment of this invention, above-mentioned transparency conducting layer constitutes a plurality of pixel electrodes, and each pixel electrode is positioned at each capacitance electrode top, and only has protective seam between each pixel electrode and each capacitance electrode and constitute storage capacitors.
In one embodiment of this invention, the second above-mentioned conductive layer comprises that further many are intended data line, and it is overlapping and electric in parallel with each first bridging line that each intends data line, and respectively intend data line bit between the two adjacent pixel electrodes that are electrically connected with the different pieces of information line.
In one embodiment of this invention, above-mentioned transparency conducting layer further comprises a plurality of serial connection patterns, each is connected in series, and pattern is crossed over each data line and connection is positioned at the capacitance electrode of each data line both sides, and the capacitance electrode that is positioned at below the same row pixel electrode is connected in series each other to constitute one second bridging line.At this moment, protective seam can further have a plurality of openings, and opening is positioned at the overlapping of serial connection pattern and capacitance electrode, and each serial connection pattern connects two capacitance electrodes that lay respectively at same data line both sides by two openings.And second conductive layer can further comprise a plurality of anti-etching patterns, lays respectively between the serial connection pattern and capacitance electrode in each opening.
In one embodiment of this invention, the material of above-mentioned semiconductor layer comprises indium germanium zinc oxygen compound.
In one embodiment of this invention, above-mentioned semi-conductive resistivity is essentially 10
-3Ω-m.
In one embodiment of this invention, above-mentioned each capacitance electrode is along the periphery configuration of each pixel electrode.
In one embodiment of this invention, above-mentioned dual scanning line pixel array substrate further comprises one first shared bus and one second shared bus, be positioned at the periphery circuit region of dual scanning line pixel array substrate, wherein first shared bus is parallel with sweep trace, second shared bus is parallel with data line, first bridging line extends in the periphery circuit region and with first shared bus and is connected, and second bridging line extends in the periphery circuit region and with second shared bus and is connected.
The present invention proposes a kind of dual scanning line pixel array substrate in addition, and this dual scanning line pixel array substrate comprises many dual scanning lines, many data lines, a plurality of pixel, many first bridging lines and a plurality of capacitance electrodes.Many data lines and dual scanning line intersect vertically to constitute a plurality of pixel regions.A plurality of pixels lay respectively in the pixel region, and wherein each pixel has a pixel electrode and an active member respectively.Many first bridging lines are made of semiconductor, and first bridging line and data line are staggered and intersect vertically with dual scanning line, and first bridging line is electrically connected to each other.A plurality of capacitance electrodes are made of semiconductor, capacitance electrode is positioned at the pixel electrode below, each capacitance electrode and each pixel electrode constitute a storage capacitors, the capacitance electrode that is positioned at same row pixel electrode below is connected in series constituting one second bridging line each other along column direction, and first bridging line and second bridging line are electrically connected to each other.
In one embodiment of this invention, only have a protective seam between each above-mentioned pixel electrode and each capacitance electrode, and storage capacitors is made of pixel electrode, protective seam and capacitance electrode.
In one embodiment of this invention, above-mentioned dual scanning line pixel array substrate further comprises a plurality of serial connection patterns, wherein respectively be connected in series pattern and cross over the both sides of each data line and connect two capacitance electrodes that lay respectively at same data line both sides, and the capacitance electrode that is positioned at same row pixel electrode below is by serial connection pattern and serial connection each other.
In one embodiment of this invention; above-mentioned pixel comprises a protective seam; protective seam has a plurality of openings, and opening is positioned at the overlapping of serial connection pattern and capacitance electrode, and each serial connection pattern connects two capacitance electrodes that lay respectively at same data line both sides by two openings.
In one embodiment of this invention, above-mentioned dual scanning line pixel array substrate further comprises a plurality of anti-etching patterns, lays respectively between the serial connection pattern and capacitance electrode in each opening, and wherein anti-etching pattern and data line are same rete.
In one embodiment of this invention, above-mentioned semi-conductive material comprises indium germanium zinc oxygen compound.
In one embodiment of this invention, above-mentioned semi-conductive resistivity is essentially 10
-3Ω-m.
In one embodiment of this invention, above-mentioned each capacitance electrode is along the periphery configuration of each pixel electrode.
In one embodiment of this invention, above-mentioned dual scanning line pixel array substrate further comprises one first shared bus and one second shared bus, be positioned at the periphery circuit region of dual scanning line pixel array substrate, wherein first shared bus is parallel with dual scanning line, second shared bus is parallel with data line, first bridging line extends in the periphery circuit region and with first shared bus and is connected, and second bridging line extends in the periphery circuit region and with second shared bus and is connected.
Based on said structure; dual scanning line pixel array substrate of the present invention utilizes a material that belongs to same rete with the passage of active member to make capacitance electrode and bridging line; and capacitance electrode, protective seam and pixel electrode constitute storage capacitors; thereby the storage capacitors value is increased; capacitance electrode by the serial connection pixel makes bridging line constitute crisscross network in the viewing area, therefore can significantly reduce the resistance value of bridging line.Thus, can quicken the time that bridging line is replied level, reduce the transverse crosstalk phenomenon, stablize voltage data signal, promote the display quality of picture.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
[description of drawings]
Figure 1A is the vertical view of a kind of dual scanning line pixel array substrate in one embodiment of the invention.
Figure 1B is the equivalent circuit diagram of the several pixels in the dual scanning line pixel array substrate of Figure 1A.
Fig. 2 is the pixel layout synoptic diagram that is denoted as square frame II place in the dual scanning line pixel array substrate that further illustrates Figure 1A.
Fig. 3 A is along the diagrammatic cross-section of AA profile line in the dual scanning line pixel array substrate of Fig. 2.
Fig. 3 B is for being denoted as the partial enlarged drawing at B place in the dual scanning line pixel array substrate of Fig. 2.
Fig. 4 A is a kind of diagrammatic cross-section of Fig. 3 B along the IV-IV profile line.
Fig. 4 B is the another kind of diagrammatic cross-section of Fig. 3 B along the IV-IV profile line.
Fig. 5 A is the partial schematic diagram that viewing area and periphery circuit region have a common boundary in the dual scanning line pixel array substrate of one embodiment of the invention.
Fig. 5 B is for further illustrating the partial enlarged drawing at B place among Fig. 5 A.
Fig. 6 is the pixel layout synoptic diagram that illustrates a kind of dual scanning line pixel array substrate in one embodiment of the invention.
Fig. 7 is the diagrammatic cross-section of Fig. 6 along the AA profile line.
[embodiment]
Figure 1A is the vertical view of a kind of dual scanning line pixel array substrate in one embodiment of the invention.Please refer to Figure 1A, dual scanning line pixel array substrate 200 has a viewing area 200D and is positioned at the outer periphery circuit region 200P of viewing area 200D, shown in Figure 1A, dual scanning line pixel array substrate 200 comprises the multi-strip scanning line G of horizontal expansion, many data line D, a plurality of pixel 220 and a shared distribution 210 of longitudinal extension.In detail, data line D and sweep trace G intersect, and are positioned at each relative both sides of data line D and two pixel region 220R adjacent one another are and define in the 200D of viewing area, and 220 of each pixels lay respectively in each pixel region 220R.It should be noted that two adjacent sweep trace G are electrically connected with a therebetween row pixel 220, and the odd number of pixels 220 of same row is connected with sweep trace G wherein, and the even number pixel 220 of same row is connected with another sweep trace G.
For instance, sweep trace G1, G2 are connected with the therebetween first row R1 pixel 220, the odd number of pixels 220 of the first row R1 is connected with sweep trace G1, and the even number pixel 220 of the first row R1 is connected with sweep trace G2, and therefore the unit of such one group of sweep trace G1, G2 is called dual scanning line again.It should be noted that, shared distribution 210 comprises many first bridging line 210C longitudinally, and in certain embodiments, shared distribution 210 can further comprise many second horizontal bridging line 210R, these the second bridging line 210R and the first bridging line 210C intersect each other in the 200D of viewing area, and it is connected to each other in the intersection, make shared distribution 210 form a crisscross network, as represent the layout (layout) of shared distribution among the figure with thicker lines, can significantly reduce the resistance value of shared distribution 210 integral body thus, in other words, these second bridging line 210R and data line D are staggered, and these first bridging line 210C and dual scanning line intersect vertically, and those second bridging lines 210R is electrically connected with these first bridging lines 210C.
In addition, in the present embodiment, the first shared bus 210A and the second shared bus 210B around viewing area 200D more can be set in periphery circuit region 200P, wherein two first shared bus 210A lay respectively at top and the below of viewing area 200D, and two the first shared bus 210A connects the top of each first bridging line 210C respectively with terminal, and two second shared bus 210B lay respectively at the left of viewing area 200D and right-hand, and two second shared bus 210B connect left end and the right-hand member of each second bridging line 210R respectively.The second horizontal bridging line 210R further can be connected in series with the first bridging line 210C longitudinally by the first shared bus 210A and the second shared bus 210B, so can further reduce the resistance value of shared distribution 210.In addition, shown in Figure 1A, in the present embodiment, when dual scanning line pixel array substrate is applied to display panel, R, the G that is indicated in the pixel 220, B represent respectively in order to demonstrate redness, green and blue pixels, "+", "-" then represent positive-negative polarity respectively, therefore in the present embodiment, pixel in the viewing area is that the mode with dot matrix is driven, present embodiment only is an illustration usefulness, and the present invention does not limit Show Color and the type of drive when pixel is used in the image element array substrates.
Figure 1B is the equivalent circuit diagram of the several pixels in the dual scanning line pixel array substrate of Figure 1A, please refer to Figure 1A and Figure 1B, the pixel 220 that is connected with same data line D is positioned at the both sides of this data line D, and these two pixels 220 are to connect with different sweep trace G respectively, as sweep trace G (n) among the figure and sweep trace G (n+1).Have active member 222, capacitance electrode 226 and pixel electrode 224 in each pixel 220.Pixel electrode 224 is electrically connected to drain electrode 222D, receiving a data voltage, and formation one liquid crystal capacitance C between pixel electrode 224 and the counter electrode CF_Vcom above it
LCIn addition, these capacitance electrodes are connected to each other and form shared distribution and bestowed and use voltage TFT_Vcom altogether, formation and liquid crystal capacitance C between capacitance electrode 226 and the pixel electrode 224
LCA storage capacitors C in parallel
StSpecifically, adjacent capacitance electrode 226 intersects each other between pixel 220 and is connected to each other, thereby constitute the low shared distribution 210 of a resistance value, thereby under the HSD framework, the bad problem of demonstration that can avoid existing dual scanning line pixel array substrate to be caused because of the cross-talk phenomenon.Specifically, capacitance electrode 226 is positioned at pixel electrode 224 belows and constitutes a storage capacitors with pixel electrode 224, and capacitance electrode 226 cross over data line D each other transverse electric connect and constitute the second bridging line 210R, and vertically be electrically connected with the first bridging line 210C.
For being described in more detail characteristics of the present invention, Fig. 2 is the pixel layout synoptic diagram that is denoted as square frame II place in the dual scanning line pixel array substrate that further illustrates Figure 1A.Please refer to Fig. 2, is to be that example describes in detail with the secondary series R2 pixel 220 among Figure 1A in the present embodiment.As shown in Figure 2, pixel 220A lays respectively at the both sides of data line D2 with pixel 220B and is connected with data line D2.In more detail, pixel 220A comprises active member 222A, capacitance electrode 226A and pixel electrode 224A, and active member 222A comprises grid 222GA, passage 222CA, source electrode 222SA and drain electrode 222DA.On the other hand, pixel 220B comprises active member 222B, capacitance electrode 226B and pixel electrode 224B, and active member 222B comprises grid 222GB, passage 222CB, source electrode 222SB and drain electrode 222DB.As shown in Figure 2, in fact grid 222GA can be considered to be the part of sweep trace G4, and in fact grid 222GB can be considered to be the part of sweep trace G3, be arranged in one group of pixel 220 of Fig. 2 A left, source electrode 222SA is connected to identical data line D2 with source electrode 222SB, and pixel electrode 224A is connected with drain electrode 222DA to be scanned line G4 at active member 222A and is received from the data voltage that data line D2 transmits in opening, and pixel electrode 224B is connected the data voltage that is received from data line D2 transmission in the line G3 unlatching to be scanned at active member 222B with drain electrode 222DB.
In the running of reality, formed storage capacitors is in order to the level of the data voltage of stablizing active member pixel electrode that the down periods are written between pixel electrode and the capacitance electrode.Below further specify in the dual scanning line pixel array substrate of the present invention the formation kenel of the storage capacitors of pixel.
Fig. 3 A is along the diagrammatic cross-section of A1-A1 profile line and A2-A2 profile line in the dual scanning line pixel array substrate of Fig. 2.Please be simultaneously with reference to Fig. 2 and Fig. 3 A, be that representative describes with pixel 220A in the present embodiment, active member 222A is made of grid 222GA, gate insulation layer 230, passage 222CA, source electrode 222SA and drain electrode 222DA, wherein grid 222GA is connected with corresponding scanning line G4, gate insulation layer 230 cover gate 222GA, passage 222CA is positioned on the gate insulation layer 230 of grid 222GA top, and source electrode 222SA and drain electrode 222DA lay respectively at the both sides of passage 222CA.Below describe the formation and the rete relation of image element array substrates in detail.Image element array substrates comprises substrate 202, the first conductive layer M1, gate insulation layer I1, semiconductor layer S, the second conductive layer M2, protective seam I2 and transparent electrode layer T.Wherein, the first conductive layer M1 is arranged on the substrate 202, and grid 222GA and sweep trace G are made up of the first conductive layer M1.Gate insulation layer I1 is covered on the first conductive layer M1.Semiconductor layer S is arranged on the gate insulation layer I1, and part semiconductor layer S (as channel layer 222CA) is positioned on the grid 222GA of the first conductive layer M1, the semiconductor layer S of another part (as capacitance electrode 226A and the capacitance electrode 226B and the first bridging line 210C) then is to be arranged on the gate insulation layer I1, wherein the first bridging line 210C and sweep trace G intersect, and the first bridging line 210C is connected with capacitance electrode 226A, 226B.The second conductive layer M2 be arranged at part semiconductor layer S go up with gate insulation layer I2 on, and its have source electrode 222SA, drain 222DA and data line D, and the first bridging line 210C is parallel with data line D.On protective seam I2 covering gate insulation course I1, the second conductive layer M2 and the semiconductor layer S, and on the drain electrode 222DA of the second conductive layer M2, be provided with a contact hole W1.Transparent electrode layer T is arranged on the protective seam I2; part semiconductor layer S (as capacitance electrode 226A and capacitance electrode 226B) is positioned under the transparent electrode layer T; and transparent electrode layer T and protective seam I2 and part semiconductor S are overlapping and constitute a storage capacitors Cst, and transparent electrode layer T is electrically connected with the drain electrode 222DA of the second conductive layer M2 by the contact hole W1 on the protective seam I2.
In like manner, the formation of active member 222B and active member 222A are similar, but active member 222B is connected with sweep trace G3.And; in the present embodiment; pixel 220 has the protective seam 240 of a covering active member 222; and protective seam has a plurality of contact hole W; as contact hole W1, the W2 among the figure, and pixel electrode 224A, 224B connect with corresponding drain electrode 222DA, 222DB by corresponding contact window W1, W2 respectively.
Please continue the A with reference to Fig. 3, in pixel 220A, pixel electrode 224A covers capacitance electrode 226A, and constitutes a storage capacitors Cst with capacitance electrode 226A.What deserves to be mentioned is, capacitance electrode 226A, capacitance electrode 226B and passage 222CA, passage 222CB are same rete, all formed by semiconductor layer S, in other words, when making pixel 220, capacitance electrode 226A, 226B can be patterned with in the fabrication steps with passage 222CA, 222CB, therefore do not need additionally to increase processing procedure and form capacitance electrode 226 and shared distribution 210.Specifically; in pixel 220A; owing to only have single protective seam 240 between pixel electrode 224A and the capacitance electrode 226A; therefore can promote the storage capacitors value of pixel 220A; in other words; in the present embodiment, the storage capacitors Cst that is made of pixel electrode 224A, protective seam 240 and capacitance electrode 226A helps to stablize the level of the data voltage that is write in the pixel electrode 224 because of having bigger storage capacitors value, and better display quality can be provided.In addition, in the operation of reality, shared distribution 210 can be bestowed a negative voltage, makes the unit storage capacitors value of the storage capacitors Cst that pixel electrode 224 and capacitance electrode 226 constituted reach maximization thus.
In order to clearly demonstrate characteristics of the present invention, below further specify in the dual scanning line pixel array substrate of the present invention the formation kenel of shared distribution.
Please continue with reference to Fig. 2, in the present embodiment, capacitance electrode 226A is along the periphery configuration of pixel electrode 224A, capacitance electrode 226B then disposes along the periphery of pixel electrode 224B, the capacitance electrode 226A of same row pixel 220 and capacitance electrode 226B be connected in series each other along the bearing of trend of each sweep trace G then constitute the second horizontal bridging line 210R, and, to be connected in series each other along the bearing of trend of each data line D with the capacitance electrode 226A of delegation's pixel 220 and capacitance electrode 226B and then constitute the first bridging line 210C longitudinally, as first bridging line 210C1～210C3 among the figure, and each first bridging line 210C is between the two adjacent pixels 220 that are electrically connected with different pieces of information line D, for example the first bridging line 210C2 the pixel 220B that is electrically connected with data line D2 and with pixel 220A that data line D3 is electrically connected between.It should be noted that in the present embodiment that the composition of the first bridging line 210C for example composition with capacitance electrode 226 is identical, just the first bridging line 210C directly utilizes serial connection to constitute with the capacitance electrode 224 of delegation's pixel 220.
Specifically, capacitance electrode 226, the second bridging line 210R and the first bridging line 210C for example comprise semi-conductor layer, and the composition of semiconductor layer is identical with the composition of passage 222C.In the present embodiment, semi-conductive material for example is indium germanium zinc oxygen compound (In-Ga-Zn-O, IGZO), because this kind indium germanium zinc oxygen compound has the advantage of high carrier mobility and low resistance, therefore can further reduce the resistance value of shared distribution 210, its resistivity for example is essentially 10
-3Ω-m.When during as the passage 222C of active member 222, giving active member 222 and have higher firing current (I with this kind indium germanium zinc oxygen compound
OnCurrent) and than the advantage of low driving voltage.
What this need specify be, capacitance electrode 226 of the present invention is same rete with the passage 222C (222CA, 222CB) of active member 222, be different from first conductive layer that constitutes sweep trace G and grid 222G owing to constitute the rete of capacitance electrode 226, and also be different from second conductive layer of composition data line D, source electrode 222S and drain electrode 222D, therefore can be with the direct serial connection and form longitudinally the first bridging line 210C and form the second horizontal bridging line 210R of the capacitance electrode among the 200D of viewing area 226 by easy wire jumper mode.
For how the capacitance electrode that clearly demonstrates same row pixel of the present invention is connected in series constituting second bridging line each other along the bearing of trend of each sweep trace, Fig. 3 B that hereinafter will arrange in pairs or groups, Fig. 4 A and Fig. 4 B describe the formation kenel of second bridging line in detail.
Fig. 3 B is for being denoted as the partial enlarged drawing at B place in the dual scanning line pixel array substrate of Fig. 2, Fig. 4 A is a kind of diagrammatic cross-section of Fig. 3 B along the IV-IV profile line.Please be simultaneously with reference to Fig. 3 B and Fig. 4 A, the second bridging line 210R has a string map interlinking case 250 with each data line D confluce, the data line D2 among the figure for example, wherein each serial connection pattern 250 is crossed over the both sides of each data line D respectively, and each serial connection pattern 250 connects two capacitance electrode 226A, 220B that lay respectively at same data line D both sides, even therefore the second bridging line 210R and data line D are interlaced, the second bridging line 210R and data line D are electrically insulated each other.
Particularly; the protective seam 240 of pixel 220 has a plurality of opening H; these openings H is positioned at serial connection pattern 250 and the overlapping of capacitance electrode 226A and the overlapping that is connected in series pattern 250 and capacitance electrode 226B; to expose capacitance electrode 226A, 226B respectively, therefore be connected in series pattern 250 and be connected with capacitance electrode 226A and capacitance electrode 226B with opening H2 by opening H1 respectively.In addition, on making, serial connection pattern 250 can utilize with the mask processing procedure with pixel electrode 224A, 224B and be made, in other words, serial connection pattern 250 can be same rete with pixel electrode 224A, 224B, and therefore being connected in series pattern 250 need not additionally increase processing procedure with original process-compatible.
Consider when making the opening H of protective seam 240; capacitance electrode 226 may suffer damage because of the etch process of protective seam 240; therefore the deviser also can set up an anti-etching pattern 260 between serial connection pattern 250 and capacitance electrode 226 on some are used, shown in Fig. 4 B.Fig. 4 B is the another kind of diagrammatic cross-section of Fig. 3 B along the IV-IV profile line.Please refer to Fig. 4 B, dual scanning line pixel array substrate 200 further comprises a plurality of anti-etching patterns 260, wherein between the serial connection pattern 250 and capacitance electrode 226 of each anti-etching pattern 260 in each opening H, on the practice, anti-etching pattern 260 can be made with the mask processing procedure with source electrode, drain electrode, data line utilization, in other words, anti-etching pattern 260 can be same rete with source electrode, drain electrode, data line.Can make certain connection between capacitance electrode 226A, 226B and the serial connection pattern 250 by anti-etching pattern 260.
What deserves to be mentioned is, except allowing the second horizontal bridging line 210R by the way with the first bridging line 210C is connected to each other in the 200D of viewing area longitudinally, thereby constitute outside the crisscross network, the shared distribution of present embodiment also can be respectively outside the viewing area around the first shared bus 210A and the second shared bus 210B as being illustrated among Figure 1A are set, shown in Figure 1A, the first shared bus 210A is parallel with sweep trace G and be positioned at periphery circuit region 200P, and the second shared bus 210B is parallel with data line D and be positioned at periphery circuit region 200P, and the common voltage that can allow shared distribution 210 be transmitted thus can be transmitted more swimmingly.
Specifically, Fig. 5 A is the concrete schematic layout pattern of the first half in the dual scanning line pixel array substrate that further illustrates Figure 1A, and Fig. 5 B is for further illustrating the partial enlarged drawing at B place among Fig. 5 A.Please be simultaneously with reference to Fig. 5 A and Fig. 5 B, in the dual scanning line pixel array substrate 200 of present embodiment, direction along data line D stretches out from viewing area 200D with above-mentioned first bridging line 210C1～210C6 longitudinally, and in periphery circuit region 200P, utilize the first shared bus 210A that the top of each first bridging line 210C1～210C6 is connected in series each other, because it is to be different from the rete that constitutes sweep trace G that the present invention constitutes the rete of first bridging line 210C1～210C6, and constitute the rete of first bridging line 210C1～210C6 and constitute between the rete of sweep trace G and have a gate insulation layer 230, therefore when passing through sweep trace G, first bridging line 210C1～210C6 need not utilize the wire jumper design, can further reduce by the resistance value of first bridging line 210C1～210C6 thus, help to reduce the resistance value of shared distribution 210 integral body.
In like manner, utilize notion with Fig. 5 A and Fig. 5 B, can further utilize another first shared bus 210A that the above-mentioned end of the first bridging line 210C longitudinally is connected in series each other, perhaps according to above-mentioned notion, equally can be in the both sides of viewing area 200D, utilize left end or the right-hand member of the second shared bus 210B (being illustrated in Figure 1A), the second bridging line 210R that each is horizontal to be connected in series each other, and constitute the first shared bus 210A and the second shared bus 210B as shown in Figure 1A.
Except aforesaid dual scanning line pixel array substrate 200, Fig. 6 further illustrates a kind of dual scanning line pixel array substrate according to another embodiment of the present invention, implements aspect in order to the another kind that above-mentioned design concept is described.Hereinafter no longer repeat to introduce the element that occurred in the previous embodiment, and omitted relevant description.As shown in Figure 6, the dual scanning line pixel array substrate 300 of present embodiment further is provided with one and intends data line 330 between two adjacent and pixels 220 that different pieces of information line D is connected, wherein intending data line 330 is to utilize with the mask processing procedure with data line D to come patterning, and the two belongs to same rete and forms identical.
Fig. 7 is the diagrammatic cross-section of Fig. 6 along the AA profile line.Please be simultaneously with reference to Fig. 6 and Fig. 7, particularly, in the dual scanning line pixel array substrate 300 of present embodiment, it is overlapping and in parallel with its electricity with each first bridging line 320 that each intends data line 330, thus, can further reduce the resistance value of bridging line integral body, in the limited time, to reply level, avoid the cross-talk phenomenon, promote display quality.
In sum, the generation type of dual scanning line pixel array substrate storage capacitors of the present invention can obtain bigger storage capacitors value and the level of the data voltage that helps to stablize in the pixel electrode and write, and utilize a material that belongs to same rete with the passage of active member to form shared distribution, and constitute crisscross signal delivery network by the capacitance electrode that connects pixel, thus, can reduce the resistance value of shared distribution integral body.Therefore, dual scanning line pixel array substrate of the present invention not only has the effect that the data line of HSD framework reduces by half, more can stablize voltage data signal, have low-resistance netted shared distribution and can be coupled back answer fast in the limited time, effectively solve the problem of transverse crosstalk, and then promote the display quality of whole picture.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any affiliated technical field technician, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (19)
1. dual scanning line pixel array substrate, it is characterized in that: this dual scanning line pixel array substrate comprises:
One substrate;
One first conductive layer is arranged on this substrate, and it constitutes a plurality of grids and multi-strip scanning line;
One gate insulation layer is covered on this first conductive layer;
Semi-conductor layer, be arranged on this gate insulation layer, this semiconductor layer constitutes a plurality of channel regions, many first bridging lines and a plurality of capacitance electrode, and wherein this channel region is positioned on this grid, this first bridging line and this sweep trace intersect, and this first bridging line is connected with this capacitance electrode;
One second conductive layer, be arranged on this semiconductor layer of part and this gate insulation layer, this second conductive layer constitutes a plurality of source electrodes, a plurality of drain electrode and many data lines, and wherein respectively this source electrode is positioned at the respectively both sides of this channel region with this drain electrode respectively, and this first bridging line is parallel with this data line;
One protective seam covers this gate insulation layer, this second conductive layer and this semiconductor layer, and wherein this protective seam respectively is being provided with a contact hole in this drain electrode; And
One transparent electrode layer is arranged on this protective seam, and this transparent electrode layer is electrically connected with this drain electrode respectively by this contact hole respectively, and respectively this capacitance electrode of this transparent electrode layer and this protective seam and this semiconductor layer is overlapping and constitute a storage capacitors.
2. dual scanning line pixel array substrate as claimed in claim 1; it is characterized in that: this transparency conducting layer constitutes a plurality of pixel electrodes; respectively this pixel electrode is positioned at respectively this capacitance electrode top, and this pixel electrode and respectively only have this protective seam between this capacitance electrode and constitute this storage capacitors respectively.
3. dual scanning line pixel array substrate as claimed in claim 2, it is characterized in that: this second conductive layer comprises that further many are intended data line, respectively should intend data line with respectively this first bridging line is overlapping and electric in parallel, and respectively should intend data line bit between the two adjacent pixel electrodes that are electrically connected with the different pieces of information line.
4. dual scanning line pixel array substrate as claimed in claim 2, it is characterized in that: this transparency conducting layer further comprises a plurality of serial connection patterns, respectively this serial connection pattern is crossed over respectively this data line and is connected and is positioned at respectively this capacitance electrode of these data line both sides, and this capacitance electrode that is positioned at same row pixel electrode below is connected in series each other to constitute one second bridging line.
5. dual scanning line pixel array substrate as claimed in claim 4; it is characterized in that: this protective seam further has a plurality of openings; this opening is positioned at the overlapping of this serial connection pattern and this capacitance electrode, and each serial connection pattern connects two these capacitance electrodes that lay respectively at same data line both sides by two openings.
6. dual scanning line pixel array substrate as claimed in claim 5 is characterized in that: this second conductive layer further comprises a plurality of anti-etching patterns, lays respectively between this serial connection pattern and this capacitance electrode in each opening.
7. dual scanning line pixel array substrate as claimed in claim 1 is characterized in that: the material of this semiconductor layer comprises indium germanium zinc oxygen compound.
8. dual scanning line pixel array substrate as claimed in claim 1 is characterized in that: this semi-conductive resistivity is 10
-3Ω-m.
9. dual scanning line pixel array substrate as claimed in claim 1 is characterized in that: respectively this capacitance electrode is along the respectively periphery configuration of this pixel electrode.
10. dual scanning line pixel array substrate as claimed in claim 1, it is characterized in that: this dual scanning line pixel array substrate further comprises one first shared bus and one second shared bus, be positioned at the periphery circuit region of this dual scanning line pixel array substrate, wherein this first shared bus is parallel with this sweep trace, this second shared bus is parallel with this data line, this first bridging line extends in this periphery circuit region and with this first shared bus and is connected, and this second bridging line extends in this periphery circuit region and with this second shared bus and is connected.
11. a dual scanning line pixel array substrate is characterized in that: this dual scanning line pixel array substrate comprises:
Many dual scanning lines;
Many data lines intersect vertically to constitute a plurality of pixel regions with this dual scanning line;
A plurality of pixels lay respectively in this pixel region, and wherein respectively this pixel has a pixel electrode and an active member respectively;
Many first bridging lines are made of semiconductor, this first bridging line and this data line is staggered and intersect vertically with this dual scanning line, and this first bridging line is electrically connected to each other; And
A plurality of capacitance electrodes, constituted by semiconductor, this capacitance electrode is positioned at this pixel electrode below, respectively this capacitance electrode constitutes a storage capacitors with this pixel electrode respectively, this capacitance electrode that is positioned at same row pixel electrode below is connected in series constituting one second bridging line each other along column direction, and this first bridging line and this second bridging line are electrically connected to each other.
12. dual scanning line pixel array substrate as claimed in claim 11 is characterized in that: this pixel electrode and respectively only have a protective seam between this capacitance electrode respectively, and this storage capacitors is made of this pixel electrode, this protective seam and this capacitance electrode.
13. dual scanning line pixel array substrate as claimed in claim 11, it is characterized in that: this dual scanning line pixel array substrate further comprises a plurality of serial connection patterns, wherein respectively this serial connection pattern is crossed over the both sides of this data line respectively and is connected two these capacitance electrodes that lay respectively at same data line both sides, and this capacitance electrode that is positioned at same row pixel electrode below is by this serial connection pattern and be connected in series each other.
14. dual scanning line pixel array substrate as claimed in claim 13; it is characterized in that: this pixel comprises a protective seam; this protective seam has a plurality of openings; this opening is positioned at the overlapping of this serial connection pattern and this capacitance electrode, and each serial connection pattern connects two these capacitance electrodes that lay respectively at same data line both sides by two openings.
15. dual scanning line pixel array substrate as claimed in claim 14, it is characterized in that: this dual scanning line pixel array substrate further comprises a plurality of anti-etching patterns, lay respectively between this serial connection pattern and this capacitance electrode in each opening, wherein this anti-etching pattern and this data line are same rete.
16. dual scanning line pixel array substrate as claimed in claim 11 is characterized in that: this semi-conductive material comprises indium germanium zinc oxygen compound.
17. dual scanning line pixel array substrate as claimed in claim 11 is characterized in that: this semi-conductive resistivity is 10
-3Ω-m.
18. dual scanning line pixel array substrate as claimed in claim 11 is characterized in that: respectively this capacitance electrode is along the respectively periphery configuration of this pixel electrode.
19. dual scanning line pixel array substrate as claimed in claim 11, it is characterized in that: this dual scanning line pixel array substrate further comprises one first shared bus and one second shared bus, be positioned at the periphery circuit region of this dual scanning line pixel array substrate, wherein this first shared bus is parallel with this dual scanning line, this second shared bus is parallel with this data line, this first bridging line extends in this periphery circuit region and with this first shared bus and is connected, and this second bridging line extends in this periphery circuit region and with this second shared bus and is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010000457A CN101770125A (en) | 2010-01-11 | 2010-01-11 | Dual scanning line pixel array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010000457A CN101770125A (en) | 2010-01-11 | 2010-01-11 | Dual scanning line pixel array substrate |
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|---|---|
| CN101770125A true CN101770125A (en) | 2010-07-07 |
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