CN113035888B

CN113035888B - Electronic device

Info

Publication number: CN113035888B
Application number: CN202110259971.8A
Authority: CN
Inventors: 王睦凯; 黄国有; 陈茂松
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-08-21
Filing date: 2021-03-10
Publication date: 2023-06-02
Anticipated expiration: 2041-03-10
Also published as: CN113035888A

Abstract

An electronic device comprises a substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel structures, a gate switching line and a switching structure. The pixel structures arranged in the same row are electrically connected with the data lines on different sides in sequence. The film layer where the gate patch cord is located is the same as the film layer where the data line is located. The grid patch cord passes through the pixel structure and the data line to form a cross-line area on the substrate. The film layer of the transfer structure is different from the film layer of the gate transfer line and the data line. In the cross-line region, one of the gate transfer line and the data line crosses over the other of the gate transfer line and the data line through an active element of the transfer structure or the pixel structure.

Description

Electronic device

Technical Field

The present invention relates to an electronic device, and more particularly, to an electronic device with a switching structure.

Background

With the progress of technology, large-sized panels are being developed toward narrow-frame designs. Currently, TGP (Tracking Gate-line in Pixel) narrow frame technology is mostly adopted to further reduce the width of the panel frame.

However, TGP bypasses the active elements of the pixel and is typically a trace design with multiple turns. Thus, the resistance-capacitance load (RC loading) of the panel is increased by 1.5-2 times, and the problems of coupling with adjacent data lines or gate/drain capacitance (Cgd) are easily generated, thereby influencing the quality of signal transmission in the electronic device. For example, the display effect of the display panel or the sensitivity of the touch panel may be affected. Therefore, how to plan the layout, reduce the coupling effect between the circuits, and avoid the increase of the load of the resistor and the capacitor has become an issue of interest for the current research staff.

Disclosure of Invention

The invention provides an electronic device, which is designed to help reduce resistance-capacitance load and avoid coupling between circuits so as to improve the quality of the electronic device.

At least one embodiment of the invention provides an electronic device, which comprises a substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel structures, a gate switching line and a switching structure. The plurality of gate lines are disposed on the substrate and extend along a first direction. The plurality of data lines are arranged on the substrate and extend along a second direction, wherein the first direction intersects with the second direction. The plurality of pixel structure arrays are arranged on the substrate. Each pixel structure is surrounded by two adjacent gate lines and two adjacent data lines and comprises an active element, wherein the pixel structures arranged in the same row along the second direction are electrically connected with the data lines on different sides in sequence. The gate adapter wire is arranged on the substrate and extends along the second direction. The gate transfer line is electrically connected with one of the gate lines, the film layer where the gate transfer line is located is the same as the film layer of the data lines, and in a top view of the electronic device, the gate transfer line penetrates through one of the pixel structures and between the data lines electrically connected with the pixel structures to form a cross line area on the substrate. The transfer structure is arranged on the substrate, and the film layer where the transfer structure is positioned is different from the film layer where the gate transfer line and the data line are positioned. In the cross-line region, one of the gate transfer line and the data line crosses over the other of the gate transfer line and the data line through an active element of the transfer structure or the pixel structure.

In an embodiment of the present invention, in the above-mentioned line crossing area, the data line crosses the gate patch cord through a switching structure, the switching structure extends along the first direction, two ends of the switching structure are respectively connected to the data line and the active element of the pixel structure, and in a top view of the electronic device, the switching structure intersects the gate patch cord.

In an embodiment of the invention, the active device of the pixel structure further includes a longitudinal conductive line, wherein the longitudinal conductive line is disposed on the substrate, two ends of the longitudinal conductive line are connected to the switching structure and the active device, and the gate switching line is located between the data line and the longitudinal conductive line in a top view of the electronic device.

In an embodiment of the invention, the electronic device further includes a first insulating layer, wherein the first insulating layer covers the gate line, and has a first via and a second via, the first via overlaps the data line, the second via overlaps the longitudinal wire in a top view of the electronic device, wherein the first via and the second via expose a portion of the switching structure, respectively, the data line is connected to the switching structure through the first via, and the switching structure is connected to the longitudinal wire through the second via.

In an embodiment of the invention, the pixel structure further has a pixel electrode, the pixel electrode and the data line are electrically connected to the drain electrode and the source electrode on opposite sides of the active device, respectively, and the pixel electrode is spaced apart from the gate adaptor line in a top view of the electronic device.

In an embodiment of the invention, the electronic device further includes a second insulating layer, the second insulating layer covers the data line and the gate adapter line, and has a third via hole, wherein the third via hole exposes a portion of the active device, and the pixel electrode covers a portion of a surface of the third via hole to be connected to the active device.

In an embodiment of the invention, the second insulating layer includes a lower insulating layer conformally disposed on the first insulating layer and an upper insulating layer disposed on the lower insulating layer.

In an embodiment of the invention, the second insulating layer has a single-layer structure.

In an embodiment of the invention, in the above-mentioned crossover region, the gate patch cord spans the data line through a switching structure, the switching structure extends along the second direction, two ends of the switching structure are respectively connected to the gate patch cord, and in a top view of the electronic device, the switching structure intersects the data line.

In an embodiment of the invention, the data line has a main line segment and a branch line segment, the main line segment extends along the second direction, two ends of the branch line segment are respectively connected to the main line segment and the active element of the pixel structure, and in a top view of the electronic device, the switching structure intersects with the branch line segment.

In an embodiment of the invention, the electronic device further includes a first insulating layer, the first insulating layer covers the gate line and has a plurality of fourth through holes, and in a top view of the electronic device, the fourth through holes overlap the gate patch line, wherein the fourth through holes expose a portion of the switching structure, the gate patch line at one end of the switching structure is connected to the switching structure through one of the fourth through holes, and the switching structure is connected to the gate patch line at the other end of the switching structure through another one of the fourth through holes.

In an embodiment of the invention, the electronic device further includes a common electrode, and the common electrode is disposed on the substrate and overlaps at least the data line, the gate adapter line and the adapter structure in a top view of the electronic device.

In an embodiment of the invention, the active device of the pixel structure is a top gate thin film transistor and includes a semiconductor channel layer, and the data line crosses the gate patch cord through the switching structure and the semiconductor channel layer in the cross-line region.

In an embodiment of the invention, the semiconductor channel layer includes a first line segment, a curved line segment and a second line segment, the first line segment and the second line segment extend along a second direction, two ends of the curved line segment are adjacent to the first line segment and the second line segment, in a top view of the electronic device, the first line segment overlaps the data line, and the curved line segment intersects the gate adapter line.

In an embodiment of the invention, the gate line further includes an extension structure, the extension structure extends from the gate line along the second direction, and the gate patch cord is electrically connected to the gate line through the extension structure. The length of the extension structure is 1/10-1/2 of the length of the pixel structure.

In an embodiment of the invention, the electronic device further includes an interlayer dielectric layer sandwiched between the gate adaptor line and the gate line, and having a through hole, wherein the gate adaptor line covers a surface of the through hole to be connected to the extension structure.

In an embodiment of the invention, the electronic device further includes a third insulating layer, wherein the third insulating layer covers the data line and the gate adapter line and has a trench. The trench extends along the second direction, and is located between the data line and the gate adaptor line in a top view of the electronic device.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic top view of an electronic device according to a first embodiment of the present invention.

Fig. 2A is an enlarged schematic view of the crossover region CR of an embodiment in the electronic device of fig. 1.

FIG. 2B is a schematic diagram of one embodiment of a cross-section along section line A' -A-B-C in the electronic device of FIG. 2A.

FIG. 2C is a schematic diagram of another embodiment of a cross-section along section line A' -A-B-C in the electronic device of FIG. 2A.

Fig. 3A is an enlarged schematic view of an overline region CR of another embodiment in the electronic device of fig. 1.

Fig. 3B is a schematic cross-sectional view of the electronic device of fig. 3A along the line A-A'.

Fig. 4A is a schematic top view of an electronic device according to a second embodiment of the invention.

Fig. 4B is an enlarged schematic view of the crossover region CR in the electronic device of fig. 4A.

Fig. 5A is a schematic top view of an electronic device according to a third embodiment of the invention.

Fig. 5B is a schematic cross-sectional view of the electronic device of fig. 5A along the section line A-A'.

Fig. 6 is a schematic top view of an electronic device according to a fourth embodiment of the invention.

Reference numerals illustrate:

10. 10A, 10A1, 10A2, 10B, 20, 30, 40: electronic device

100: substrate board

102: buffer layer

110: gate patch cord

120. 200, 300: switching structure

130: longitudinal wire

140: a first insulating layer

150. 150': second insulating layer

152: lower insulating layer

154: upper insulating layer

160: third insulating layer

310: semiconductor channel layer

312: first line segment

314: curved line section

316: second line segment

320: extension structure

AA: active region

B: blue sub-pixel

CH: semiconductor pattern

COM: common electrode

CR: crossover region

CS: conduction structure

D1: first direction

D2: second direction

DE: drain electrode

DL, DL1, DL2: data line

DLa: main line segment

DLb: branch line segment

G: green sub-pixel

GE: grid electrode

GI: gate insulating layer

GL: gate line

ILD: interlayer dielectric layer

M1: first conductor layer

M2: second conductor layer

PE: pixel electrode

R: red sub-pixel

SE: source electrode

SP: pixel structure

T1 and T2: active device

TH: through hole

TR: groove(s)

VIA1: first through hole

VIA2: second through hole

VIA3: third through hole

VIA4: fourth through hole

Detailed Description

In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" or "overlying" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between the elements.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "section" discussed below could be termed a second element, component, region, layer, or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well as "at least one" unless the context clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Moreover, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "above" can encompass both an orientation of above and below.

As used herein, "about" includes both the value and an average value within an acceptable deviation of the particular value as determined by one of ordinary skill in the art, taking into account the particular number of measurements and errors associated with the measurements (i.e., limitations of the measurement system) in question. For example, "about" may mean within one or more standard deviations of the values, or within ±30%, ±20%, ±10%, ±5%. Further, "about" as used herein may select a more acceptable deviation range or standard deviation depending on the optical, etching, or other properties, and may not apply to all properties with one standard deviation.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations in the shape of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area shown or described as being flat may generally have rough and/or nonlinear features. Furthermore, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a schematic top view of an electronic device according to a first embodiment of the present invention. For convenience of explanation, the positions of the insulating layers are omitted in fig. 1.

Referring to fig. 1, the electronic device 10 includes a substrate 100, a plurality of gate lines GL, a plurality of data lines DL, a plurality of pixel structures SP, and a gate switching line 110. The substrate 100 may have an active area AA and a peripheral area (not shown) located outside the active area AA. In the present embodiment, the material of the substrate 100 may include glass or other suitable materials, but the present invention is not limited thereto. The gate line GL is disposed on the substrate 100 and extends along a first direction D1. The data line DL is disposed on the substrate 100 and extends along a second direction D2 intersecting the first direction D1.

The plurality of pixel structures SP are arrayed on the substrate 100. In other words, the pixel structures SP may be arrayed along the first direction D1 and the second direction D2, wherein the first direction D1 may be understood as a lateral direction and the second direction D2 may be understood as a longitudinal direction. Therefore, the lateral and longitudinal directions described in the following embodiments can be regarded as the first direction D1 and the second direction D2 in fig. 1, respectively. In the present embodiment, each pixel structure SP is surrounded by two adjacent gate lines GL and two adjacent data lines DL. For example, the pixel structures SP aligned in a row along the first direction D1 are sandwiched between two gate lines GL; the pixel structures SP aligned in a row along the second direction D2 are sandwiched between two data lines DL. Therefore, the pixel structures SP of the same column and the pixel structures SP of the same row described in the following embodiments can be respectively regarded as the pixel structures SP arranged along the first direction D1 and the pixel structures SP arranged along the second direction D2 in fig. 1.

Each pixel structure SP may include an active device T1 and a pixel electrode PE connected to the active device T1, wherein the active device T1 is electrically connected to the corresponding gate line GL and the data line DL. In this embodiment, the pixel structures SP arranged in the same row along the second direction D2 can be electrically connected to the data lines DL on different sides in sequence. For example, the active devices T1 of the same row of pixel structures SP may be electrically connected to the data line DL1 on a first side (e.g., right side of fig. 1) and the data line DL2 on a second opposite side (e.g., left side of fig. 1) in a staggered manner. In some embodiments, in the pixel structures SP arranged in multiple rows along the first direction D1, the active devices T1 of the pixel structures SP in a single row may be electrically connected to the data lines DL1 on the first side thereof, and the active devices T1 of the pixel structures SP in a double row may be electrically connected to the data lines DL2 on the second side thereof, but the invention is not limited thereto.

In some embodiments, the plurality of pixel structures SP may include a plurality of red sub-pixels R, a plurality of green sub-pixels G, and a plurality of blue sub-pixels B, which are respectively arranged along the second direction D2. For example, taking the data line DL1 as an example in fig. 1, in the case that the data line DL1 is located between the same row of blue sub-pixels B and the same row of red sub-pixels R, the data line DL1 can be alternately electrically connected to the blue sub-pixels B and the red sub-pixels R; taking the data line DL2 as an example in fig. 1, in the case that the data line DL2 is located between the same row of green sub-pixels G and the same row of blue sub-pixels B, the data line DL2 may be alternately electrically connected to the green sub-pixels G and the blue sub-pixels B, and one skilled in the art may adjust the arrangement and connection relationship between the data line DL and the pixel structure SP according to the design requirement, which is not limited in the present invention.

In this embodiment, the pixel electrode PE and the data line DL can be electrically connected to the drain and the source on opposite sides of the active layer of the active device T1, respectively. For example, the active device T1 may be a transistor having a gate electrode connected to one of the gate lines GL, a source electrode connected to one of the data lines DL, and a drain electrode connected to the pixel electrode PE. In addition, in order to avoid a short circuit between the gate line GL and the data line DL, the gate line GL and the data line DL may be formed of different film layers, and one or more insulating layers may be interposed between the gate line GL and the data line DL.

The gate adaptor line 110 is disposed on the substrate 100 and extends along the second direction D2. In the present embodiment, the gate adaptor line 110 may be parallel to the data line DL. For example, the gate adaptor line 110 and the data line DL may be line patterns parallel to each other or may have zigzag patterns parallel to each other, but the invention is not limited thereto. In fig. 1, the gate patch cord 110 is located between the data line DL1 and the pixel structure SP immediately adjacent to the dummy frame, for example, and the gate patch cord 110 is not directly connected to the pixel structure SP. In the top view of the substrate 100, the gate patch cord 110 directly spans the connection path between the active device T1 and the data line DL1 of the pixel structure SP. In some embodiments, the pixel electrode PE may not overlap the gate adaptor line 110 in a top view of the substrate 100. For example, the pixel electrode PE is separated from the gate adaptor line 110 by a distance, but the invention is not limited thereto. In other embodiments, the pixel electrode PE may also overlap the gate adaptor line 110.

The gate adaptor line 110 and the data line DL may be located in the same layer. In the embodiment, the gate adapter line 110 may be electrically connected to one of the gate lines GL, and the film layer where the gate line GL is located may be located in a different film layer from the gate adapter line 110 and the data line DL. The active device T1 may be connected to the gate switching line 110 through one of the gate lines GL. Accordingly, the signal of the gate of the active device T1 can be transferred to the gate line GL by the gate switching line 110, and then be input to the gate by the gate line GL. In some embodiments, in order to transfer a signal from the gate transfer line 110 to the gate line GL, a conductive structure (e.g., a conductive structure CS indicated as a dummy frame) may be disposed between the corresponding gate transfer line 110 and the gate line GL. Thus, the signal of the gate of the active device T1 is transferred to the gate line GL through the gate switching line 110 via the conductive structure CS, and then transferred to the gate through the gate line GL.

In some embodiments, the signal of the gate of the active device T1 is, for example, a signal output from a driving circuit (not shown) located in the peripheral region. In some embodiments, the driving circuit may be located at one end of the gate adaptor line 110 and one end of the data line DL. The gate patch cord 110 and the data line DL can directly receive the signal provided by the driving circuit, and the gate line GL can receive the signal corresponding to the gate patch cord 110 through the corresponding conductive structure CS. In this way, the electronic device 10 can meet the requirement of a narrow frame design without having to provide a circuit or related circuit for transmitting signals at both ends of the first direction D1, and the contour of the electronic device 10 is not limited. For example, the electronic device 10 may have a non-rectangular outline as viewed in a top view of the substrate 100. In some embodiments, other longitudinal signal lines (not shown) may be further included in the electronic device 10, and the longitudinal signal lines may not be used to transfer signals required by the gate lines GL, but be input with a direct current potential. For example, the longitudinal signal line may not be connected to any gate line GL, but may be applied to the realization of touch or other functions.

In fig. 1, the gate adapter line 110 may penetrate between one of the pixel structures SP and the data line DL1 electrically connected to the pixel structure SP to form a cross-line region CR on the substrate 100. More specifically, in the flying lead region CR, the electronic device 10 further includes a transfer structure (described in detail below) disposed on the substrate 100, wherein the film layer of the transfer structure is different from the film layer of the gate transfer line 110 and the data line DL1, so that in the flying lead region CR, one of the gate transfer line 110 and the data line DL1 can cross the other of the gate transfer line 110 and the data line DL1 through the transfer structure or the active element T1 of the pixel structure SP, and therefore, the number of signal routing turns can be reduced through the transfer structure in the flying lead region CR, and problems such as increased resistance-capacitance load, adverse effects caused by coupling between lines, etc. can be avoided, and further, functions (e.g. image display, touch sensing, etc.) executed by the electronic device are improved. In other embodiments, the configuration of the switching structure may be adjusted according to different designs or process requirements, which will be described later.

Hereinafter, an embodiment of the transfer structure applicable to the above-described embodiment will be exemplified, but the present invention is not limited to the following embodiment.

FIG. 2A is an enlarged schematic view of an overline region CR of an embodiment in the electronic device of FIG. 1; FIG. 2B is a schematic diagram of one embodiment of a cross-section along section line A' -A-B-C in the electronic device of FIG. 2A; FIG. 2C is a schematic diagram of another embodiment of a cross-section along section line A' -A-B-C in the electronic device of FIG. 2A. Fig. 2A corresponds to the cross-line region CR of fig. 1. It should be noted that fig. 2A to 2C use the element numbers and part of the contents of the embodiment of fig. 1, in which the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. The description of the omitted parts will be referred to the foregoing embodiments and will not be repeated here.

Referring to fig. 2A and fig. 2B, the data line DL1 of the electronic device 10A can be connected to the active device T1 through the switching structure 120 crossing the gate switching line 110. In the present embodiment, the switching structure 120 extends along the first direction D1, for example, and two ends of the switching structure 120 are respectively connected to the data line DL1 and the active device T1 of the pixel structure SP. In this way, the via structure 120 and the gate via 110 have intersections in the top view of the substrate 100, and thus form the crossover region CR described in fig. 1. The film layer of the transfer structure 120 of the present embodiment is the same as that of the gate line GL, for example, and the material of the transfer structure 120 may be the same as that of the gate line GL, but the present invention is not limited thereto.

In this embodiment, the active device T1 of the pixel structure SP may further have a longitudinal conductive line 130. The longitudinal conductive line 130 is disposed on the substrate 100, and two ends of the longitudinal conductive line 130 can be connected to the switching structure 120 and the active device T1 of the pixel structure SP, respectively. In the top view of the substrate 100, the gate adaptor line 110 is located between the data line DL1 and the vertical conductive line 130, for example.

For clarity of explanation of the film relationships of the components in the electronic device, the description will be given with reference to fig. 2A and 2B. Referring to fig. 2A and fig. 2B, the active device T1 includes, for example: gate electrode GE, semiconductor pattern CH (as a channel layer), source electrode SE, and drain electrode DE. In the present embodiment, the active device T1 is illustrated as a bottom gate structure, but the invention is not limited thereto. The gate electrode GE of the active device T1 may be electrically connected to a corresponding gate line GL, and the gate line GL may be electrically connected to a corresponding gate switching line 110 through the conductive structure CS. The gate electrode GE and the gate line GL belong to the same layer, for example. The semiconductor pattern CH is disposed above the gate electrode GE, for example. The source electrode SE and the drain electrode DE are disposed above the semiconductor pattern CH, for example. In the present embodiment, the longitudinal conductive line 130 may be regarded as an extension of the source SE, but the present invention is not limited thereto. In the embodiment, the gate line GL and the transfer structure 120 are located in the first conductive layer M1, and the data line DL1 and the gate transfer line 110 are located in the second conductive layer M2, but the invention is not limited thereto. In addition, a first insulating layer 140 may be further included between the first conductive layer M1 and the second conductive layer M2. The first insulating layer 140 may cover the gate line GL and the transfer structure 120, and has a first VIA hole VIA1 and a second VIA hole VIA2. As shown in fig. 2A, the first VIA hole VIA1 overlaps the data line DL1, and the second VIA hole VIA2 overlaps the vertical conductive line 130 as the source SE extension, wherein the first VIA hole VIA1 and the second VIA hole VIA2 respectively expose a portion of the switching structure 120. In this way, the data line DL1 located in the second conductive layer M2 may be connected to the VIA structure 120 of the first conductive layer M1 below by penetrating through the conductive structure of the first VIA hole VIA1, and the VIA structure 120 located in the first conductive layer M1 may be connected to the vertical conductive line 130 of the second conductive layer M2 above by penetrating through the conductive structure of the second VIA hole VIA2. Therefore, the signal of the data line DL1 of the second conductive layer M2 can be transferred to the longitudinal conductive line 130 of the second conductive layer M2 and the source SE of the active device T1 of the pixel structure SP through the switching structure 120 of the first conductive layer M1. Accordingly, even if the data line DL1 and the gate patch cord 110 are located in the same layer, the data line DL1 can cross the gate patch cord 110 through the switching structure 120 in the crossover region CR, so that the number of turns in the routing design of the gate patch cord 110 can be reduced, and the problems of increasing the load of the resistor and the capacitor, generating adverse effects caused by coupling between the lines, and the like can be avoided, thereby improving the functions executed by the electronic device.

As shown in fig. 2B, the electronic device 10A1 of the present embodiment may further include a second insulating layer 150. The second insulating layer 150 covers the data line DL1, the gate adaptor line 110, the vertical conductive line 130, and the active device T1 of the pixel structure SP, for example. In this embodiment, the second insulating layer 150 may have a third VIA hole VIA3, the third VIA hole VIA3 may expose a portion of the active device T1, and the pixel electrode PE may cover a portion of the surface of the third VIA hole VIA3 to be connected to the active device T1.

The second insulating layer 150 may have a single-layer or multi-layer structure. For example, as shown in fig. 2B, the second insulating layer 150 includes, for example, a lower insulating layer 152 and an upper insulating layer 154, wherein the lower insulating layer 152 may be conformally disposed on the first insulating layer 140, and the upper insulating layer 154 may be disposed on the lower insulating layer 152. In some embodiments, the lower insulating layer 152 may serve as a passivation layer (passivation layer), and the upper insulating layer 154 may serve as a planarization layer, but the invention is not limited thereto.

On the other hand, compared to the second insulating layer 150 of the electronic device 10A1 of fig. 2B, the second insulating layer 150' of the electronic device 10A2 of fig. 2C is illustrated as a single-layer structure. The second insulating layer 150 'may be an oxide layer, and the material of the second insulating layer 150' may be the same as that of the lower insulating layer 152 of fig. 2B, but the present invention is not limited thereto.

Referring to fig. 2A and 2B, the electronic device 10 may further include a common electrode COM. The common electrode COM is disposed on the active area AA of the substrate 100, for example, and overlaps at least the data line DL1, the gate transfer line 110, the transfer structure 120, and the active element T1 of the pixel structure SP in the top view of the substrate 100. In some embodiments, the common electrode COM may be a common electrode for connecting a panel or implementing a touch function. In some embodiments, in the case that the electronic device further has a touch signal line (TP trace, not shown), the common electrode COM may also have a plurality of common electrodes COM, and gaps exist between the plurality of common electrodes COM to expose the touch signal line, which may be applied to implementation of touch or other functions. For example, the plurality of common electrodes COM may be spaced apart from each other by about 2.0 μm to about 8.0 μm with the touch signal line as a center.

The electronic device 10 may also include a third insulating layer 160. The third insulating layer 160 covers the common electrode COM and the second insulating layer 150. In some embodiments, the third insulating layer 160 is interposed between the common electrode COM and the pixel electrode PE to separate the common electrode COM from the pixel electrode PE. In some embodiments, the third insulating layer 160 may be a passivation layer (passivation layer), but the invention is not limited thereto.

FIG. 3A is an enlarged schematic view of an overline region CR of another embodiment in the electronic device of FIG. 1; fig. 3B is a schematic cross-sectional view of the electronic device of fig. 3A along the line A-A'. Fig. 3A corresponds to the cross-line region CR of fig. 1. It should be noted that, fig. 3A and fig. 3B use the element numbers and part of the content of the embodiment of fig. 2A, where the same or similar numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted. The description of the omitted parts will be referred to the foregoing embodiments and will not be repeated here.

Unlike the above-mentioned flying lead region CR of the electronic device 10A in fig. 2A, the switching structure 120 extending along the first direction D1 is used as a relay station for signal transmission of the data line DL1, and the flying lead region CR of the electronic device 10B in the present embodiment is used as a relay station for signal transmission of the gate switching line 110 through the switching structure 200 extending along the second direction D2. Referring to fig. 3A, in the electronic device 10B of the present embodiment, the gate patch cord 110 can cross the data line DL1 through the patch structure 200. In the present embodiment, the interposer 200 extends along the second direction D2, and two ends of the interposer 200 are connected to the gate interposer 110 respectively. In this way, the transfer structure 200 and the data line DL1 have intersections in the planar view of the substrate 100, and the crossover region CR is formed.

In the present embodiment, the data line DL1 may include a main line segment DLa and a branch line segment DLb. The main line segment DLa extends along the second direction D2 and is located between two adjacent rows of pixel structures SP; the branch line segment DLb extends from the main line segment DLa along the first direction D1 and the second direction D2, and two ends of the branch line segment DLb are respectively connected to the main line segment DLa and the active element T1 of the pixel structure SP. For example, in the top view of the substrate 100, the branch line DLb spans the interposer fabric 200. That is, the branch line segment DLb has an intersection with the switching structure 200, and the gate switching line 110 crosses the branch line segment DLb of the data line DL1 through the switching structure 200.

Referring to fig. 3A and 3B, in the present embodiment, the switching structure 200 is located, for example, in the first conductive layer M1, and the main line segment DLa, the branch line segment DLb, and the gate switching line 110 are located, for example, in the second conductive layer M2. In this way, the signal of the data line DL1 can be transferred to the second conductive layer M2, and the gate patch cord 110 can transfer the signal to the first conductive layer M1 through the patch structure 200 at the intersection with the data line DL1, and then transfer the signal to the second conductive layer M2 to cross the data line DL1.

Referring to fig. 3B, the cross-sectional view of the VIA structure 200 further includes a plurality of fourth VIA holes VIA4 and a first insulating layer 140 covering the gate line GL. As shown in fig. 3A, the fourth VIA4 overlaps the gate transfer line 110 and exposes a portion of the transfer structure 200. In this way, the gate patch cord 110 at one end of the patch cord 200 may be connected to the patch cord 200 through one of the conductor structures penetrating through the fourth VIA4, so that the signal of the gate patch cord 110 is jumped from the second conductor layer M2 to the first conductor layer M1. In addition, the VIA structure 200 may be connected to the gate patch cord 110 at the other end of the VIA structure 200 through another conductor structure penetrating through the fourth VIA hole VIA4, so that the signal of the gate patch cord 110 is jumped from the first conductor layer M1 to the second conductor layer M2. That is, both ends of the VIA structure 200 may be connected to the gate VIA 110 by a conductor structure penetrating the fourth VIA4. Therefore, the data line DL1 and the gate pad line 110 may be located in the same layer, and a signal of the gate pad line 110 may be transferred to the gate pad line 110 located at the other end through one end of the pad structure 200. In addition, the routing design of the gate patch cord 110 can reduce the number of turning points, so as to avoid the problems of increased resistance-capacitance load, adverse effect caused by coupling between lines, and the like, thereby improving the functions executed by the electronic device.

FIG. 4A is a schematic top view of an electronic device according to a second embodiment of the invention; fig. 4B is an enlarged schematic view of the crossover region CR in the electronic device of fig. 4A. Fig. 4B corresponds to the cross-line region CR of fig. 4A. It should be noted that, fig. 4A and fig. 4B use the reference numerals and part of the contents of the embodiment of fig. 2A, where the same or similar reference numerals are used to denote the same or similar elements, and descriptions of the same technical contents are omitted. The description of the omitted parts will be referred to the foregoing embodiments and will not be repeated here. For convenience of description, fig. 4A and 4B omit positions of the pixel electrodes.

Referring to fig. 4A and 4B, the electronic device 20 of the second embodiment is different from the electronic device 10 of the first embodiment in that the active device T1 of the electronic device 10 is illustrated as a bottom gate structure, the active device T2 of the electronic device 20 is illustrated as a top gate structure, and the data line DL1 is connected to the semiconductor channel layer 310 of the active device T2 through the switching structure 300. For example, the active device T2 of the pixel structure SP may include a semiconductor channel layer 310, and in the cross-line region CR, the data line DL1 may cross the gate transfer line 110 through the transfer structure 300 and the semiconductor channel layer 310.

In this embodiment, the active device T2 of the pixel structure SP includes, for example: a semiconductor channel layer 310, a data electrode (as a source or drain) and a gate electrode. The semiconductor channel layer 310 is disposed on the substrate 100. The gate insulating layer covers the semiconductor channel layer 310, the gate electrode is disposed on the gate insulating layer (e.g., the gate insulating layer GI shown in fig. 5B), and the gate electrode overlaps the semiconductor channel layer 310 in a top view of the substrate 100. An interlayer dielectric layer covers the gate electrode and insulates the gate electrode and the data electrode from each other (e.g., an interlayer dielectric layer ILD shown in fig. 5B). The data electrode (source/drain electrode) is electrically connected to the semiconductor channel layer 310. The gate electrode of the active device T2 is electrically connected to a corresponding gate line GL, and the gate line GL may be connected to the gate adaptor line 110 through the conductive structure CS.

In this embodiment, in order to transfer signals from the data line DL1 to the semiconductor channel layer 310, the switching structure 300 may be disposed between the corresponding data line DL1 and the semiconductor channel layer 310. For example, the via structure 300 may penetrate the interlayer dielectric layer and the gate insulating layer. That is, the film layer of the switching structure 300 is between the film layer of the data line DL1 and the film layer of the semiconductor channel layer 310.

More specifically, the semiconductor channel layer 310 may include a first line segment 312, a curved line segment 314, and a second line segment 316, where the first line segment 312 and the second line segment 316 extend along a second direction D2, for example, and two ends of the curved line segment 314 are adjacent to the first line segment 312 and the second line segment 316. In the present embodiment, the curved section 314 is, for example, U-shaped, but the present invention is not limited thereto. In other embodiments, the shape of the curved line segment 314 may also be adjusted according to design requirements. In the top view of the substrate 100, the first line segment 312 overlaps the data line DL1, for example, and the curved line segment 314 has an intersection with the gate adaptor line 110. In addition, the first line segment 312 is connected to the interposer 300 with respect to an end of the adjacent curved line segment 314, and the second line segment 316 is connected to the active device T2 with respect to an end of the adjacent curved line segment 314. In this way, the signal of the data line DL1 can be transferred to the first line segment 312 through the switching structure 300, and sequentially transferred to the active device T2 through the curved line segment 314 and the second line segment 316. Therefore, the data line DL1 and the gate pad line 110 are located in the same layer, and the signal of the data line DL1 can be transferred to the active device T2 of the pixel structure SP across the gate pad line 110 via the pad structure 300. In addition, the routing design of the gate patch cord 110 can reduce the number of turning points, so as to avoid the problems of increased resistance-capacitance load, adverse effect caused by coupling between lines, and the like, and further improve the functions (such as image display, touch sensing, and the like) executed by the electronic device.

FIG. 5A is a schematic top view of an electronic device according to a third embodiment of the invention; fig. 5B is a schematic cross-sectional view of the electronic device of fig. 5A along the section line A-A'. It should be noted that, fig. 5A and fig. 5B use the reference numerals and part of the contents of the embodiments of fig. 4A and fig. 4B, where the same or similar reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. The description of the omitted parts will be referred to the foregoing embodiments and will not be repeated here. For convenience of description, fig. 5A and 5B omit positions of the pixel electrodes.

Referring to fig. 5A and 5B, compared with the electronic device 20 of fig. 4A, the gate line GL of the electronic device 30 of the embodiment further has an extension structure 320 extending along the second direction D2, and the conductive structure CS is disposed at one end of the extension structure 320 away from the gate line GL, i.e. the gate interposer 110 is connected to one end of the extension structure 320 at one end of the interposer region CR through the conductive structure CS, and the other end of the extension structure 320 is connected to the gate line GL. In this embodiment, the film layer of the extension structure 320 is the same as the film layer of the gate line GL. For example, as shown in fig. 5B, the buffer layer 102, the gate insulating layer GI, the interlayer dielectric layer ILD and the gate adaptor line 110 may be sequentially disposed on the substrate 100, wherein the extension structure 320 and the gate line GL are, for example, disposed on a side of the interlayer dielectric layer ILD near the gate insulating layer GI, but the invention is not limited thereto. As shown in fig. 5A, the extension structure 320 extends from the gate line GL to the middle area of the pixel structure SP along the second direction D2. For example, the length of the extension structure 320 may be about 1/10 to 1/2 of the length of the pixel structure SP. In some embodiments, the length of the extension structure 320 may be equivalent to 1/2 of the length of the pixel structure SP, but the present invention is not limited thereto.

In the present embodiment, the gate adaptor line 110 may be electrically connected to the gate line GL through the extension structure 320. For example, as shown in fig. 5B, an interlayer dielectric layer ILD may be interposed between the gate electrode adaptor line 110 and the gate line GL, the interlayer dielectric layer ILD may have a through hole TH, and a portion of the gate electrode adaptor line 110 may cover a surface of the through hole TH to serve as the conductive structure CS, but the invention is not limited thereto. Accordingly, the gate adaptor line 110 may be connected to the extension structure 320. In other words, the signal of the gate electrode of the active device T2 can be sequentially transferred to the extension structure 320 and the gate line GL by the gate transfer line 110, and then be input to the gate electrode by the gate line GL. In this way, the conductive structure CS can be flexibly disposed, and the conductive structure CS is not necessarily disposed at the intersection of the gate interposer 110 and the gate line GL. In addition, the pattern of the extension structure 320 and the position of the gate adapter 110 connected to the extension structure 320 can be adjusted according to the process consideration, so as to avoid the problem of loading effect (or non-uniform line width) caused by too close distance between the conductive structures or the conductive structures of different lines.

Fig. 6 is a schematic top view of an electronic device according to a fourth embodiment of the invention. It should be noted that, fig. 6 uses reference numerals and some contents of elements in the embodiment of fig. 1, where the same or similar reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. The description of the omitted parts will be referred to the foregoing embodiments and will not be repeated here.

Referring to fig. 6, the electronic device 40 of the fourth embodiment is different from the electronic device 10 of the first embodiment in that the electronic device 40 further has an insulating layer covering the data line DL and the gate electrode patch cord 110, and the insulating layer has a trench TR.

In the present embodiment, the trench TR extends along the gate transfer line 110 and the data line DL. The projection of the trench TR on the substrate 100 is located between the projection of the gate transfer line 110 on the substrate 100 and the projection of the data line DL on the substrate 100. For example, the sidewalls of the trench TR are separated from the sides of the gate and data lines 110 and DL, respectively, by a distance, for example, and the lower limit of the distance is preferably 2.0 μm, preferably 3.0 μm. The upper limit of the distance is preferably 6.0. Mu.m, more preferably 5.0. Mu.m. In some embodiments, the trench TR may be spaced apart from the gate adaptor line 110 and the data line DL by about 2 μm to 6 μm, respectively. It should be noted that the trench implementation may be adjusted according to design requirements, and the present invention is not limited thereto.

For example, taking the embodiment of fig. 2B as an example, the trench TR may be located within the second insulating layer 150. In some embodiments, the depth of trench TR may correspond to the film thickness of upper insulating layer 154. In some embodiments, trench TR may extend from upper insulating layer 154 into lower insulating layer 152. For example, the depth of the trench TR may be greater than the film thickness of the upper insulating layer 154 and less than the film thickness of the lower insulating layer 152. In other embodiments, the depth of trench TR may be less than the film thickness of upper insulating layer 154. In addition, taking the embodiment of fig. 2C as an example, the trench TR may be located in the second insulating layer 150'. In some embodiments, the depth of the trench TR may correspond to the film thickness of the second insulating layer 150'. In some embodiments, the trench TR may extend from the second insulating layer 150' into the first insulating layer 140. For example, the depth of the trench TR may be greater than the film thickness of the second insulating layer 150' and less than the film thickness of the first insulating layer 140. In other embodiments, the depth of the trench TR may be smaller than the film thickness of the second insulating layer 150'.

In some embodiments, the common electrode COM covers the surface of the trench TR. Therefore, the shielding (shielding) of the interference between the gate patch cord 110 and the data line DL can be performed to reduce the adverse effect caused by the coupling between the lines. For example, the common electrode COM covers the surface of the trench TR and the trench TR is located between the gate adaptor line 110 and the data line DL, so that the electric field generated by the gate adaptor line 110 is shielded and not coupled to the data line DL, which can ensure that the data line DL maintains a certain level of output voltage, thereby improving functions (such as display, touch sensing, etc.) performed by the electronic device.

In summary, the electronic device of the present invention can make one of the gate adapter and the data line cross the other of the gate adapter and the data line through the active device of the switching structure or the pixel structure in the cross-line area by disposing the switching structure. In this way, the problems of increased load of resistor and capacitor, adverse effect caused by coupling between lines, etc. can be avoided, and the functions (such as image display, touch sensing, etc.) executed by the electronic device can be further improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An electronic device, comprising:

a substrate;

a plurality of gate lines disposed on the substrate and extending in a first direction;

a plurality of data lines disposed on the substrate and extending along a second direction, wherein the first direction intersects the second direction;

a plurality of pixel structures arranged on the substrate in an array, wherein each pixel structure is surrounded by two adjacent gate lines and two adjacent data lines and comprises an active element, and the pixel structures arranged in the same row along the second direction are electrically connected with the data lines on different sides in sequence;

the grid transfer line is arranged on the substrate and extends along the second direction, the grid transfer line is electrically connected with one of the grid lines, the film layer where the grid transfer line is positioned is the same as the film layer where the data lines are positioned, and in a top view of the electronic device, the grid transfer line penetrates through one of the pixel structures and between the data lines electrically connected with the pixel structures to form a line crossing area on the substrate; and

a transfer structure disposed on the substrate, wherein a film layer of the transfer structure is different from a film layer of the gate transfer line and the data line, one of the gate transfer line and the data line spans the other of the gate transfer line and the data line through the transfer structure or the active element of the pixel structure in the cross line region,

Wherein in the flying lead region, the data line crosses the gate patch cord through the patch structure,

the switching structure extends along the first direction, two ends of the switching structure are respectively connected with the data line and the active element of the pixel structure, and in a top view of the electronic device, the switching structure is intersected with the grid switching line.

2. The electronic device of claim 1, wherein the active element of the pixel structure further comprises:

and the longitudinal wires are arranged on the substrate, two ends of each longitudinal wire are connected with the switching structure and the active element, and in a top view of the electronic device, the grid switching wire is positioned between the data wire and the longitudinal wires.

3. The electronic device of claim 2, further comprising:

the first insulating layer covers the grid line and is provided with a first through hole and a second through hole, the first through hole is overlapped with the data line in a top view of the electronic device, the second through hole is overlapped with the longitudinal wire, the first through hole and the second through hole respectively expose a part of the switching structure, the data line is connected to the switching structure through the first through hole, and the switching structure is connected to the longitudinal wire through the second through hole.

4. The electronic device of claim 1, wherein the pixel structure further has a pixel electrode electrically connected to the drain and the source on opposite sides of the active element, respectively, and

in a top view of the electronic device, the pixel electrode is spaced apart from the gate adaptor line.

5. The electronic device of claim 3, further comprising:

the second insulating layer covers the data line and the gate transfer line and is provided with a third through hole, wherein the third through hole exposes a part of the active element, the pixel structure is further provided with a pixel electrode, the pixel electrode and the data line are respectively and electrically connected to the drain electrode and the source electrode on two opposite sides of the active element, and the pixel electrode covers part of the surface of the third through hole so as to be connected to the active element.

6. The electronic device of claim 5, wherein the second insulating layer comprises a lower insulating layer conformally disposed on the first insulating layer and an upper insulating layer disposed on the lower insulating layer.

7. The electronic device according to claim 5, wherein the second insulating layer has a single-layer structure.

8. The electronic device of claim 1, further comprising:

the third insulating layer covers the data line and the gate adapter line, the third insulating layer is provided with a groove, the groove extends along the second direction, and in a top view of the electronic device, the groove is located between the data line and the gate adapter line.

9. An electronic device, comprising:

a substrate;

wherein in the flying lead region, the gate patch cord spans the data line through the patch structure,

the transfer structure extends along the second direction, two ends of the transfer structure are respectively connected with the grid transfer line, and in a top view of the electronic device, the transfer structure is intersected with the data line.

10. The electronic device of claim 9, wherein the data line has a main line segment and a branch line segment, the main line segment extends along a second direction, two ends of the branch line segment are respectively connected to the main line segment and the active element of the pixel structure, and the switching structure intersects the branch line segment in a top view of the electronic device.

11. The electronic device of claim 10, further comprising:

The first insulating layer covers the gate line and is provided with a plurality of fourth through holes, the fourth through holes are overlapped with the gate patch cord in a top view of the electronic device, a part of the switching structure is exposed by the fourth through holes, the gate patch cord at one end of the switching structure is connected to the switching structure through one of the fourth through holes, and the switching structure is connected to the gate patch cord at the other end of the switching structure through the other one of the fourth through holes.

12. The electronic device of claim 1 or claim 9, further comprising:

and a common electrode disposed on the substrate and overlapping at least the data line, the gate transfer line, and the transfer structure in a plan view of the electronic device.

13. An electronic device, comprising:

a substrate;

the active element of the pixel structure is a top gate thin film transistor and comprises a semiconductor channel layer, and the data line crosses the gate switching line through the switching structure and the semiconductor channel layer in the crossover region.

14. The electronic device of claim 13, wherein the semiconductor channel layer comprises a first line segment, a curved line segment, and a second line segment, the first line segment and the second line segment extending along the second direction, two ends of the curved line segment being adjacent to the first line segment and the second line segment,

in a top view of the electronic device, the first line segment overlaps the data line, and the curved line segment intersects the gate patch cord.

15. The electronic device of claim 13, wherein the gate line further comprises an extension structure extending from the gate line in the second direction, the gate interposer being electrically connected to the gate line through the extension structure,

the length of the extension structure is 1/10-1/2 of the length of the pixel structure.

16. The electronic device of claim 15, further comprising:

and the interlayer dielectric layer is clamped between the gate transfer line and the gate line and is provided with a through hole, wherein the gate transfer line covers the surface of the through hole so as to be connected to the extension structure.