CN107037650B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN107037650B CN107037650B CN201710260996.3A CN201710260996A CN107037650B CN 107037650 B CN107037650 B CN 107037650B CN 201710260996 A CN201710260996 A CN 201710260996A CN 107037650 B CN107037650 B CN 107037650B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention discloses an array substrate, a display panel and a display device.A data outgoing line which is not overlapped with a scanning signal line is arranged, so that parasitic capacitance formed between the scanning signal line and the data outgoing line is avoided, and further, the interference on data voltage transmitted by the data outgoing line is avoided; and the data outgoing line is connected with the data line so as to transmit data voltage for the data line through the data outgoing line, and when the data line transmits the data voltage to the pixel unit corresponding to the scanning signal line scanned currently, the number of parasitic capacitance interfering the data voltage is greatly reduced, the interference of the parasitic capacitance to the data voltage is improved, and the display effect of the display device is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
The performance of the array substrate, which is one of the important components of the display device, directly affects the display effect of the display device. The array substrate has a complex structure, and generally includes a plurality of scan signal lines and a plurality of data lines crossing each other and insulated from each other. When the display scanning is carried out, the scanning driving circuit scans the scanning signal lines, and simultaneously when data is input, the data driving structure provides data voltage for the data lines. Because the scanning signal lines and the data lines are arranged in a cross mode, parasitic capacitance is generated in the overlapping area of the scanning signal lines and the data lines, and in the display scanning process of the display device, the parasitic capacitance interferes with data voltage transmitted by the data lines, so that the data voltage is changed when being transmitted to the pixel units, and the display effect of the display device is reduced.
Disclosure of Invention
In view of this, the present invention provides an array substrate, a display panel and a display device, in which a data outgoing line that is not overlapped with a scan signal line is provided, so as to prevent a parasitic capacitance from being formed between the scan signal line and the data outgoing line, thereby preventing interference to data voltage transmitted by the data outgoing line; and the data outgoing line is connected with the data line so as to transmit data voltage for the data line through the data outgoing line, and when the data line transmits the data voltage to the pixel unit corresponding to the scanning signal line scanned currently, only the connection end of the data line and the data outgoing line interferes with the data voltage through the parasitic capacitance in the area between the data line and the scanning signal line scanned currently, so that the number of the parasitic capacitance interfering with the data voltage is greatly reduced, the condition that the parasitic capacitance interferes with the data voltage is improved, and the display effect of the display device is improved.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
an array substrate comprises a plurality of intersecting and insulated data lines and a plurality of scanning signal lines, wherein the plurality of scanning signal lines comprise a first scanning signal line to an Nth scanning signal line, N is an integer not less than 2, and the array substrate further comprises:
the first ends of the data outgoing lines are correspondingly connected with the data lines one by one, the connecting ends of the data outgoing lines and the data lines are positioned between two adjacent scanning signal lines, and the data outgoing lines are not overlapped with the scanning signal lines;
and the driving structure is connected with the second end of the data outgoing line and used for transmitting data voltage for the data line through the data outgoing line.
The invention provides an array substrate, a display panel and a display device, which comprise a plurality of intersecting and insulated data lines and a plurality of scanning signal lines, wherein the plurality of scanning signal lines comprise a first scanning signal line to an Nth scanning signal line, N is an integer not less than 2, and the array substrate further comprises: the first ends of the data outgoing lines are correspondingly connected with the data lines one by one, the connecting ends of the data outgoing lines and the data lines are positioned between two adjacent scanning signal lines, and the data outgoing lines are not overlapped with the scanning signal lines; and the driving structure is connected with the second end of the data outgoing line and used for transmitting data voltage for the data line through the data outgoing line.
According to the technical scheme provided by the invention, the data outgoing line which is not overlapped with the scanning signal line is arranged, so that parasitic capacitance formed between the scanning signal line and the data outgoing line is avoided, and further, the interference on the data voltage transmitted by the data outgoing line is avoided; and the data outgoing line is connected with the data line so as to transmit data voltage for the data line through the data outgoing line, and when the data line transmits the data voltage to the pixel unit corresponding to the scanning signal line scanned currently, the number of parasitic capacitance interfering the data voltage is greatly reduced, the interference of the parasitic capacitance to the data voltage is improved, and the display effect of the display device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2a is a schematic diagram of data voltage transmission according to an embodiment of the present application;
FIG. 2b is a schematic diagram of a conventional data voltage transmission;
fig. 3a is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 3b is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 3c is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 3d is a schematic structural diagram of a conventional array substrate;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of another display panel provided in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the array substrate has a complex structure, which generally includes a plurality of scan signal lines and a plurality of data lines crossing each other and insulated from each other. When the display scanning is carried out, the scanning driving circuit scans the scanning signal lines, and simultaneously when data is input, the data driving structure provides data voltage for the data lines. Because the scanning signal lines and the data lines are arranged in a cross mode, parasitic capacitance is generated in the overlapping area of the scanning signal lines and the data lines, and in the display scanning process of the display device, the parasitic capacitance interferes with data voltage transmitted by the data lines, so that the data voltage is changed when being transmitted to the pixel units, and the display effect of the display device is reduced.
Based on this, the embodiment of the application provides an array substrate, a display panel and a display device, wherein a data outgoing line which is not overlapped with a scanning signal line is arranged, so that parasitic capacitance formed between the scanning signal line and the data outgoing line is avoided, and interference on data voltage transmitted by the data outgoing line is further avoided; and the connecting ends of the data outgoing lines and the data lines are connected, the length from the two end parts of the data lines is smaller than the integral length of the data lines, the voltage drop difference between the connecting ends and the two end parts of the data lines is reduced, and when the pixel units corresponding to the scanning signal lines at different positions are scanned, the condition that the difference of data voltages input into each pixel unit through the data lines is large is improved, so that the display brightness of different areas of the display device is uniform, and the display effect of the display device is improved. In order to achieve the above object, the technical solutions provided in the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 6.
Referring to fig. 1, a schematic structural diagram of an array substrate provided in an embodiment of the present application is shown, where the array substrate includes:
a plurality of intersecting and insulated data lines 100 and a plurality of scan signal lines 200, wherein the plurality of scan signal lines 200 include a first scan signal line to an nth scan signal line, N is an integer not less than 2, and further including:
a plurality of data outgoing lines 300, wherein first ends of the data outgoing lines 300 are connected with the data lines 100 in a one-to-one correspondence manner, the connection ends of the data outgoing lines 300 and the data lines 100 are located between two adjacent scanning signal lines 200, and the data outgoing lines 300 are not overlapped with the scanning signal lines 200, which is referred to as "non-overlapping" in the present invention, that is, in a direction perpendicular to the array substrate, the projection of the data outgoing lines 300 is not overlapped with the projection of the scanning signal lines 200;
and a driving structure 400, the driving structure 400 being connected to a second end of the data outlet 300, and configured to transmit a data voltage to the data line 100 through the data outlet 300.
As can be seen from the above, in the technical scheme provided in the embodiment of the present application, the data outgoing line that is not overlapped with the scan signal line is provided, so that a parasitic capacitance formed between the scan signal line and the data outgoing line is avoided, and further, interference on data voltage transmitted by the data outgoing line is avoided; and the data outgoing line is connected with the data line so as to transmit data voltage for the data line through the data outgoing line, and when the data line transmits the data voltage to the pixel unit corresponding to the scanning signal line scanned currently, the number of parasitic capacitance interfering the data voltage is greatly reduced, the interference of the parasitic capacitance to the data voltage is improved, and the display effect of the display device is improved.
For the interference of the parasitic capacitance to the data voltage, it is mainly reflected that the impedance generated by the parasitic capacitance will affect the impedance on the data line, and further affect the data voltage transmitted on the data line. The parasitic capacitance is formed between the data line and the plurality of scanning signal lines from the voltage input end to the cut-off end on the data line, wherein the impedance generated by the parasitic capacitance affects the impedance on the data line, and along with the direction from the voltage input end to the cut-off end on the data line, the impedance on the data line is gradually increased along with the increase of the overlapping amount of the impedance and the scanning signal lines, so that the voltage drop of the data voltage transmitted on the data line is increased, the difference of the data voltage finally transmitted to the pixel unit is large, and the brightness distribution of the display device is not uniform. According to the embodiment of the application, the number of the parasitic capacitors interfering with the data voltage is reduced, the interference condition of the parasitic capacitors on the data voltage is improved, the uneven brightness distribution condition of the display device is improved, and the display effect of the display device is improved.
The following describes in detail a situation of improving interference of parasitic capacitance to data voltage with reference to the accompanying drawings, in which the data voltage is transmitted to the data line through the connection terminal where the data outgoing line and the data line are connected, and the parasitic capacitance that is not on the path where the data voltage is transmitted from the connection terminal to the currently scanned scanning signal line does not increase the voltage drop of the data voltage, so in the following cases, the interference of the data voltage is described by the parasitic capacitance in the area between the connection terminal where the data outgoing line and the data line are connected and the currently scanned scanning signal line.
Specifically, referring to fig. 2a, a schematic diagram of data voltage transmission provided in the embodiment of the present application is shown, wherein the array substrate includes: data lines 101, scan signal lines 201 to 207 and data lead-out lines 301; the data lines 101 respectively cross and are insulated from the scan signal lines 201 to 207. Referring to fig. 2a, four parasitic capacitances, that is, parasitic capacitances formed in the overlapping regions between the data line 101 and the scan signal line 201, the scan signal line 202, the scan signal line 203, and the scan signal line 204, respectively, are formed between the connection end where the data outgoing line 301 is connected to the data line 101 and the end of the data line 101 on the side of the scan signal line 201; and three parasitic capacitances, namely, the parasitic capacitances formed by the data line 101 and the overlapping regions between the data line 101 and the scanning signal line 205, the scanning signal line 206 and the scanning signal line 207 respectively, are formed between the connection end of the data outgoing line 301 and the data line 101 and the end of the data line 101 on the side of the scanning signal line 207. The interference of the parasitic capacitance formed by the data line 101 and the overlapping area among the scanning signal line 201, the scanning signal line 202, the scanning signal line 203 and the scanning signal line 204 on the data voltage and the interference of the parasitic capacitance formed by the data line 101 and the overlapping area among the scanning signal line 205, the scanning signal line 206 and the scanning signal line 207 on the data voltage have no influence on each other.
When the scanning signal line 202 is scanned while the data voltage is transmitted to the data line 101 through the data outlet 301, the data voltage needs to be transmitted along the data outlet 301 and the data line 101 to the corresponding pixel unit where the scanning signal line 202 and the data line 101 intersect. Since the connection end of the data outgoing line 301 connected to the data line 101 is located in the region between the scan signal line 204 and the scan signal line 205, the data voltage (as indicated by the dotted arrow) will be transmitted to the connection end of the data line 101 along the data outgoing line 301, and then enter the data line 101 from the connection end, and only the parasitic capacitances formed by the scan signal line 204 and the scan signal line 203 and the data line 101 respectively will cause interference to the data voltage in the process that the data voltage is transmitted to the corresponding pixel unit at the intersection of the scan signal line 202 and the data line 101 along the data line 101, thereby reducing the number of the parasitic capacitances interfering with the data voltage, improving the interference of the parasitic capacitances to the data voltage, and improving the display effect of the display device.
In the prior art, referring specifically to fig. 2b, a schematic diagram of data voltage transmission is shown, in which an array substrate includes: the data lines 101 ', the scan signal lines 201 ', and the scan signal lines 207 '. When the conventional display device performs display scanning, and a currently scanned scanning signal line is the scanning signal line 202 ', a data voltage needs to be transmitted from the data line 101' near the input end of the scanning signal line 207 ', and for this reason, in a process that the data voltage is transmitted to a corresponding pixel unit at the intersection of the scanning signal line 202' and the data line 101 'along the data line 101', five parasitic capacitances are totally used to interfere with the data voltage, that is, the parasitic capacitances are respectively formed by the scanning signal line 207 ', the scanning signal line 206', the scanning signal line 205 ', the scanning signal line 204', and the scanning signal line 203 'and the data line 101'. Compared with the technical solutions provided in the embodiments of the present application, in the prior art, the number of parasitic capacitors that interfere with the data voltage is large, which affects the display effect of the display device.
In an embodiment of the present application, at most two data outgoing lines 300 are included between two adjacent scan signal lines 200 provided in the present application. That is, in the embodiment of the present application, it is preferable that a plurality of data lines 300, that is, a plurality of connection terminals between the data lines 300 and the data lines 100, are included between two adjacent scanning signal lines 200 under the condition that the space area and the pixel aperture ratio between two adjacent scanning signal lines 200 are not affected.
Further, referring to fig. 3a, a schematic structural diagram of another array substrate provided in the present embodiment is shown, wherein all the data outgoing lines 300 are located in a region between the 1+ a-th scan signal line 20(1+ a) and the N-b-th scan signal line 20(N-b), where 1+ a and N-b are positive integers, and 1+ a is smaller than N-b. In the array substrate provided by the embodiment of the application, all the data outgoing lines 300 are preferably located at the central portion of the area formed by all the scanning signal lines 200 in a concentrated manner, that is, the data outgoing lines 300 are distributed in a radiation manner from the middle to both sides of the area formed by all the scanning signal lines 200, so as to ensure that the data voltages transmitted by all the data outgoing lines 300 can be interfered by a small number of parasitic capacitors during display scanning, and ensure that the display effect of the display device is optimal. In the preferred embodiment of the present application, the values of a and b are the same.
The following describes the technical solution provided by the embodiment of the present application in detail with reference to fig. 3b, fig. 3c, fig. 3d, table 1 and table 2, wherein fig. 3b to fig. 3c each take seven scanning signal lines and two data lines as an example for explanation.
Fig. 3b is a schematic structural diagram of another array substrate provided in this embodiment of the present application, and fig. 3b specifically illustrates that the array substrate includes two data outgoing lines, namely a data outgoing line 301 and a data outgoing line 302; and, fig. 3b illustrates an example where N is 7, and a and b are both 2, then 1+ a-1 + 2-3, and N-b-7-2-5; among them, the data outlet 301 and the data outlet 302 are located at the central portion of the scan signal line composition region, that is, the data outlet 301 is located between the third scan signal line 203 and the fourth scan signal line 204, and the data outlet 302 is located between the fourth scan signal line 204 and the fifth scan signal line 205.
In contrast, fig. 3c is a schematic structural diagram of another array substrate provided in this embodiment, where fig. 3c illustrates a case where the data pinout is located at an end of the scan signal line composition region, that is, the data pinout 301 'is located between the scan signal line 205 and the scan signal line 206, and the data pinout 302' is located between the scan signal line 206 and the scan signal line 207.
And, for comparison, fig. 3d is a schematic structural diagram of a conventional array substrate, where fig. 3d illustrates that the array substrate includes scan signal lines 201 'to 207' and two data lines 100 ', and the two data lines 100' respectively input data voltages through the input terminals 301 ″ and 302 ″.
For both cases shown in fig. 3b and 3c (i.e., the case where the data pinout is located at the central portion of the scanning signal line constituent region and the case where the data pinout is located at the end portion of the scanning signal line constituent region), the number of parasitic capacitances that cause interference with the data voltage in the entire scanning process (i.e., the scanning process for the scanning signal lines 201 to 207) is as shown in table 1:
TABLE 1
And, for the case of the prior art shown in fig. 3d, the number of parasitic capacitances that disturb the data voltage during the entire scanning process is shown in table 2:
TABLE 2
Referring to table 1, during the whole scanning process, the number of interferences generated by parasitic capacitances suffered by the data voltages transmitted by the data outlet 301 and the data outlet 302 is 5+3+1+0+1+3+5 to 18; and the number of disturbances caused by parasitic capacitance to which the data voltages transmitted by the data pinout 301 'and the data pinout 302' are subjected is 9+7+5+3+1+0+ 1-26. In combination with the two cases shown in fig. 3b and fig. 3c and the data in table 1, compared to the case where the data pinout 301 'and the data pinout 302' are located at the end of the scan signal line composition region (i.e., between the scan signal line 205 and the scan signal line 207), the data pinout 301 and the data pinout 302 provided in the embodiment of the present application are located at the central portion of all the scan signal line composition regions (i.e., between the scan signal line 203 and the scan signal line 205), the number of parasitic capacitances that disturb the data voltage during the display process is smaller, and the display effect of the display device is improved.
In addition, compared to the case of the conventional scan process shown in fig. 3d and table 2, the number of parasitic capacitances that disturb the data voltage is 12+10+8+6+4+2+0 — 42. In other words, no matter which embodiment is corresponding to fig. 3b or fig. 3c provided in the present application, compared with the prior art, the number of parasitic capacitors that interfere with the data voltage in the display process is smaller, and the display effect of the display device is improved.
It should be noted that the embodiment shown in fig. 3a, fig. 3b, and fig. 3c is only one of all the wiring structures in the present application, and in other embodiments of the present application, the wiring structure may be in other manners, which does not specifically limit the present application, and needs to be specifically designed according to practical applications. And, the preferred length of all data lines of this application embodiment is the same, guarantees that the storage capacitance of data line is unanimous.
Referring to fig. 4, a schematic structural diagram of another array substrate provided in the embodiment of the present application is shown, wherein the driving structure 400 provided in the embodiment of the present application includes:
a multiplexing circuit 410, said multiplexing circuit 410 being connected to a second end of said data pinout 300. The output end of the multi-path selection circuit 410 is connected to the data outgoing line 300, the input end of the multi-path selection circuit 410 is connected to a driving chip of the display device, the driving chip transmits data voltages to the multi-path selection circuit 410, and then the multi-path selection circuit 410 selects corresponding data voltages and transmits the data voltages to corresponding data lines 100 through the data outgoing line 300.
In an embodiment of the present invention, the multiplexer circuit 410 is located on a first side of the extending direction of the scan signal line 200.
And, the array substrate that this application embodiment provided includes: a scan driving circuit 500, wherein the scan driving circuit 500 is connected to the first scan signal line to the nth scan signal line, and is configured to transmit a scan signal to the scan signal line 200;
the scan driving circuit 500 is located on a second side in the extending direction of the scan signal line 200.
As can be seen from the above, in the embodiment of the present invention, the scan driving circuit 500 and the multiplexing circuit 410 are oppositely disposed on both sides of the scan signal line 200, so as to properly route the array substrate and optimize the routing structure of the array substrate.
In any of the above embodiments of the present application, the data leading-out line and the scan signal line are located on the same conductive layer. The data outgoing line and the scanning signal line are arranged on the same conductive layer, so that the situation that the conductive layer is newly added in the manufacturing process is avoided, and the purpose of saving resources is achieved. And the data outgoing line and the data line can be connected through a via hole.
It should be noted that, in other embodiments of the present application, the data outgoing line and the scanning signal line may also be located in different conductive layers, which is not specifically limited to this application and needs to be specifically designed according to practical applications.
Correspondingly, the embodiment of the application also provides a display panel, and the display panel comprises the array substrate provided by any one of the embodiments.
It should be noted that the display panel provided in the embodiment of the present application may be a liquid crystal display panel, an organic electroluminescence display panel, or an electronic paper display panel, and the like, and the present application is not particularly limited, and needs to be specifically selected according to actual applications.
Referring to fig. 5, in order to illustrate a structure of a display panel provided in an embodiment of the present disclosure, the display panel 10 provided in an embodiment of the present disclosure may be a circular display panel, so as to manufacture the display panel into a display panel of a display device such as a dial.
The display panel 10 includes a display area AA, and the display area AA is provided with the scanning signal lines, the gate lines, the data outgoing lines, and the like of the array substrate provided in any of the above embodiments. And, in the frame region of the display panel 10, along both side directions of the scanning signal lines, a data scanning region 101 and a gate scanning region 102 are provided.
The data scanning area 101 may be provided with a multi-channel selection circuit of the array substrate provided in any of the above embodiments, the multi-channel selection circuit is connected to the driving chip, and the gate scanning area 102 is provided with a scanning driving circuit of the array substrate provided in any of the above embodiments.
Further, the data scanning area 101 may be further provided with a structure such as an electrostatic discharge circuit, and the application is not particularly limited thereto.
Referring to fig. 6, a schematic structural diagram of another display panel provided in the embodiment of the present application is shown, wherein, different from the embodiment corresponding to fig. 5, a data scanning area 101 and a gate scanning area 102 of the display panel shown in fig. 6 of the present application may also be arranged in a position opposite to the position shown in fig. 5.
Correspondingly, an embodiment of the present application further provides a display device, where the display device includes the display panel provided in any one of the above embodiments.
It should be noted that the display device provided in the embodiments of the present application may be a liquid crystal display device, an organic electroluminescence display device, or an electronic paper display device, and the like, and the present application is not particularly limited and needs to be specifically selected according to practical applications.
The embodiment of the application provides an array substrate, display panel and display device, including crossing and many insulated data lines and many scanning signal lines, many scanning signal lines include first scanning signal line to nth scanning signal line, and N is not less than 2's integer, still includes: the first ends of the data outgoing lines are correspondingly connected with the data lines one by one, the connecting ends of the data outgoing lines and the data lines are positioned between two adjacent scanning signal lines, and the data outgoing lines are not overlapped with the scanning signal lines; and the driving structure is connected with the second end of the data outgoing line and used for transmitting data voltage for the data line through the data outgoing line.
As can be seen from the above, in the technical scheme provided in the embodiment of the present application, the data outgoing line that is not overlapped with the scan signal line is provided, so that a parasitic capacitance formed between the scan signal line and the data outgoing line is avoided, and further, interference on data voltage transmitted by the data outgoing line is avoided; and the data outgoing line is connected with the data line so as to transmit data voltage for the data line through the data outgoing line, and when the data line transmits the data voltage to the pixel unit corresponding to the scanning signal line scanned currently, the number of parasitic capacitance interfering the data voltage is greatly reduced, the interference of the parasitic capacitance to the data voltage is improved, and the display effect of the display device is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. An array substrate comprises a plurality of intersecting and insulated data lines and a plurality of scanning signal lines, wherein the plurality of scanning signal lines comprise a first scanning signal line to an Nth scanning signal line, N is an integer not less than 2, and the array substrate is characterized by further comprising:
the first ends of the data outgoing lines are correspondingly connected with the data lines one by one, the connecting ends of the data outgoing lines and the data lines are positioned between two adjacent scanning signal lines, and the data outgoing lines are not overlapped with the scanning signal lines;
the driving structure is connected with the second end of the data outgoing line and used for transmitting data voltage for the data line through the data outgoing line;
wherein the driving structure comprises: a multiplexer circuit connected to the second end of the data outgoing line and located on a first side of the extension direction of the scanning signal line; and, the array substrate includes: a scanning drive circuit connected to an end portion of a second side in an extending direction of the first to nth scanning signal lines, for transmitting a scanning signal to the scanning signal lines;
wherein the scan driving circuit is located on a second side in an extending direction of the scan signal line.
2. The array substrate of claim 1, wherein at most two data outgoing lines are included between two adjacent scanning signal lines.
3. The array substrate of claim 2, wherein all the data leading-out lines are located in a region between the 1+ a-th scan signal line and the N-b-th scan signal line, wherein 1+ a and N-b are positive integers, and 1+ a is smaller than N-b.
4. The array substrate of claim 3, wherein a and b have the same value.
5. The array substrate of claim 1, wherein the data pinout lines and the scan signal lines are located on a same conductive layer.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. The display panel according to claim 6, wherein the display panel is a circular display panel.
8. A display device characterized in that it comprises a display panel as claimed in claim 6 or 7.
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| CN107481666A (en) * | 2017-08-16 | 2017-12-15 | 深圳市华星光电半导体显示技术有限公司 | A kind of organic light emitting diode display |
| CN110942708B (en) * | 2018-09-21 | 2021-08-27 | 元太科技工业股份有限公司 | Conductive structure, circuit design and display |
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Effective date of registration: 20210929 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201 Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |