CN1316439C

CN1316439C - Driving circuit of plane display device

Info

Publication number: CN1316439C
Application number: CNB031073816A
Authority: CN
Inventors: 尤建盛
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2003-03-25
Filing date: 2003-03-25
Publication date: 2007-05-16
Anticipated expiration: 2023-03-25
Also published as: CN1532787A

Abstract

The present invention relates to a driving circuit of a plane display device, which is arranged on a plane display panel and is composed of a plurality of signal lines, at least one scan signal complementation pair creation unit, a plurality of switch units and a display area, wherein the signal lines are used for providing a plurality of analog video signals to the switch units, and at least one signal complementation pair creation unit is used for generating at least one scan signal, and the scan signal is output to the switch units of which the actions are controlled by at least one of the scan signal; thereby, the received analog video signals are switched to data signals which are output to the display area.

Description

The flat display driving circuit

Technical field

The present invention relates to a kind of driving circuit, refer in particular to a kind of flat display driving circuit.

Background technology

Along with the prosperity of opto-electronics, flat-panel screens is applied on the display screen of any monitor or electronic product at large.Present flat-panel screens is that driving circuit, thin film transistor (TFT) and necessary circuit are in the layout of on the glass substrate.Fig. 1 shows the synoptic diagram of known signal sampling/holding circuit, this sample of signal/holding circuit is in the layout of on the substrate, and analog switch 111,112,113 are disposed at signal wire 121,122,123 and viewing area 131 between, wherein, these analog switches 111,112,113 control grid is the output terminal that is connected to negative circuit 141, the input end of negative circuit 141 is connected in a clock signal generator (figure does not show), to receive and to produce the anti-phase clock signal that timing signal generator was produced, controls each analog switch 111 respectively for the signal that scans of output complementary pair, 112,113 action, these analog switches 111,112,113 also are connected to signal wire 121 respectively, 122,123, to receive analog video signal and to export corresponding analog video signal by the control of sweep signal.

Yet, these analog switches 111,112,113 are connected to negative circuit 141 or signal wire 121,122,123 o'clock, can be at signal wire 121,122, produce on 123 and intersect but unconnected crossover point (Crossover) 151,152, certainly, in this synoptic diagram, there is more crossover point 151,152 not draw.These crossover point 151,152 parts all can produce stray capacitance (Parasitic Capacitance).Because stray capacitance can cause electric energy loss, and make picture quality reduce.Therefore, at analog switch 111,112,113, negative circuit 141 and signal wire 121,122, layout how between 123 to reduce stray capacitance quantity, has become the problem of needing solution badly.

Summary of the invention

Fundamental purpose of the present invention is that a kind of flat display driving circuit is being provided, and can reduce the quantity of stray capacitance, to improve electric energy loss and to promote picture quality.

For achieving the above object, a kind of flat display driving circuit of the present invention is to be in the layout of on the two-d display panel, and this two-d display panel has a viewing area, and this driving circuit mainly comprises:

Many signal line provide a plurality of analog video signals; At least one signal complementary pair generation unit that scans is in order to produce at least one signal that scans; And a plurality of switch elements, be to be disposed between these signal wires that a plurality of analog video signals are provided, each switch element also is connected with at least one signal wire respectively, to receive an analog video signal, each switch element also is connected with this at least one signal complementary pair generation unit that scans, by this at least one action that scans these switch elements of signal controlling, with outputting data signals this viewing area to this two-d display panel.

The no special restriction of this viewing area configuration of these switch elements of driving circuit of the present invention and this two-d display panel is preferably at least one signal wire of being separated by between this viewing area of these switch elements and this two-d display panel.

The no special restriction of signal wire configuration of driving circuit of the present invention is preferably this at least one signal wire and scans between the signal complementary pair generation unit between this switch element and this.

This signal wire of driving circuit of the present invention and the configuration between this switch element do not have special restriction, are preferably these signal wires that a plurality of analog video signals are provided between this switch element and this viewing area.

Driving circuit of the present invention to scan signal complementary pair generation unit unrestricted, be preferably an amplifying circuit, the best is a see-saw circuit, receiving a clock signal, and this clock signal is amplified, with this at least one signal that scans of output.

Flat display driving circuit of the present invention, wherein this at least one inversion signal that scans signal for this clock signal.

Flat display driving circuit of the present invention, wherein these switch elements are transistor.

Flat display driving circuit of the present invention, wherein these switch elements are thin film transistor (TFT) (TFT).

The two-d display panel that is applicable to driving circuit of the present invention is unrestricted, being preferably this two-d display panel is Plasmia indicating panel (PDP), organic electric-excitation luminescent displaying panel (OLED), Field Emission Display panel (FED) or display panels (LCD), the best is a display panels.

Description of drawings

Fig. 1 is the synoptic diagram of known signal sampling/holding circuit;

Fig. 2 (A) is the driving circuit synoptic diagram of the present invention's first preferred embodiment;

Fig. 2 (B) is the stray capacitance synoptic diagram that the present invention's first preferred embodiment produces;

Fig. 3 (A) is the driving circuit synoptic diagram of the present invention's second preferred embodiment;

Fig. 3 (B) is the stray capacitance synoptic diagram that the present invention's second preferred embodiment produces;

Fig. 4 is the present invention and known relatively form.

Embodiment

The relevant first embodiment of the present invention, the sampling that please show with reference to Fig. 2 (A)/keep the driving circuit synoptic diagram, it is mainly by complex signal line 211,212,213, plural switch element 221,222,223, scan signal complementary pair generation unit 231 and viewing area 241 is formed.These signal wires 211,212,213 are in order to provide analog video signal, for example: signal wire 211 provides blue analog video signal, and signal wire 212 provides red analog video signal, and signal wire 213 provides green analog video signal.

In present embodiment, scan signal complementary pair generation unit 231 and be preferably a negative circuit.Its input end is connected to one and scans signal generation unit (figure does not show), this scans the signal generation unit in order to produce the positive clock signal, be used for driving these switch elements 221,222, N type metal oxide semiconductor field effect transistor (NMOS) in 223, scan 231 positive clock signals that receive the output of sweep signal generation unit of signal complementary pair generation unit, for producing the complementary pair (being anti-phase clock signal) that scans signal, to drive these switch elements 221, P type metal oxide semiconductor field effect transistor (PMOS) in 222,223.

In present embodiment, these switch elements 221,222,223 can be any electronic switch, are preferably transistor switch, and the best is thin film transistor switch (TFT).These switch elements 221,222,223rd are disposed between signal wire 212 and the signal wire 213, and its control grid all is connected in the output terminal that scans signal complementary pair generation unit, each switch element 221,222,223 also respectively with a signal wire 211,212,213 are connected, for difference received signal line 211,212,213 analog video signals that transmitted, and by scanning these switch elements 221 of signal controlling, 222,223 output and the corresponding digital data signal of these analog video signals.Wherein, these switch elements 221,222,223 export digital data signal to data line in the viewing area 241 (figure does not show) by

output line

2211,2221,223 respectively.

Fig. 2 (B) shows the stray capacitance synoptic diagram that first embodiment of the invention produced, switch element 221 is with signal wire 212 with signal line wiring 2111 and scans signal complementary pair generation unit 231 and these switch elements 221,222,223 connecting

line

2311,2312 crossover point 411,412,413 (among the figure by annotation triangle place) produce stray capacitance (totally 3 stray capacitances).Switch element 222 with signal line wiring 2121 is and scans signal complementary pair generation unit 231 and these switch elements 221, the crossover point 421 of 222,223 connecting

line

2311,2312,422,423 (among the figure by the square place of annotation) produce stray capacitance (totally 3 stray capacitances).Switch element 223 and signal line wiring 2131 are to produce stray capacitance (totally 3 stray capacitances) with the crossover point 431,432,433 of the

output line

2211,2221,223 1 of these switch elements 221,222,223 (among the figure by annotation sexangle place).

Fig. 3 shows the present invention's take a sample/keep second embodiment synoptic diagram of driving circuit, its element and connected mode are all similar with first embodiment, these switch elements 321 of thought, 322,323 are disposed between signal wire 212 (red analog video signal is provided) and the signal wire 213 (green analog video signal is provided) in Fig. 2 (A) originally, in present embodiment, these switch elements 321,322,323 are disposed between signal wire 313 (green analog video signal is provided) and the signal wire 311 (blue analog video signal is provided), and in Fig. 2 (A), these switch elements 321,322,323 and viewing area 241 between across a signal line 213, in present embodiment, these switch elements 321,322,323 and viewing area 341 between across two signal line 311,312.

Fig. 3 (B) shows the stray capacitance synoptic diagram that second embodiment of the invention produced, switch element 321 with signal line wiring 3111 is and these switch elements 321,322,323

output signal line

3211,3221,3231 and switch element 322 be connected to the crossover point 451,452 of the connecting line 3222 of signal wire 312,453,454 (among the figure by annotation triangle place) produce stray capacitance (totally 4 stray capacitances).Switch element 322 and signal line wiring 3121 are the output lines 3211 with these switch elements 321,322,323,3221,3231 and the crossover point 461,462 of signal wire 311,463,464 (among the figure by annotation sexangle place) produce stray capacitance (totally 4 stray capacitances).Switch element 323 with signal line wiring 3131 is and scans signal complementary pair generation unit 331 and these switch elements 321,322, the crossover point 441,442 of 323 connecting line 3311,3312 (among the figure by the square place of annotation) produces stray capacitance (totally 2 stray capacitances).

Fig. 4 shows the relatively signal table of the stray capacitance that the present invention and known drive circuitry arrangement are produced, table can be learnt thus, within each picture element length, known circuit layout will produce 12 stray capacitances, but as if the layout according to first embodiment of the invention, then only produce 9 stray capacitances, if layout according to second embodiment of the invention, produce 10 stray capacitances, thus the stray capacitance quantity that the present invention reduces layout really to be produced, to improve electric energy loss and to promote picture quality.

The foregoing description only has been convenience explanation and giving an example, and the interest field that the present invention advocated is from should being as the criterion with claims, but not only limits to the foregoing description.

Claims

1, a kind of flat display driving circuit is in the layout of on the two-d display panel, and this two-d display panel has a viewing area, and this driving circuit is characterized in that, mainly comprises:

Many signal line are used to provide a plurality of analog video signals;

At least one signal complementary pair generation unit that scans is in order to produce at least one signal that scans;

A plurality of switch elements, be disposed between these signal wires that a plurality of analog video signals are provided, at least one signal wire of wherein being separated by between this viewing area of these switch elements and this two-d display panel, each switch element is connected with at least one signal wire respectively, to receive an analog video signal, each switch element also is connected with this at least one signal complementary pair generation unit that scans, by this at least one action that scans these switch elements of signal controlling, with outputting data signals this viewing area to this two-d display panel.

2, flat display driving circuit according to claim 1, it is characterized in that wherein this at least one signal complementary pair generation unit that scans is a negative circuit, it receives a clock signal, and this clock signal carried out anti-phase processing, with this at least one signal that scans of output.

3, flat display driving circuit according to claim 2 is characterized in that, wherein this at least one inversion signal that scans signal for this clock signal.

4, flat display driving circuit according to claim 1 is characterized in that, wherein these switch elements are transistor.

5, flat display driving circuit according to claim 1 is characterized in that, wherein these switch elements are thin film transistor (TFT).

6, flat display driving circuit according to claim 1 is characterized in that, wherein at least one signal wire scans between the signal complementary pair generation unit between this switch element and this.

7, flat display driving circuit according to claim 1 is characterized in that, wherein these signal wires that a plurality of analog video signals are provided are between this switch element and this viewing area.

8, flat display driving circuit according to claim 1 is characterized in that, wherein this two-d display panel is a display panels.