TWI300589B - - Google Patents

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Publication number
TWI300589B
TWI300589B TW091115966A TW91115966A TWI300589B TW I300589 B TWI300589 B TW I300589B TW 091115966 A TW091115966 A TW 091115966A TW 91115966 A TW91115966 A TW 91115966A TW I300589 B TWI300589 B TW I300589B
Authority
TW
Taiwan
Prior art keywords
layer
epitaxial layer
transferring
substrate
epitaxial
Prior art date
Application number
TW091115966A
Other languages
English (en)
Chinese (zh)
Inventor
Yew Chung Sermon Wu
Pei Yen Lin
Original Assignee
Univ Nat Chiao Tung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Chiao Tung filed Critical Univ Nat Chiao Tung
Priority to TW091115966A priority Critical patent/TWI300589B/zh
Priority to US10/253,575 priority patent/US6686257B1/en
Application granted granted Critical
Publication of TWI300589B publication Critical patent/TWI300589B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
TW091115966A 2002-07-17 2002-07-17 TWI300589B (https=)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091115966A TWI300589B (https=) 2002-07-17 2002-07-17
US10/253,575 US6686257B1 (en) 2002-07-17 2002-10-04 Method for transferring epitaxy layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091115966A TWI300589B (https=) 2002-07-17 2002-07-17

Publications (1)

Publication Number Publication Date
TWI300589B true TWI300589B (https=) 2008-09-01

Family

ID=30442124

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091115966A TWI300589B (https=) 2002-07-17 2002-07-17

Country Status (2)

Country Link
US (1) US6686257B1 (https=)
TW (1) TWI300589B (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005064188A (ja) * 2003-08-11 2005-03-10 Sumitomo Electric Ind Ltd 基板の回収方法および再生方法、ならびに半導体ウエハの製造方法
US20050186757A1 (en) * 2004-02-20 2005-08-25 National Chiao Tung University Method for lift off GaN pseudomask epitaxy layer using wafer bonding way
US20050186764A1 (en) * 2004-02-20 2005-08-25 National Chiao Tung University Method for lifting offGaN pseudomask epitaxy layerusing wafer bonding way
JP4624131B2 (ja) * 2005-02-22 2011-02-02 三洋電機株式会社 窒化物系半導体素子の製造方法
JP2007134388A (ja) * 2005-11-08 2007-05-31 Sharp Corp 窒化物系半導体素子とその製造方法
TWI319893B (en) * 2006-08-31 2010-01-21 Nitride semiconductor substrate, method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate
US8188573B2 (en) * 2006-08-31 2012-05-29 Industrial Technology Research Institute Nitride semiconductor structure
US8859399B2 (en) 2008-11-19 2014-10-14 Agency For Science, Technology And Research Method of at least partially releasing an epitaxial layer
TWI472477B (zh) * 2010-03-02 2015-02-11 國立臺灣大學 矽奈米結構與其製造方法及應用
TWI429795B (zh) * 2011-10-31 2014-03-11 國立臺灣大學 於氮化鎵上製作氧化鋅之方法與其應用thereof
TWI460885B (zh) * 2011-12-09 2014-11-11 Univ Nat Chiao Tung 具有空氣介質層之半導體光電元件及空氣介質層之製作方法
JPWO2021221055A1 (https=) * 2020-04-28 2021-11-04

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073230A (en) * 1990-04-17 1991-12-17 Arizona Board Of Regents Acting On Behalf Of Arizona State University Means and methods of lifting and relocating an epitaxial device layer
EP0747935B1 (en) * 1990-08-03 2004-02-04 Canon Kabushiki Kaisha Process for preparing an SOI-member
US6177359B1 (en) * 1999-06-07 2001-01-23 Agilent Technologies, Inc. Method for detaching an epitaxial layer from one substrate and transferring it to another substrate
JP4461616B2 (ja) * 2000-12-14 2010-05-12 ソニー株式会社 素子の転写方法、素子保持基板の形成方法、及び素子保持基板

Also Published As

Publication number Publication date
US20040014297A1 (en) 2004-01-22
US6686257B1 (en) 2004-02-03

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MM4A Annulment or lapse of patent due to non-payment of fees