TWI300589B - - Google Patents

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Publication number
TWI300589B
TWI300589B TW91115966A TW91115966A TWI300589B TW I300589 B TWI300589 B TW I300589B TW 91115966 A TW91115966 A TW 91115966A TW 91115966 A TW91115966 A TW 91115966A TW I300589 B TWI300589 B TW I300589B
Authority
TW
Taiwan
Application number
TW91115966A
Inventor
Yew Chung Sermon Wu
Pei Yen Lin
Original Assignee
Univ Nat Chiao Tung
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nat Chiao Tung filed Critical Univ Nat Chiao Tung
Priority to TW91115966A priority Critical patent/TWI300589B/zh
Application granted granted Critical
Publication of TWI300589B publication Critical patent/TWI300589B/zh

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
TW91115966A 2002-07-17 2002-07-17 TWI300589B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91115966A TWI300589B (zh) 2002-07-17 2002-07-17

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW91115966A TWI300589B (zh) 2002-07-17 2002-07-17
US10/253,575 US6686257B1 (en) 2002-07-17 2002-10-04 Method for transferring epitaxy layer

Publications (1)

Publication Number Publication Date
TWI300589B true TWI300589B (zh) 2008-09-01

Family

ID=30442124

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91115966A TWI300589B (zh) 2002-07-17 2002-07-17

Country Status (2)

Country Link
US (1) US6686257B1 (zh)
TW (1) TWI300589B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005064188A (ja) * 2003-08-11 2005-03-10 Sumitomo Electric Ind Ltd 基板の回収方法および再生方法、ならびに半導体ウエハの製造方法
US20050186757A1 (en) * 2004-02-20 2005-08-25 National Chiao Tung University Method for lift off GaN pseudomask epitaxy layer using wafer bonding way
US20050186764A1 (en) * 2004-02-20 2005-08-25 National Chiao Tung University Method for lifting offGaN pseudomask epitaxy layerusing wafer bonding way
JP4624131B2 (ja) * 2005-02-22 2011-02-02 三洋電機株式会社 窒化物系半導体素子の製造方法
JP2007134388A (ja) * 2005-11-08 2007-05-31 Sharp Corp 窒化物系半導体素子とその製造方法
TWI319893B (en) * 2006-08-31 2010-01-21 Nitride semiconductor substrate, method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate
US8188573B2 (en) * 2006-08-31 2012-05-29 Industrial Technology Research Institute Nitride semiconductor structure
SG171762A1 (en) 2008-11-19 2011-07-28 Agency Science Tech & Res Method of at least partially releasing an epitaxial layer
TWI472477B (en) * 2010-03-02 2015-02-11 Univ Nat Taiwan Silicon nanostructures and method for producing the same and application thereof
TWI429795B (en) * 2011-10-31 2014-03-11 Univ Nat Taiwan Method for producing zinc oxide on gallium nitride and application thereof
TWI460885B (en) * 2011-12-09 2014-11-11 Univ Nat Chiao Tung A semiconductor optical device having air media layer and the method for forming the air media layer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073230A (en) * 1990-04-17 1991-12-17 Arizona Board Of Regents Acting On Behalf Of Arizona State University Means and methods of lifting and relocating an epitaxial device layer
EP0688048A3 (en) * 1990-08-03 1996-02-28 Canon Kk Semiconductor member having an SOI structure
US6177359B1 (en) * 1999-06-07 2001-01-23 Agilent Technologies, Inc. Method for detaching an epitaxial layer from one substrate and transferring it to another substrate
JP4461616B2 (ja) * 2000-12-14 2010-05-12 ソニー株式会社 素子の転写方法、素子保持基板の形成方法、及び素子保持基板

Also Published As

Publication number Publication date
US20040014297A1 (en) 2004-01-22
US6686257B1 (en) 2004-02-03

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees