!297216 九、發明說明： 【發明所屬之技術領域】!297216 IX. Description of the invention: [Technical field to which the invention belongs]
本發明-般是有關i浮動閘記憶體裝置，更特別的是 《裝置’藉垂直沉積出具複數個 。己憶胞絕緣層的複數個浮動間極記憶胞陣列，得到改良的 保存特性與集積容量。 【先前技術】The present invention is generally related to i floating gate memory devices, and more particularly, the "device" is deposited by a plurality of vertical depositions. A plurality of floating interpole memory cell arrays having a cell insulating layer have been obtained, and improved storage characteristics and accumulation capacity are obtained. [Prior Art]
圖1是顯示出傳統浮動閘記憶體裝置的剖示圖。 、傳統浮動閘記憶體裝置的記憶胞包括在p型基板2上形 成的一N型;:及極區4與一 N型源極區6、依序在冑道區上形 成的-第-絕緣層8、一浮動閘極1〇、—第二絕緣層12 以及一字線14。 在上述傳統浮動閘記憶體裝置的記憶胞中，記憶胞的 通道電阻是由儲存在浮動閘極1〇内的電荷狀態來區分。 亦即，既然電子儲存在浮動閘極丨〇内時，通道中會被 感應出正通道電荷，所以記憶胞會變成高電阻狀態而被 關閉。 同時’當正電洞儲存在浮動閘極10内時，通道中會被 感應出負通道電荷，所以記憶胞會變成低電阻狀態而被 打開。 以這種方式’藉選取出浮動閘極丨0内的電荷種類，讓 資料寫入記憶胞内，使得記憶胞能當作非揮發性記憶胞 來操作。 然而’既然傳統浮動閘記憶體裝置的記憶胞尺寸變小 101040.doc 1297216 時’保存特性會變1，所以报難進行正常的操作。 ^的是，既然具奈米級浮_極結構之記憶胞的保 存⑩會變得較弱，所㈣使是在低電㈣度下，無法 在項取模式下將隨機電壓施加到字線上。 【發明内容】 因此，本發明的目的是要具奈米級浮動間極 憶胞在低電壓下操作。 幻己 本毛月的另一目的是要藉沉積出複數個與複數個記憶 胞絕緣層垂直的浮動閘記憶胞陣列，來改善記憶胞 容量。 在實施例中，浮動閘記憶體裝置包括-底部字線、一 在底部字線上形成且保持在浮動狀態的浮動通道層、一 芋動閘極與一在浮動閘極上形成且平行於底部字線的 頂部字線。有資料儲存在浮動通道上形成的浮動間極 中。在此，視底部字線與頂部字線的位準而定，將資料 _ 寫入到浮動閘極中，並且視浮動閘極内電荷的極性狀態 而疋，依據浮動通道中被感應出的不同通道電阻，來讀 取資料。 在另一實施例中，浮動閘記憶體裝置一底部字線、一 在底部字線上形成的第一絕緣層、一在第一絕緣層上形 成且保持在浮動狀態的p型浮動通道、一在p型浮動通道 上形成的第二絕緣層、一浮動閘極、一在浮動閘極上形 頂部 成的第 以及在浮動通道二側上形成的一 N型汲極區與一 N型源 101040.doc 1297216 極區。在第二絕緣層上形成的浮動閘極中儲存有電荷。 在此，視底部字線與頂部字線的位準而定，將資料寫入 到浮動閘極中’並且視浮動閘極内電荷的極性狀態而 定，依據浮動通道中被感應出的不同通道電阻，來讀取 資料。 在另一實施例中，浮動閘記憶體裝置包括複數個單元 «己隐胞陣列。每個該等複數個單元記憶胞陣列都包括複1 is a cross-sectional view showing a conventional floating gate memory device. The memory cell of the conventional floating gate memory device includes an N-type formed on the p-type substrate 2; and a polar region 4 and an N-type source region 6, sequentially forming a -first insulation on the ramp region Layer 8, a floating gate 1 —, a second insulating layer 12, and a word line 14. In the memory cell of the above conventional floating gate memory device, the channel resistance of the memory cell is distinguished by the state of charge stored in the floating gate 1〇. That is, since the electrons are stored in the floating gate, the positive channel charge is induced in the channel, so the memory cell becomes a high resistance state and is turned off. At the same time, when the positive hole is stored in the floating gate 10, the negative channel charge is induced in the channel, so the memory cell becomes a low resistance state and is turned on. In this way, by selecting the type of charge in the floating gate 丨0, the data is written into the memory cell, so that the memory cell can operate as a non-volatile memory cell. However, since the memory cell size of the conventional floating gate memory device becomes smaller at 101,040.doc 12,972,16, the storage characteristic changes to 1, so it is difficult to perform normal operations. ^, since the memory 10 of the memory cell with a nano-level floating _ pole structure becomes weaker, (4) makes it impossible to apply a random voltage to the word line in the item-taking mode at low power (four) degrees. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to operate at a low voltage with a nanoscale floating inter-cell memory. Another purpose of this month is to improve the memory cell capacity by depositing a plurality of floating gate memory cell arrays perpendicular to a plurality of memory cells. In an embodiment, the floating gate memory device includes a bottom word line, a floating channel layer formed on the bottom word line and held in a floating state, a flip gate and a floating gate formed parallel to the bottom word line The top word line. Data is stored in the floating pole formed on the floating channel. Here, depending on the level of the bottom word line and the top word line, the data_ is written into the floating gate, and depending on the polarity state of the charge in the floating gate, depending on the difference induced in the floating channel Channel resistance to read data. In another embodiment, the floating gate memory device has a bottom word line, a first insulating layer formed on the bottom word line, a p-type floating channel formed on the first insulating layer and maintained in a floating state, and a a second insulating layer formed on the p-type floating channel, a floating gate, a first formed on the top of the floating gate, and an N-type drain region formed on two sides of the floating channel and an N-type source 101040.doc 1297216 Polar zone. A charge is stored in the floating gate formed on the second insulating layer. Here, depending on the level of the bottom word line and the top word line, the data is written into the floating gate' and depending on the polarity state of the charge in the floating gate, depending on the different channels induced in the floating channel Resistance, to read the data. In another embodiment, the floating gate memory device includes a plurality of cells «self-cell arrays. Each of the plurality of unit memory cell arrays includes a complex
數個汙動閘極記憶胞。在此，浮動閘極記憶胞包括一底 子線、一在底部字線上形成的第一絕緣層、一在第一 、、、邑緣層上开^成且保持在浮動狀態的p型浮動通道、一在p 型洋動通道上形成的第二絕緣層、—浮動閘極、一在浮 動閘極上形成的第三絕緣層、一在第三絕緣層上形成的 頂部字線、以及在浮動通道二側上形成的一N型汲極區 與-N型源極區。在第二絕緣層上形成的浮動閘極中儲 存有電何。在此，視底部字線與頂部字線的位準而定， 將貝料寫人到浮動閘極中’並且視浮動閘極内電荷的極 性狀態而$，依據浮動通道中被感應出的不同通道電 阻，來讀取資料。 “在另Λ施例中，浮動閘記憶體裝置包括複數個單另 記憶胞陣列。每個該等複數個單元記憶胞陣列都包括潜 ^料動閘極記憶胞。在此，浮動閘極記憶胞包括-友 P字線在底部字線上形成的第一絕緣層、一在第一 、’、邑、·彖層上形成且保持在浮動狀態的p型浮動通道、—在 b㈣道上形成的第二絕緣層、—浮動閘極、一在巧 101040.doc 1297216 動閘極上形成的第三絕緣層、一在第三絕緣層上形成的 頂部字線、以及在浮動通道二側上形成的一1^型汲極區 與一 N型源極區。在第二絕緣層上形成的浮動閘極中儲 存有電荷。在此，每個該等複數個單元記憶胞陣列中的 複數個浮動閘極記憶胞是共同連接到底部字線，在選取 出底部字線時，視底部字線與頂部字線的位準而定，將 貝料寫入到浮動閘極中，並且視浮動閘極内電荷的極性 狀態而定，依據浮動通道中被感應出的不同通道電阻， 來讀取資料。 在另一實施例中，浮動閘記憶體裝置包括複數個串聯 連接的記憶胞、一選擇性連接複數個記憶胞到位元線以 反應第一選擇信號的第一切換單元、與一選擇性連接複 數個記憶胞到感測線以反應第二選擇信號的第二切換單 凡。在複數個串聯連接的記憶胞中，經由位元線施加上 去的資料，視施加到頂部字線與底部字線上的電壓而 定，而儲存在浮動閘極中，或將儲存在浮動閘極中的資 料輸出到位元線上。在此，每個複數個記憶胞都包括一 在底郤子線上形成的第一絕緣層、一 Ρ型浮動通道、在浮 動通道二側上形成的一 Ν型汲極區與一 源極區、一在 ρ型π動通道上形成的第二絕緣層、一在第二絕緣層上形 成的浮動閘極、與_在浮動閘極上且在頂部字線下形成 的第三絕緣層。在第一絕緣層上形成的Ρ型浮動通道之電 阻會視浮動閘極的極性而改變。 在另一實施例中，浮動閘記憶體裝置包括複數個配置 101040.doc 1297216 成平行於列方向上複數個底部字線的頂部字線、複數個 配置成行方向上的位元線、複數個配置成垂直於複數個 ，位元線的感測線、複數個記憶胞陣列、與複數個感測放 • 大器複數個記憶胞陣列是配置成在複數個頂部字線、 複數個底部字線、與複數個位元線交錯處。複數個感測 放大器，一個接著一個對應到複數個位元線，會感測並 放大位7G線内的資料。在此，每個複數個記憶胞陣列都 包括複數値串聯連接的記憶胞、一選擇性連接複數個記 響憶胞到位元線以反應第一選擇信號的第一切換單元、與 選擇性連接複數個記憶胞到感測線以反應第二選擇信 號的第二切換單元。在複數個串聯連接的記憶胞中，經 由位元線施加上去的資料，視施加到頂部字線與底部字 線上的電壓而定，而儲存在浮動閘極中，或將儲存在浮 動閘極中的資料輸出到位元線上。複數個記憶胞中的每 個記憶胞都包括-在底部字線上形成的第一絕緣層、一p _ 孓浮動通道在浮動通道二側上形成的一 N型汲極區與 - N型源極區、—在”浮動通道上形成的第二絕緣層'、 一在第二絕緣層上形成的浮動閘極、與一在浮動問極上 且在頂部字線下形成的第三絕緣層。在第一絕緣層上形 成的P型浮動通道之電阻會視浮動閘極的極性而改變。 【實施方式】 將參考所附圖式詳細說明本發明。 2a是顯示出依據本發明實施例平行於浮動閘記憶體 裝置中字線方向所切割開之單元記憶胞的剖示圖。 101040.doc -10- 1297216 立f單7憶胞中，底部字線16是在底層中形成，而頂 η!5:線18疋在頂層中形成。底部字線咐配置成平行於 頁P子線1 8且由相同列的位址解碼器來驅動。 第絕緣層2〇、浮動通道22、第二絕緣層24、浮動閘 極26與第二絕緣層28都是依序在底部字線μ上形成。在 此，浮動通道22是用p型半導體來形成。 圖2b疋顯不出依據本發明實施例垂直於浮動閘記憶體 凌置中子線方向所切割開之單元記憶胞的剖示圖。 在單元記憶胞中，底部字線16是在底層中形成，而頂 邛字線18疋在頂層中形成。底部字線“是配置成平行於 頂部字線1 8。 第一絕緣層20、浮動通道22、第二絕緣層24、浮動閘 極26與第二絕緣層28都是依序在底部字線16上形成。在 此，>^型/及極區30與N型源極區32都是在浮動通道22的二 側上形成。 浮動通道22、N型汲極區30與N型源極區32都是用碳奈 米官、矽、Ge與其它材料中的至少一種材料來形成。 浮動閘δ己憶體裝置的單元記憶胞之通道電阻會隨浮動 閘極26中所儲存的電荷狀態而改變。 亦即，既然電子儲存在浮動閘極26内時，正通道電荷 會被感應到記憶胞的通道中，所以記憶胞會在高電阻通 道狀態下關閉。 同時，既然正電洞儲存在浮動閘極26内時，負電荷會 被感應到記憶胞的通道中，所以記憶胞會在低電限通道 101040.doc 1297216 狀態下打開。 以攻種方式，藉選取出浮動閘極26内的電荷種類，讓 資料被寫人到記憶胞内，使得記憶胞能當作非揮發性記 憶胞來操作。 上述依據本發明實施例的單元記憶胞是由圖2c中的符 號來代表。 圖h至3b是顯示出依據本發明實施例浮動閘記憶體裝 置的高位準資料”1，，的寫入與讀取操作的圖式。 圖3a是顯示出高位準資料”丨，，的寫入操作之圖式。 正電壓+v被施加到底部字線16，而負電壓被施加到 頂部字線18。在此，汲極區3〇與源極區32會變成接地電 壓GND狀態。 此時’當藉第一絕緣層20、第二絕緣層24、第三絕緣 層28間之電容器的電壓分割器，而在浮動間極％與浮動 通道區22間施加電壓時，電子會被發射到通道區22内。 結果’正電荷會在浮動閘極26内累積。 圖3b是顯示出高位準資料"丨”的讀取操作之圖式。 當接地電壓GND施加到底部字線丨6與頂部字線丨8時， 負電荷會被感應到通道區22中，且汲極區30與源極區32 會變成接地狀態，使得通道區22打開。 結果，在讀取模式下，儲存在記憶胞中的資料”丨，，會被 頃取出來。在此’當些微的電壓差被施加到沒極區3 〇與 源極區32時，通道區22打開，使得大量電流流過。 圖4a至4b是顯示出依據本發明實施例浮動閘記憶體裝 101040.doc 1297216 置的低位準資料"0”的寫入與讀取操作的圖式。 圖4 a是顯示出低位準資料"〇"的寫入操作之圖式。 當接地電壓GND施加到汲極區3〇與源極區32，且正電 '** 壓+V被施加到底部字線16與頂部字線18時，通道會打 開’使得通道内形成接地電壓的通道。 既然通道的接地電壓與頂部字線18的正電壓+v之間 形成高電壓差，所以通道區的電子會朝浮動閘極“移 動’使得電子在浮動閘極26内累積。 同時，當正電壓+v被施加到汲極區30與源極區32，而 间位準資料” 1 ”儲存在浮動閘極26内時，通道會關閉，使 得通道内不會形成接地電壓的通道。 既然浮動狀態下通道的正電壓與頂部字線18的正電壓 +v之間沒有形成電壓差，所以電子不會朝浮動閘極26移 動。 結果，浮動閘極26是保持在先前的狀態下。亦即，既 馨 然先前儲存的高位準資料’’ 1 ’’被保持住，所以高位準資料 ’fin會寫入所有記憶胞中，並選擇性的寫入低位準資料 ，，0，，〇 圖4b是顯示出低位準資料”〇”的讀取操作之圖式。 當接地電壓GND施加到底部字線16與頂部字線1 8，而 且些微的電壓差被施加到汲極區30與源極區32時，通道 ' 會關閉，使得少量電流流過。 、 在讀取模式下，底部字線16與頂部字線18都是在接地 電壓狀態下。結果，既然沒有強的電壓施加到浮動問極 101040.doc -13- 1297216 26，所以記憶胞的保持特性有獲得改善。 圖5是顯示出依據本發明實施例之浮動閘記憶體裝置 的佈局平面圖。 參閱圖5，複數個單元記憶胞11(：被配置成在複數個字 線WL與複數個位元線bl交錯處。 頂部字線WL是配置成平行於相同方向上的底部字線 BWL，並垂直於位元線BL。 圖6a是顯示出平行於圖5字線WL之方向A-A，的剖示 圖。 參閱圖6a，複數個單元記憶胞UC是在行方向上的相同 底。P予線16 BWL—1與頂部字線18 WL一1之間形成。 圖6b是顯示出垂直於圖5字線WL之方向B-B，的剖示 圖〇 參閱圖6b ’複數個單元記憶胞uc是在列方向上的相同 位元線BL一1中形成。 圖7疋顯不出依據本發明實施例具多層結構之浮動閘 記憶體裝置的剖示圖〇 參閱圖7 ’形成複數個記憶胞氧化物層 C 0 L 1 〜C Ο 了 zi -r- —，而且複數個浮動閘記憶胞陣列是在剖面 方向上/儿積在一起。結果，在對應到沉積記憶胞陣列數 目的相同面積中，記憶胞的集積容量會增加。 °疋”、、員示出依據本發明另一實施例之浮動閘記憶體 裝置的佈局平面圖。 多閱圖8 ’底部字線16 B WL__S —般是在預設記憶胞陣 101040.doc • 14 - 1297216 列的範圍内使用，雖然圖8類似於圖5。圖8的浮動閘記憶 體裝置包括複數個在行方向上的頂部字線18 W]L、複數 個在列方向上的位元線BL、與複數個配置在複數個頂部 字線18與複數個位元線BL交錯處之單元記億胞uc。 圖9a是顯示出平行於圖8字線WL之方向c_c，的剖示 圖。 參閱圖9a，複數個單元記憶胞1](：是在行方向上相同底 部字線16 BWL一1與相同頂部字線18之間形成。 圖9b是顯示出垂直於圖8字線WL之方向d_d，的剖示 圖。 參閱圖9b，複數個單元記憶胞11(：是在列方向上相同位 凡線BL—1内形成。在此，底部字線16 BWL 一 s一般是連 接在一起。 圖10疋顯不出依據本發明另一實施例具多層結構之浮 動閘記憶體裝置的剖示圖。 參閱圖10，圖8的單元記憶胞^^是沉積成多層結構。 母個單元記憶胞都被複數個記憶胞氧化物層 COL1〜COL4分隔開。 雖然’ N型汲極區30與n型源極區32在p型通道區22二 側形成的實例已解釋過，但是？型汲極區30與p型源極區 32也可以在？型通道區22二側上形成。 圖11疋顯示出依據本發明實施例浮動閘記憶體裝置之 單元記憶胞陣列34的圖式。 在實施例中，圖11的單元記憶胞陣列34包括複數個串 101040.doc -15- 1297216 聯連接^記憶胞Q1〜Q m、與切換單元N i、N 2。在此，第 一切換單元N1具有-閘極’以接收第-選擇信號Sel 1， 選擇性的連接記憶胞⑽彳位城BL，而第：切換單元-N2 ”有閘極’以接收第二選擇信號則―2，選擇性的連接 記憶胞Qm到感測線S/L。 稷數個串聯連接在切換單元N1與N2之間的記憶胞 Q1 Qni會藉;同列位址解碼器所驅動之複數個頂部字線 WL—1 WL—m與複數個底部字線，來選擇 性的進行切換操作。在此，每個記憶胞(^1〜(5111的詳細結 構是顯示於圖2a與2b中。 圖12疋顯不出依據本發明實施例浮動閘記億體裝置之 單元記憶胞陣列結構的圖式。 在貫施例中’圖12的浮動閘記憶體裝置包括複數個單 元記憶胞陣列34、複數個底部字線BWL-1〜BWL一m、複 數個第一選擇信號SEL一 11〜SEL jn、複數個第二選擇信 φ 號SEL-21〜SEL—2n、與複數個列方向上之感測線 S/L一 1〜S/L一η，其中該等複數個單元記憶胞陣列34是共同 連接到複數個行方向上之位元線BL-1〜BL_n，以及共同 連接到複數個頂部字線〜WL_m。在此，複數個位 元線BL-1〜BL__n是一個接著一個連接到複數個感測線 36 〇 圖13是顯示出依據本發明實施例之浮動閘記憶體裝置 的寫入操作之圖式。 在依據本發明實施例之浮動閘記憶體裝置中，寫入操 101040.doc -16- 1297216 作循環可以分割成二附屬操作區。亦即，資料"丨"是在第 -附屬操作區中寫入。在第二附屬操作區中，將第一附 屬操作區所寫入的資料"丨"保存住或寫入資料，，〇"。 當需要保存資料”!"時，如果在預設期間内施加一高電 壓到位元線BL上，則在第一附屬操作區中寫入的資料"厂， 之數值，會在記憶胞中保存下來。 圖14是顯示出依據本發明實施例中浮動閉記憶體裝置 之資料"Γ，的寫人操作時序圖。在此，圖出圖6中 第一單元記憶胞陣列34的第一記憶胞Q1被選取出來的 實例。 首先，在記憶胞的預先充電時間⑺内，所有信號與接 線都被預先充電到接地電壓vss。 在時間tl内，當第一選擇信號SEL i -L—2傳送出，高位準，以打開切換電單元 線BL—1是連接到記憶胞…的源極，而感測線s/l是連接 到記憶胞Qm的汲極。在此，複數個頂部字線 WL—1〜WL-m、複數個底部字線bwL-UWL—m、位元線 BL一1與感測線S/L—1都保持在低位準。 在時間t2内，除連接到已選取記憶胞Q1之底部字線 BWL一1外的剩餘底部字線BWL一2〜BWL—m都會傳送出， 高位準’。結果，除已選取記憶胞Q1外的剩餘記憶胞 Q2〜Qm都會被打開，使得已選取記憶胞Q1的源極連接到 接地電壓VSS。 當負電壓VNEG在時間t3内施加到連接至已選取記憶 101040.doc •17- 1297216 胞Q1的字線WL-1，而且底部字線B WL一 1在時間t4内傳送 出河位準’時，如圖3a所示，則藉頂部字線WL-1與底部 一 字線BWL一1的電壓分割，從浮動閘極26發射出電子，使 •，， 得資料’’ 1"被寫入。 當頂部字線WL-1與底部字線bwL-i在時間〇内被傳 迗到接地電壓vss，且剩餘底部字線BWL—2〜BWL-m在 時間t6内被傳送到接地電壓VSS時，除已選取記憶胞Q1 _ 外的剩餘記憶胞Q2〜Qm都會關閉。 在時間t7内，第一選擇信號SELj與第二選擇信號 SEL一2被傳送到低位準，切換電單元m與N2關閉，使得 寫入操作完成。 圖15是顯示出依據本發明實施例中浮動閘記憶體裝置 之資料”1”的保持操作以及資料”〇”的寫入操作之時序 圖。圖15顯不出圖12中第一單元記憶胞陣列34的第一記 憶胞Q1被選取出來的實例。 _ 首先，在記憶胞的預先充電時間期to内，所有信號與 接線都被預先充電到接地電壓VSS。 在時間tl内，當第一選擇信號SELJ傳送出，高位準， 時，切換電單元m打開，使得位元線連接到記憶胞 Q1的源極。 - 在此，第二選擇信號SEL_2、複數個頂部字線 ；WL-1〜WL-m、複數個底部字線B WL_ 1〜B WL_m、位元線 ， BL—1、與感測線s/L—1都保持在低位準。 在時間t2内，所有底部字線]5|乙一1〜3貿1^一瓜都會傳送 101040.doc -18· 1297216 出，高位準，。結果，記憶胞Q1〜Qm都打開，經底部字線 BWL—1〜BWL—m而連接到位元線BL，使得所有施加到位 元線BL上的資料都被傳送到所有的記憶胞Q1〜Qm。 在時間t3内，當要寫入記憶胞Q1内的資料是”〇，，時，位 凡線BL一1會持續保持在接地電壓VSS狀態，而且當需要 保持住儲存在已選取記憶胞q 1中的資料”丨，，時，位元線 BL-1會傳送出’高位準’。 在時間t4内，當連接到已選取記憶胞qi的頂部字線 WL-1傳送出•高位準，時，如圖4a所示，電子會藉頂部字 線WL一1 ’而在已選取記憶胞卩丨的？型通道區22内累積。 因此，當正電壓施加到頂部字線WLj以產生臨界電壓差 時，通道電子會注入到浮動閘極26内。結果，資料，，〇，，被 寫入到已選取記憶胞Q 1内。 同時’當需要保持住儲存在已選取記憶胞q 1中的資枓 Π1 ”時，高位準電壓會被施加到位元線BL-1，使得位元線 BL」的電壓被施加到已選取記憶胞。結果，既然避免 在通道區22内形成電子，所以資料"丨，，可以保持住。 頂部字線WL-1在時間t5内再一次被傳送到接地電壓 VSS狀態，且所有底部字線BWL-1〜BWL—m與位元線 BL-1在時間t6内被傳送到接地電壓vss，使得所有記憬 胞Q1〜Qm都關閉。 在時間t7内，當第一選擇信號sel一1被傳送到低位準 時，切換電單元N1會關閉，使得寫入操作完成。 圖1 6是顯示出依據本發明實施例中浮動閘記憶體裝置 101040.doc -19- 1297216 中所儲存之資料的感測操作時序圖。 首先，在記憶胞的預先充電時間_，所有信號與接 線都被預先充電到接地電壓VSS。 在時間tl内，當第一 SEL_2被傳送到高位準 選擇信號SEL—1與第二選擇信號 ’使得切換電單元N1與N2打開Several dirty gate memory cells. Here, the floating gate memory cell includes a bottom sub-line, a first insulating layer formed on the bottom word line, a p-type floating channel opened on the first, and the rim edge layer and maintained in a floating state, a second insulating layer formed on the p-type ocean moving channel, a floating gate, a third insulating layer formed on the floating gate, a top word line formed on the third insulating layer, and a floating channel 2 An N-type drain region and an -N-type source region are formed on the side. What is stored in the floating gate formed on the second insulating layer. Here, depending on the level of the bottom word line and the top word line, the bead material is written into the floating gate ' and the polarity state of the charge in the floating gate is $, depending on the difference induced in the floating channel. Channel resistance to read data. "In another embodiment, the floating gate memory device includes a plurality of single memory cell arrays. Each of the plurality of cell memory cell arrays includes a latent gate memory cell. Here, the floating gate memory The cell includes a first insulating layer formed on the bottom word line, a p-type floating channel formed on the first, ', 邑, 彖 layer and maintained in a floating state, and a second formed on the b (four) track a second insulating layer, a floating gate, a third insulating layer formed on the movable gate of 101040.doc 1297216, a top word line formed on the third insulating layer, and a 1 formed on two sides of the floating channel a type of drain region and an N-type source region. Charges are stored in the floating gate formed on the second insulating layer. Here, a plurality of floating gate memories in each of the plurality of unit memory cell arrays The cells are commonly connected to the bottom word line. When the bottom word line is selected, depending on the level of the bottom word line and the top word line, the buck is written into the floating gate, and the charge in the floating gate is considered. Depending on the polarity state, it is induced according to the floating channel In another embodiment, the floating gate memory device includes a plurality of memory cells connected in series, and a first selectively connected plurality of memory cells to the bit line to reflect the first selection signal. a switching unit, and a second switching unit that selectively connects the plurality of memory cells to the sensing line to reflect the second selection signal. In the plurality of serially connected memory cells, the applied data is applied via the bit line, The top word line and the voltage on the bottom word line are stored in the floating gate, or the data stored in the floating gate is output to the bit line. Here, each of the plurality of memory cells includes a bottom but a first insulating layer formed on the sub-line, a 浮动-type floating channel, a 汲-type drain region and a source region formed on two sides of the floating channel, and a second insulating layer formed on the p-type π-moving channel, a floating gate formed on the second insulating layer, and a third insulating layer formed on the floating gate and under the top word line. The resistance of the meandering floating channel formed on the first insulating layer is regarded as floating In another embodiment, the floating gate memory device includes a plurality of configurations 101040.doc 1297216 into a top word line parallel to a plurality of bottom word lines in the column direction, and a plurality of configurations are arranged in a row direction a bit line, a plurality of pixels arranged perpendicular to the plurality of bits, a sense line of the bit line, a plurality of memory cell arrays, and a plurality of sense amplifiers, and the plurality of memory cell arrays are configured to be in a plurality of top word lines a plurality of bottom word lines interleaved with a plurality of bit lines. The plurality of sense amplifiers, one after the other corresponding to the plurality of bit lines, sense and amplify the data in the 7G line. Here, each The plurality of memory cell arrays comprise a plurality of memory cells connected in series, a first switching unit that selectively connects a plurality of memory cells to the bit line to reflect the first selection signal, and selectively connects the plurality of memory cells to each other. The line is measured to reflect a second switching unit of the second selection signal. In a plurality of memory cells connected in series, the data applied via the bit line depends on the voltage applied to the top word line and the bottom word line, and is stored in the floating gate or stored in the floating gate. The data is output to the bit line. Each of the plurality of memory cells includes a first insulating layer formed on the bottom word line, a p-type 孓 floating channel formed on both sides of the floating channel, and an N-type drain region and an -N source. a region, a second insulating layer formed on the "floating channel", a floating gate formed on the second insulating layer, and a third insulating layer formed on the floating gate and under the top word line. The resistance of the P-type floating channel formed on an insulating layer varies depending on the polarity of the floating gate. [Embodiment] The present invention will be described in detail with reference to the accompanying drawings. 2a is shown to be parallel to a floating gate according to an embodiment of the present invention. A cross-sectional view of the cell memory cell cut by the word line direction in the memory device. 101040.doc -10- 1297216 In the memory cell, the bottom word line 16 is formed in the bottom layer, and the top η!5: line 18疋 is formed in the top layer. The bottom word line 咐 is arranged parallel to the page P sub-line 18 and is driven by the address decoder of the same column. The first insulating layer 2〇, the floating channel 22, the second insulating layer 24, the floating The gate 26 and the second insulating layer 28 are sequentially formed on the bottom word line μ Here, the floating channel 22 is formed using a p-type semiconductor. Fig. 2b shows a cross-sectional view of a cell memory cell cut perpendicular to the direction of the neutron line of the floating gate memory in accordance with an embodiment of the present invention. In the cell memory cell, the bottom word line 16 is formed in the bottom layer and the top word line 18 is formed in the top layer. The bottom word line "is arranged parallel to the top word line 18. The first insulating layer 20, the floating channel 22, the second insulating layer 24, the floating gate 26 and the second insulating layer 28 are all formed sequentially on the bottom word line 16. Here, the >^//polar region 30 and the N-type source region 32 are both formed on both sides of the floating channel 22. The floating channel 22, the N-type drain region 30 and the N-type source region 32 are each formed of at least one of carbon nanotubes, germanium, Ge, and other materials. The channel resistance of the cell memory cell of the floating gate δ memory device varies with the state of charge stored in the floating gate 26. That is, since the electrons are stored in the floating gate 26, the positive channel charge is induced into the channel of the memory cell, so the memory cell is turned off in the high resistance channel state. At the same time, since the positive hole is stored in the floating gate 26, the negative charge is induced into the channel of the memory cell, so the memory cell is turned on in the low power channel 101040.doc 1297216 state. In the attack mode, by selecting the type of charge in the floating gate 26, the data is written into the memory cell, so that the memory cell can operate as a non-volatile memory cell. The unit cell described above in accordance with an embodiment of the present invention is represented by the symbol in Figure 2c. Figures h to 3b are diagrams showing the writing and reading operations of the high level data "1" of the floating gate memory device in accordance with an embodiment of the present invention. Figure 3a is a diagram showing the writing of high level data "丨," Enter the operation diagram. A positive voltage +v is applied to the bottom word line 16, and a negative voltage is applied to the top word line 18. Here, the drain region 3A and the source region 32 become the ground voltage GND state. At this time, when the voltage divider of the capacitor between the first insulating layer 20, the second insulating layer 24, and the third insulating layer 28 is applied, and a voltage is applied between the floating gate % and the floating channel region 22, electrons are emitted. Go to channel area 22. As a result, a positive charge will accumulate in the floating gate 26. Figure 3b is a diagram showing the read operation of the high level data "丨.) When the ground voltage GND is applied to the bottom word line 丨6 and the top word line 丨8, a negative charge is induced into the channel region 22, And the drain region 30 and the source region 32 will become grounded, so that the channel region 22 is opened. As a result, in the read mode, the data stored in the memory cell "丨" will be taken out. Here, when a slight voltage difference is applied to the non-polar region 3 〇 and the source region 32, the channel region 22 is opened, so that a large amount of current flows. 4a to 4b are diagrams showing the writing and reading operations of the low level data "0" of the floating gate memory device 101040.doc 1297216 according to an embodiment of the present invention. Fig. 4a is a view showing low level information. "〇" The pattern of the write operation. When the ground voltage GND is applied to the drain region 3〇 and the source region 32, and the positive voltage '** voltage + V is applied to the bottom word line 16 and the top word line At 18 o'clock, the channel will open a channel that causes the ground voltage to form in the channel. Since the ground voltage of the channel forms a high voltage difference with the positive voltage +v of the top word line 18, the electrons in the channel region "move" toward the floating gate. 'Enabling electrons to accumulate in the floating gate 26. Meanwhile, when a positive voltage +v is applied to the drain region 30 and the source region 32, and the inter-level data "1" is stored in the floating gate 26, the channel is closed, so that no ground voltage is formed in the channel. aisle. Since no voltage difference is formed between the positive voltage of the channel in the floating state and the positive voltage +v of the top word line 18, the electrons do not move toward the floating gate 26. As a result, the floating gate 26 is maintained in the previous state. That is, the high-level data ''1'' that was previously stored is kept, so the high-level data 'fin will be written into all memory cells, and the low-level data will be selectively written, 0, 〇 Figure 4b is a diagram showing the read operation of the low level data "〇". When the ground voltage GND is applied to the bottom word line 16 and the top word line 18, and a slight voltage difference is applied to the drain region 30 and the source region 32, the channel 'is turned off, causing a small amount of current to flow. In the read mode, the bottom word line 16 and the top word line 18 are both in the ground voltage state. As a result, since no strong voltage is applied to the floating pole 101040.doc -13-1297216 26, the memory cell retention characteristics are improved. Figure 5 is a plan view showing the layout of a floating gate memory device in accordance with an embodiment of the present invention. Referring to FIG. 5, a plurality of cell memory cells 11 (: are configured to be interleaved with a plurality of word lines WL and a plurality of bit lines bl. The top word line WL is configured to be parallel to the bottom word line BWL in the same direction, and Vertical to the bit line BL. Fig. 6a is a cross-sectional view showing the direction AA parallel to the word line WL of Fig. 5. Referring to Fig. 6a, a plurality of unit memory cells UC are the same bottom in the row direction. BWL-1 is formed between the top word line 18 WL-1. Fig. 6b is a cross-sectional view showing the direction BB perpendicular to the word line WL of Fig. 5, see Fig. 6b 'Multiple cell memory cells uc are in the column direction FIG. 7 is a cross-sectional view showing a floating gate memory device having a multi-layer structure according to an embodiment of the present invention. Referring to FIG. 7 'forming a plurality of memory cell oxide layers C 0 L 1 ～C zi zi -r- —, and a plurality of floating gate memory cell arrays are integrated in the cross-sectional direction. As a result, in the same area corresponding to the number of deposited memory cell arrays, the memory cells The accumulation capacity will increase. The staff member shows another implementation according to the present invention. The layout of the floating gate memory device is shown in Figure 8. The bottom word line 16 B WL__S is generally used in the range of the preset memory cell 101040.doc • 14 - 1297216 column, although Figure 8 is similar to Figure 5. The floating gate memory device of FIG. 8 includes a plurality of top word lines 18 W]L in the row direction, a plurality of bit lines BL in the column direction, and a plurality of top word lines 18 and a plurality of elements arranged in the column direction Fig. 9a is a cross-sectional view showing a direction c_c parallel to the word line WL of Fig. 8. Referring to Fig. 9a, a plurality of unit memory cells 1] (: is on the side of the line The upper bottom word line 16 is formed between the BWL-1 and the same top word line 18. Fig. 9b is a cross-sectional view showing the direction d_d perpendicular to the word line WL of Fig. 8. Referring to Fig. 9b, a plurality of unit memory cells 11 (: is formed in the same direction in the column direction as the line BL-1. Here, the bottom word line 16 BWL_s is generally connected together. Fig. 10 shows a multilayer structure according to another embodiment of the present invention. A cross-sectional view of a floating gate memory device. Referring to Figure 10, the cell memory cell of Figure 8 Deposited into a multi-layer structure. The mother cell memory cells are separated by a plurality of memory cell oxide layers COL1 to COL4. Although the 'N-type drain region 30 and the n-type source region 32 are formed on both sides of the p-type channel region 22 An example has been explained, but the ?-type drain region 30 and the p-type source region 32 may also be formed on both sides of the ?-channel region 22. Figure 11A shows a unit of a floating gate memory device in accordance with an embodiment of the present invention. A diagram of the memory cell array 34. In an embodiment, the cell memory cell array 34 of FIG. 11 includes a plurality of strings 101040.doc -15-1297216 connected to the memory cells Q1 to Qm, and the switching cells N i, N 2 . Here, the first switching unit N1 has a -gate' to receive the first selection signal Sel 1, and selectively connects the memory cell (10) to the bit city BL, and the first: switching unit -N2 " has a gate" to receive the second The selection signal is “2”, which selectively connects the memory cell Qm to the sensing line S/L. A plurality of memory cells Q1 Qni connected in series between the switching units N1 and N2 are borrowed; the complex number driven by the same column address decoder The top word line WL-1 WL-m and the plurality of bottom word lines are selectively switched. Here, the detailed structure of each memory cell (^1~5111 is shown in Figs. 2a and 2b). 12 is a diagram showing a structure of a cell memory cell array of a floating gate device according to an embodiment of the present invention. In the embodiment, the floating gate memory device of FIG. 12 includes a plurality of cell memory cell arrays 34, a plurality of bottom word lines BWL-1 to BWLm, a plurality of first selection signals SEL_11 to SELjn, a plurality of second selection signals φ#SEL~SEL-2n, and a plurality of column directions Lines S/L-1 to S/L-η, wherein the plurality of unit memory cell arrays 34 are commonly connected to The bit lines BL-1 to BL_n in the plurality of row directions are connected in common to the plurality of top word lines WL_m. Here, the plurality of bit lines BL-1 to BL__n are connected one after another to the plurality of sensing lines 36. 13 is a diagram showing a write operation of a floating gate memory device in accordance with an embodiment of the present invention. In a floating gate memory device according to an embodiment of the present invention, a write operation 101040.doc -16-1297216 is performed. The loop can be divided into two auxiliary operating areas. That is, the data "丨" is written in the first-affiliated operating area. In the second auxiliary operating area, the data written in the first auxiliary operating area"丨"Save or write data, 〇". When you need to save the data "!", if a high voltage is applied to the bit line BL within the preset period, write in the first auxiliary operation area. The entered data "factor, the value, will be saved in the memory cell. Fig. 14 is a timing chart showing the writing operation of the data of the floating closed memory device according to the embodiment of the present invention. Figure 1 shows the first cell memory cell array in Figure 6. An example of the first memory cell Q1 of 34 is selected. First, all signals and connections are precharged to the ground voltage vss during the precharge time (7) of the memory cell. During time t1, when the first selection signal SEL i -L-2 is transmitted, the high level is opened to open the switching electric unit line BL-1 is connected to the source of the memory cell, and the sensing line s/l is the drain connected to the memory cell Qm. Here, a plurality of The top word lines WL-1 to WL-m, the plurality of bottom word lines bwL-UWL-m, the bit lines BL-1, and the sensing lines S/L-1 are kept at a low level. During time t2, the remaining bottom word lines BWL-2 to BWL-m except for the bottom word line BWL-1 connected to the selected memory cell Q1 are transmitted, and the high level is transmitted. As a result, the remaining memory cells Q2 to Qm except for the selected memory cell Q1 are turned on, so that the source of the selected memory cell Q1 is connected to the ground voltage VSS. When the negative voltage VNEG is applied to the word line WL-1 connected to the selected memory 101040.doc • 17-1297216 cell Q1 at time t3, and the bottom word line B WL-1 is transmitted out of the river level during time t4 As shown in FIG. 3a, the voltage is split from the top word line WL-1 and the bottom word line BWL-1, and electrons are emitted from the floating gate 26, so that the data ''1" is written. When the top word line WL-1 and the bottom word line bwL-i are transferred to the ground voltage vss in time ,, and the remaining bottom word lines BWL-2 to BWL-m are transferred to the ground voltage VSS at time t6, The remaining memory cells Q2~Qm except the selected memory cell Q1_ will be turned off. During time t7, the first selection signal SELj and the second selection signal SEL-2 are transferred to the low level, and the switching electrical units m and N2 are turned off, so that the writing operation is completed. Fig. 15 is a timing chart showing the holding operation of the data "1" of the floating gate memory device and the writing operation of the data "〇" according to the embodiment of the present invention. Fig. 15 shows an example in which the first memory cell Q1 of the first cell memory cell array 34 of Fig. 12 is selected. _ First, all signals and wiring are precharged to the ground voltage VSS during the precharge period of the memory cell. During time t1, when the first selection signal SELJ is transmitted, the high level, the switching electrical unit m is turned on, so that the bit line is connected to the source of the memory cell Q1. - Here, the second selection signal SEL_2, the plurality of top word lines; WL-1 WL WL-m, the plurality of bottom word lines B WL_ 1 to B WL_m, the bit lines, BL-1, and the sensing line s/L -1 are kept at a low level. In time t2, all the bottom word lines]5|B-1~3 Trade 1^One melon will be transmitted 101040.doc -18· 1297216 out, high level. As a result, the memory cells Q1 to Qm are both turned on, and are connected to the bit line BL via the bottom word lines BWL-1 to BWL-m, so that all the data applied to the bit line BL is transmitted to all the memory cells Q1 to Qm. During time t3, when the data to be written into the memory cell Q1 is "〇,, the bit line BL-1 will continue to be maintained at the ground voltage VSS state, and when it is necessary to hold the memory cell q 1 stored. In the data "丨,, the bit line BL-1 will transmit a 'high level'. During time t4, when the top word line WL-1 connected to the selected memory cell qi transmits a high level, as shown in FIG. 4a, the electron will borrow the top word line WL-1' in the selected memory cell. What? The type channel area 22 is accumulated. Therefore, when a positive voltage is applied to the top word line WLj to generate a threshold voltage difference, channel electrons are injected into the floating gate 26. As a result, the data, 〇, is written into the selected memory cell Q 1 . At the same time, when it is necessary to hold the resource 1 stored in the selected memory cell q 1 , a high level voltage is applied to the bit line BL-1, so that the voltage of the bit line BL" is applied to the selected memory cell. . As a result, since the formation of electrons in the channel region 22 is avoided, the data "丨, can be maintained. The top word line WL-1 is again transferred to the ground voltage VSS state during time t5, and all of the bottom word lines BWL-1 BBWL-m and the bit line BL-1 are transferred to the ground voltage vss at time t6, All cell cells Q1~Qm are turned off. During time t7, when the first selection signal sel-1 is transferred to the low level, the switching electric unit N1 is turned off, so that the writing operation is completed. Figure 16 is a timing chart showing the sensing operation of the data stored in the floating gate memory device 101040.doc -19-1297216 in accordance with an embodiment of the present invention. First, at the precharge time _ of the memory cell, all signals and wirings are precharged to the ground voltage VSS. In time t1, when the first SEL_2 is transferred to the high level selection signal SEL-1 and the second selection signal ', the switching electric units N1 and N2 are turned on.
時，位元線BL一1是連接到記憶胞Q1的源極，而感測線s/l 是連接到記憶胞Qm的汲極。在此，複數個頂部字線 WL-1〜WL一m、複數個底部字線BWL—1〜BWL—m、位元線 BL一1與感測線S/L—1都保持在低位準。 在時間t2内，除連接到已選取記憶胞qi之底部字線 BWL一1外的剩餘底部字線BWL一2〜BWL—m都會被傳送到 咼位準。結果’除已選取記憶胞q 1外的剩餘憶胞Q2〜Qm 都會被打開，使得已選取記憶胞Q1的源極連接到接地電 壓 VSS 〇 在此’所有字線WL-1〜WL—m都保持在接地電壓vss 狀態，使得位元線BL-1與感測線S/L-1之間的電流流動 可以由已選取記憶胞Q1内所形成的極性來決定。 在時間t3内，感測放大器致能信號s/Α被傳送到高位 準’以操作感測放大器36。然後，當感測電壓VS被施加 到位元線BLJ時，位元線BL一1内的電流流動是由已選取 記憶胞Q1内所形成之極性來決定 亦即，如圖3b所示，當電流不施加到位元線BL_1時， 要了解的是，資料"1”是被儲存在已選取記憶胞Q1内。 另一方面，如圖4b所示，當超過預設值的電流被施加 101040.doc -20- 1297216 到位元線BL一1時，要了解的是，資料，，〇"是被儲存在已選 取記憶胞Q1内。 在時間t4内，當感測放大器致能信號S/A被傳送到接地 電壓VSS ’使得感測放大器36的操作停止時，位元線bl_1 會诶傳送到低位準，以完成感測操作。 在時間t5内，除連接到已選取記憶胞qi之底部字線 B WL—1外的剩餘底部字線B WL一2〜B WL-m都會被傳送到 低位準’所有記憶胞Q1〜Qm都關閉。 在時間t6内，當第一選擇信號犯乙一丨與第二選擇信號 SEL一2被傳送到低位準，使得切換電單元n丨與N2關閉。 結果，本發明實施例中，在讀取模式下使用ndr〇(非 破壞性讀取）時，記憶胞的資料都不會被破壞掉。 如上所述，依據本發明實施例的浮動閘記憶體裝置具 有使用奈米級浮動閘極的記憶胞結構，來克服尺寸縮小 的現象。 此外，在浮動閘記憶體裝置中，使用複數個記憶胞氧 化物層，讓複數個浮動閘極記憶胞陣列沉積在一起，以 改善對應到已沉積記憶胞陣列之數目的記憶胞集積容 量。 、 雖然發明很容易做不同的修改與其它形式，但是已經 藉圖式中的實例以及在此所做的詳細說明來顯示出特定 的實施例。然而，要了解的是’本發明並不受限於所揭 不出的特定形式。而是’本發明涵蓋所有落在所附申靖 專利範财収義之本發明精神與範圍内的修改、對 101040.doc •21 - 1297216 等、與其它形式。 【圖式簡單說明】 在項元以上洋細的說明μ 月乂及參考數個圖式後，本發明 的其它特點與優點將變得爭 又仔更加明顯，其中： 圖1是顯示出傳統浮動閑纪 ⑺尤憶體裝置的剖示圖； 圖2a是顧示出依據本發 %月實方也例平行於浮動閘記憶體 波置中字線方向所切割間 °』開之早凡記憶胞的剖示圖； 圖2b是顯示出依據本菸 i月員％例垂直於浮動閘記憶體 4置中字線方向所切宝丨】問 w _ 開之早凡記憶胞的剖示圖； 圖2 c是顯示出圖以罩 早凡记憶胞的電路圖； :3二至3b疋顯不出依據本發明實施例浮動閘記憶體裝 置的_資料””的寫入與讀取操作的圖式； 圖4a至4b疋顯不出依據本發明實施例浮動間記憶體装 置的低位準責料"〇’，的寫入與讀取操作的圖式； 圖5疋顯不出依據本發明實施例之浮動閘記憶體裝置 的佈局平面圖； ^ 圖6a是顯示屮 只丁出干仃於圖5字線WL之方向Α-Α，的 圖； 十 圖6乜疋顯示屮击士 丁出垂直於圖5字線WL之方向Β-Β，的剖示 圖； 圖7是顯示屮& 4务1 出依據本發明實施例具多層結構之浮間 記憶體装置的剖示调·， 圖8疋頌不出依據本發明另一實施例之浮動閘記憮體 裝置的佈局平面圖； μ 101040.doc -22- 1297216 圖； 圖9a是顯不出平行於圖8字線WL之方向C-C，的剖 示 圖9b是顯不出垂直於圖8字線wL之方向D_D，的 圖； ^ 圖10是顯不出依據本發明另一實施例具多層結構之浮 動閘記憶體裝置的剖示圖； 子 圖11疋顯不出依據本發明實施例浮動閘記憶體裝置之 單元記憶胞陣列的圖式； 圖12是顯示出依據本發明實施例浮動閘記憶體裝置之 單元記憶胞陣列結構的圖式； 乂 圖13是顯示出依據本發明實施例之浮動閉記 的寫入操作之圖式； 凌置 圖14是顯示出依據本發明實施例中浮動閉記憶 之資料’’ Γ’的寫入操作時序圖； 圖1 5是顯示出依據本發明實施例中浮動閉記情 之資料的保持操作以及資料，，〇，，的寫入二 圖；以及 子序 圖16是顯示出依據本發明實施例中 動閘5己憶體裝詈 中所儲存之資料的感測操作時序圖。 【主要元件符號說明】 p型基板 ^ 30 N型汲極區 、32 N型源極區 >20 第一絕緣層 2 4 101040.doc -23- 1297216 10、26 浮動閘極 12、24 第二絕緣層 14 字線 16 底部字線 18 頂部字線 22 浮動通道 28 第三絕緣層 34 單元記憶胞陣列 36 感測放大器 101040.doc -24-At the time, the bit line BL-1 is connected to the source of the memory cell Q1, and the sensing line s/l is the drain connected to the memory cell Qm. Here, the plurality of top word lines WL-1 to WLm, the plurality of bottom word lines BWL-1 to BWL_m, the bit line BL-1, and the sensing line S/L-1 are kept at a low level. During time t2, the remaining bottom word lines BWL-2 to BWL-m except for the bottom word line BWL-1 connected to the selected memory cell qi are transferred to the 咼 level. As a result, the remaining memory cells Q2~Qm except the selected memory cell q1 are turned on, so that the source of the selected memory cell Q1 is connected to the ground voltage VSS. Here, all word lines WL-1 to WL-m are connected. The ground voltage vss state is maintained such that the current flow between the bit line BL-1 and the sense line S/L-1 can be determined by the polarity formed in the selected memory cell Q1. During time t3, the sense amplifier enable signal s/Α is transmitted to a high level to operate the sense amplifier 36. Then, when the sensing voltage VS is applied to the bit line BLJ, the current flow in the bit line BL-1 is determined by the polarity formed in the selected memory cell Q1, that is, as shown in FIG. 3b, when the current When not applied to the bit line BL_1, it is to be understood that the data "1" is stored in the selected memory cell Q1. On the other hand, as shown in Fig. 4b, when the current exceeding the preset value is applied, 101040. Doc -20- 1297216 When the bit line BL-1 is in place, it is to be understood that the data, 〇" is stored in the selected memory cell Q1. During the time t4, when the sense amplifier enables the signal S/A When transmitted to the ground voltage VSS' such that the operation of the sense amplifier 36 is stopped, the bit line bl_1 is transferred to a low level to complete the sensing operation. In time t5, in addition to the bottom word connected to the selected memory cell qi The remaining bottom word lines B WL-2 to B WL-m outside the line B WL-1 will be transmitted to the low level. All the memory cells Q1~Qm are turned off. During the time t6, when the first selection signal is violated, The second selection signal SEL-2 is transmitted to a low level, so that the switching electrical units n丨 and N2 are off. As a result, in the embodiment of the present invention, when ndr〇 (non-destructive reading) is used in the reading mode, the data of the memory cell is not destroyed. As described above, the floating gate memory according to the embodiment of the present invention. The body device has a memory cell structure using a nano-level floating gate to overcome the size reduction phenomenon. Further, in the floating gate memory device, a plurality of memory cell oxide layers are used to allow a plurality of floating gate memory cell arrays. Deposited together to improve the memory cell accumulation capacity corresponding to the number of deposited memory cell arrays. Although the invention is susceptible to various modifications and other forms, it has been illustrated by the examples in the drawings and detailed descriptions herein. The specific embodiments are shown. However, it is to be understood that the invention is not limited to the specific forms disclosed, but rather, the invention encompasses all inventions falling within the scope of the appended claims. Modifications in spirit and scope, on 101040.doc •21 - 1297216, etc., and other forms. [Simplified description of the schema] Other features and advantages of the present invention will become more apparent after the drawings. FIG. 1 is a cross-sectional view showing a conventional floating idle (7) memory device; FIG. 2a is a diagram showing The %% real side is also parallel to the floating gate memory wave in the middle of the word line direction. The section of the memory cell is opened. Figure 2b shows the % of the month according to the smoke. Gate memory 4 is placed in the middle of the word line direction. 问 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FIG. 4a to FIG. 4b show a low level of the floating memory device according to the embodiment of the present invention. FIG. 4a to FIG. 4b show a low level of the floating memory device according to the embodiment of the present invention. FIG. 5 is a plan view showing the layout of the floating gate memory device according to the embodiment of the present invention; FIG. 6a is a view showing the layout of the floating gate memory device; Figure 图 Α Α 图 图 图 图 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 字 ; 字FIG. 7 is a cross-sectional view showing the direction of the word line WL, and FIG. 7 is a cross-sectional view of the floating memory device having a multi-layer structure according to an embodiment of the present invention. FIG. A layout plan view of a floating gate body device according to another embodiment of the present invention; μ 101040.doc -22- 1297216; FIG. 9a is a cross-sectional view showing a direction CC parallel to the word line WL of FIG. Figure 9b is a view showing a direction D_D perpendicular to the word line wL of Figure 8; Figure 10 is a cross-sectional view showing a floating gate memory device having a multi-layer structure according to another embodiment of the present invention; 11 is a diagram showing a cell memory cell array of a floating gate memory device according to an embodiment of the present invention; FIG. 12 is a diagram showing a cell memory cell array structure of a floating gate memory device according to an embodiment of the present invention; 13 is a diagram showing a write operation of a floating close in accordance with an embodiment of the present invention; FIG. 14 is a timing chart showing a write operation of a floating closed memory data ''Γ' according to an embodiment of the present invention; FIG. Figure 15 shows the floating closure in accordance with an embodiment of the present invention. The holding operation of the data of the essay and the writing of the data, 〇, 、, and the sub-sequence 16 are the sensing of the data stored in the slamming device 5 according to the embodiment of the present invention. Operation timing diagram. [Major component symbol description] p-type substrate ^ 30 N-type drain region, 32 N-type source region > 20 first insulating layer 2 4 101040.doc -23- 1297216 10, 26 floating gate 12, 24 second Insulation Layer 14 Word Line 16 Bottom Word Line 18 Top Word Line 22 Floating Channel 28 Third Insulation Layer 34 Cell Memory Cell Array 36 Sense Amplifier 101040.doc -24-