KR100636927B1 - Float gate memory device - Google Patents

Abstract

The float gate memory device of the present invention improves retention characteristics in a nano scale float gate memory device, and a plurality of float gate cell arrays are stacked in a vertical direction using a plurality of cell insulating layers to accumulate cells. Disclosed is a technique for increasing capacity. To this end, according to the potential applied to the upper word line and the lower word line, a plurality of serially connected memory cells in which data applied through the bit line is stored in the float gate, or data stored in the float gate is output to the bit line; A first switching element selectively connecting the bit line and the plurality of memory cells according to the state of the first selection signal; And a plurality of unit memory cell arrays including a second switching element selectively connecting the sensing line and the plurality of memory cells according to the state of the second selection signal.

Description

Float gate memory device

1 is a cross-sectional view of a memory cell of a float gate memory device according to the prior art.

2A is a cross-sectional view of a unit memory cell cut in a direction parallel to a word line.

2B is a cross-sectional view of the unit memory cell cut in a direction perpendicular to the word line.

FIG. 2C is a circuit diagram in which a unit memory cell illustrated in FIG. 2B is defined in a circuit.

3A and 3B are diagrams for describing an operation of reading and writing data " 1 " of the float gate memory device according to the present invention.

4A and 4B are diagrams for describing an operation of reading and writing data " 0 " of the float gate memory device according to the present invention.

5 is a diagram illustrating a unit memory cell array 34 of a float gate memory device according to the present invention.

6 illustrates a memory cell array structure of a float gate memory device according to the present invention.

7 is a view for explaining a write operation of the float gate memory device according to the present invention.

8 is a timing diagram illustrating a data “1” write operation of the float gate memory device according to the present invention.

9 is a timing diagram illustrating an operation of holding data " 1 " or writing data " 0 " in a float gate memory device according to the present invention.

10 is a timing diagram illustrating an operation of sensing data stored in a memory cell of a float gate memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a float gate memory device, and more particularly to improving retention characteristics in a nano scale float gate memory device and using a plurality of cell insulating layers to provide a plurality of floats. Gate cell arrays are stacked in a vertical direction to increase cell integration capacity.

1 is a cross-sectional view of a memory cell of a float gate memory device according to the prior art.

The memory cell of the float gate memory device includes an N-type drain region 4 and an N-type source region 6 formed on the P-type substrate 2, and includes a first insulating layer sequentially formed on the channel region. 8), a float gate 10, a second insulating layer 12, and a word line 14.

In the memory cell of the conventional float gate memory device having such a configuration, the channel resistance of the memory cell is changed by the state of the charge (Carge) stored in the float gate 10.

In other words, if electrons are stored in the float gate 10, positive channel charges are induced in the channel, so that the memory cell is in a high resistance channel state and is turned off.

On the other hand, when holes are stored in the float gate 10, negative channel charges are induced in the channel, and thus the memory cell is in a low resistance channel state.

As such, the type of charge of the float gate 10 is selected and used to operate as a nonvolatile memory cell.

However, the memory cell of the above-described conventional float gate memory device has a problem in that it is difficult to implement normal operation due to a scale down and retention characteristics.

In particular, the nano gate-level float gate structure memory cells are weak in low voltage stress, and thus, a method of applying an arbitrary voltage to a word line during a read operation cannot be applied. have.

An object of the present invention to solve the above problems is to enable the memory cell of the nanoscale level charge trap insulator structure to operate at a low voltage.

Another object of the present invention for solving the above problems is to increase the cell integration capacity by stacking a plurality of charge trap insulator cell array in a vertical direction using a plurality of cell insulating layers.

According to the float gate memory device of the present invention for achieving the above object, the data applied through the bit line is stored in the float gate according to the potential applied to the upper word line and the lower word line, or the data stored in the float gate is A plurality of serially connected memory cells output as bit lines; A first switching element selectively connecting any one of a bit line and the plurality of memory cells according to a state of a first selection signal; And a second switching element configured to selectively connect one of a sensing line and another one of the plurality of memory cells according to a state of a second selection signal, wherein the plurality of memory cells have a first insulation formed on the lower word line. layer; A P-type float channel formed on the first insulating layer and having a resistance changed according to the polarity of the float gate; An N-type drain region and an N-type source region formed on both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The float gate formed on the second insulating layer; And a third insulating layer formed above the float gate and below the upper word line.

In addition, the float gate memory device of the present invention for achieving the above object is a plurality of upper word lines and a plurality of lower word lines arranged in the horizontal direction and parallel to each other; A plurality of bit lines arranged in the longitudinal direction; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; A plurality of memory cell arrays disposed in an area where the plurality of upper word lines and the plurality of lower word lines and the plurality of bit lines cross each other; And a plurality of sense amplifiers for sensing and amplifying data on the bit lines in a one-to-one correspondence with the plurality of bit lines, wherein each of the plurality of memory cell arrays comprises an upper word line and a lower word line. A plurality of serially connected memory cells in which data applied through a bit line is stored in a float gate according to a potential applied to the float gate, or data stored in the float gate is output to the bit line; A first switching element selectively connecting any one of a bit line and the plurality of memory cells according to a state of a first selection signal; And a second switching element configured to selectively connect one of a sensing line and another one of the plurality of memory cells according to a state of a second selection signal, wherein the plurality of memory cells have a first insulation formed on the lower word line. layer; A P-type float channel formed on the first insulating layer and having a resistance changed according to the polarity of the float gate; An N-type drain region and an N-type source region formed on both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The float gate formed on the second insulating layer; And a third insulating layer formed above the float gate and below the upper word line.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A is a cross-sectional view of a unit memory cell cut in a direction parallel to a word line.

First, a bottom word line 16 is formed in the bottom layer, and an upper word line 18 is formed in the top layer. The lower word line 16 and the upper word line are arranged in parallel with each other.

The first insulating layer 20, the float channel 22, the second insulating layer 24, the float gate 26, and the third insulating layer 28 are sequentially formed on the lower word line 10. . Here, the float channel 22 is formed using a P-type semiconductor.

2B is a cross-sectional view of the unit memory cell cut in a direction perpendicular to the word line.

First, a bottom word line 16 is formed on the bottom layer, and an upper word line 18 is formed on the top layer. The lower word line 16 and the upper word line are arranged in parallel with each other.

The first insulating layer 20, the float channel 22, the second insulating layer 24, the float gate 26, and the third insulating layer 28 are sequentially formed on the lower word line 10. . Here, the N type drain 30 and the N type source 32 are formed on both sides of the float channel 22.

In addition, the float channel 22, the N-type drain 30, and the N-type source 32 may be in the form of carbon nanotubes, or may be formed of silicon, germanium, or other materials. have.

In the unit memory cell of the float gate memory device according to the present invention formed as described above, the channel resistance of the memory cell changes according to the state of charge stored in the float gate 26.

That is, if electrons are stored in the float gate 26, the positive cell charge is induced in the channel of the memory cell, and the memory cell is turned off as a high resistance channel state.

On the other hand, if holes are stored in the float gate 26, negative charge is induced in the channel, and the memory cell is turned on in the low resistance channel state.

In this manner, the type of charge of the float gate 26 is selected and used to operate as a nonvolatile memory cell.

The unit memory cell of the present invention having such a configuration is intended to be represented as a symbol shown in FIG. 2C.

3A and 3B are diagrams for describing an operation of writing and reading data “1” of the float gate memory device according to the present invention.

First, FIG. 3A is a conceptual diagram illustrating a write operation of data "1".

A positive voltage + V is applied to the lower word line 16 and a negative voltage -V is applied to the upper word line 18. At this time, the drain region 30 and the source region 32 are in a ground voltage GND state.

In this case, when voltage is applied between the float gate 26 and the channel region 22 by voltage distribution of a capacitor between the first insulating layer 20, the second insulating layer 24, and the third insulating layer 28. In order to accumulate positive charge in the float gate 26, electrons are released to channel zero. Accordingly, the float gate 26 is in a state where positive charges are accumulated.

3B is a conceptual diagram illustrating a read operation of data "1".

When the ground voltage GND is applied to the lower word line 16 and the upper word line 18, negative charge is induced in the channel region 22, and the drain region 30 and the source region 32 are in a ground state. The channel region 22 is turned on.

Accordingly, data “1” stored in the memory cell can be read in the read operation mode. At this time, when a slight voltage difference is applied to the drain region 30 and the source region 32, a large current flows because the channel region 22 is in an on state.

4A and 4B are diagrams for describing an operation of reading and writing data " 0 " of the float gate memory device according to the present invention.

First, FIG. 4A is a conceptual diagram illustrating a write operation of data "0".

When the ground voltage GND is applied to the drain region 30 and the source region 32, and the positive voltage + V is applied to the lower word line 16 and the upper word line 18, the channel is turned on and the channel is turned on. A channel of ground voltage is formed.

Since a high voltage is formed between the ground voltage of the channel and the positive voltage + V of the upper word line 18, electrons in the channel region move to the float gate 26, and electrons accumulate in the gate gate 26.

On the other hand, if a positive voltage + V is applied to the drain region 30 and the source region 32 while data " 1 " is stored in the float gate 26, the channel is turned off to form a channel having a ground voltage in the channel. I can't.

Since there is no voltage between the positive voltage of the floating state of the channel and the positive voltage + V of the upper word line 18, no movement of electrons to the float gate 26 occurs.

Thus, float gate 26 remains in its previous state. That is, since previously stored data "1" is retained, data "1" can be written to all memory cells and data "0" can be selectively written.

4B is a conceptual diagram illustrating a read operation of data "0".

When the ground voltage GND is applied to the lower word line 16 and the upper word line 18, and a slight voltage difference is applied between the drain region 30 and the source region 32, a small off current flows because the channel is off. .

Accordingly, in the read mode as described above, voltage stress is not applied to the float gate using the lower word line 16 and the upper word line 18 as the ground voltage, thereby improving the retention characteristics of the memory cell.

5 is a diagram illustrating a unit memory cell array 34 of a float gate memory device according to the present invention.

The unit memory cell array 34 includes a plurality of memory cells Q1 to Qm and switching elements N1 and N2. Here, the plurality of memory cells Q1 to Qm are connected in series, and the first switching device N1 is applied with the first selection signal SEL_1 to the gate terminal to selectively connect the bit line BL and the memory cell Q1, and the second switching device N2 is The second selection signal SEL_2 is applied to the gate terminal to selectively connect the sensing line S / L and the memory cell Qm.

The plurality of memory cells Q1 to Qm are selectively connected by the upper word lines WL_1 to WL_m and the lower word lines BWL_1 to BWL_m that are connected in series between the switching elements N1 and N2 and driven by the same row address decoder. The detailed configuration of each of the memory cells Q1 to Qm is as shown in FIGS. 2A and 2B.

6 shows a memory cell array structure of a float gate memory device according to the present invention.

The float gate memory device includes a plurality of unit memory cell arrays 34 illustrated in FIG. 5, and is commonly connected to a plurality of bit lines BL_1 to BL_n in a column direction, and a plurality of upper portions in a row direction. It is commonly connected to the word lines WL_1 to WL_m, the lower word lines BWL_1 to BWL_m, the first selection signals SEL_11 to SEL_1n, the second selection signals SEL_21 to SEL_2n, and the sensing lines S / L_1 to S / L_n. Here, the plurality of bit lines BL_1 to BL_n are connected in one-to-one correspondence with the plurality of sense amplifiers 36.

 7 is a view for explaining a write operation of the float gate memory device according to the present invention.

The write operation cycle of the float gate memory device according to the present invention may be divided into two sub-operation regions. That is, data "1" is written in the first sub-operation area, and data "1" written in the first sub-operation area is stored or data "0" is written in the second sub-operation area.

If a high voltage is applied to the bit line BL for a predetermined period when the data "1" is to be preserved, the value of the data "1" written in the first sub-operation area is stored in the memory cell.

8 is a timing diagram illustrating a data “1” write operation of the float gate memory device according to the present invention. Here, an example in which the first memory cell Q1 of the first unit memory cell array 34 shown in FIG. 6 is selected will be described.

First, the t0 section is a precharge section of the memory cell, and all signals and lines are precharged to the ground voltage VSS.

When the first select signal SEL_1 and the second select signal SEL_2 transition to a high level in the period t1 and the switching elements N1 and N2 are turned on, the bit line BL_1 and the source terminal of the memory cell Q1 are connected, and the sensing line S / L The drain terminal of the memory cell Qm is connected. In this case, the plurality of upper word lines WL_1 to WL_m, the plurality of lower word lines BWL_1 to BWL_m, the bit line BL_1, and the sensing line S / L_1 maintain a low level state.

A plurality of lower word lines BWL_2 to BWL_m, except for the lower word line BWL_1 connected to the selected memory cell Q1, transition to a high level in a period t2. Accordingly, all of the plurality of memory cells Q2 to Qm except the selected memory cell Q1 are turned on so that the source terminal of the selected memory cell Q1 is connected to the ground voltage VSS.

When the negative voltage VNEG is applied to the word line WL_1 connected to the selected memory cell Q1 in the t3 period, and the lower word line BWL_1 transitions to the high level in the t4 period, as illustrated in FIG. 3A, the upper word line WL_1 and the lower word are shown. By the voltage distribution of the line BWL_1, electrons can escape from the float gate 26 and write data " 1 ".

The upper word line WL_1 and the lower word line BWL_1 transition to the ground voltage VSS again in the period t5, and the remaining plurality of lower word lines BWL_2 to BWL_m transition to the ground voltage VSS in the period t6, so that the remaining memory cells Q2 other than the selected memory cell Q1 ~ Qm is turned off.

The first selection signal SEL_1 and the second selection signal SEL_2 are transitioned to the low level in the period t7, so that the switching elements N1 and N2 are turned off to complete the write operation.

9 is a timing diagram illustrating an operation of holding data " 1 " or writing data " 0 " in a float gate memory device according to the present invention. Here, an example in which the first memory cell Q1 of the first unit memory cell array 34 shown in FIG. 6 is selected will be described.

First, the t0 section is a precharge section of the memory cell, and all signals and lines are precharged to the ground voltage VSS.

When the first select signal SEL_1 transitions to a high level in a period t1, the first switching device N1 is turned on to connect the bit line BL_1 to the source terminal of the selected memory cell Q1.

In this case, the second selection signal SEL_2, the plurality of upper word lines WL_1 to WL_m, the plurality of lower word lines BWL_1 to BWL_m, the bit lines BL_1, and the sensing line S / L_1 maintain a low level state.

In the period t2, all of the lower word lines BWL_1 to BWL_m transition to a high level. Accordingly, all of the memory cells Q1 to Qm are all turned on, connected to the bit line BL through the lower word lines BWL_1 to BWL_m, and data applied to the bit line BL may be transferred to all the memory cells Q1 to Qm.

If the data to be written to the selected memory cell Q1 is "0" in the period t3, the bit line BL_1 continues to maintain the ground voltage VSS state, and if it is desired to maintain the data "1" stored in the selected memory cell Q1, the bit line BL_1 is high. Transition to level.

Subsequently, when the upper word line WL_1 to which the selected memory cell Q1 is connected in the period t4 transitions to a high level, as shown in FIG. 4A, electrons are transferred to the P-type channel region 22 of the memory cell Q1 selected by the upper word line WL_1. Will accumulate. Therefore, when a positive voltage is applied to the upper word line WL_1 to generate a threshold voltage difference, channel electrons flow into the float gate 26. Accordingly, data "0" can be written to the selected memory cell Q1.

On the other hand, when the data "1" stored in the selected memory cell Q1 is to be kept as it is, a high level voltage is applied to the bit line BL_1 so that the voltage of the bit line BL_1 is applied to the selected memory cell Q1. Accordingly, data "1" can be preserved by preventing electrons from being formed in the channel region 22.

The upper word line WL_1 transitions to the ground voltage VSS again in the period t5, and all the lower word lines BWL_1 to BWL_m and the bit line BL_1 transition to the ground voltage VSS in the period t6, thereby turning off all the memory cells Q1 to Qm.

When the selection signal SEL_1 transitions to the low level in the t7 period, the switching element N1 is turned off to complete the write operation.

10 is a timing diagram illustrating an operation of sensing data stored in a memory cell of a float gate memory device according to the present invention. Here, an example in which the first memory cell Q1 of the first unit memory cell array 34 shown in FIG. 6 is selected will be described.

First, the t0 section is a precharge section of the memory cell, and all signals and lines are precharged to the ground voltage VSS.

When the first selection signal SEL_1 and the second selection signal SEL_2 transition to a high level in the t1 period and the switching elements N1 and N2 are turned on, the bit line BL_1 and the source terminal of the selected memory cell Q1 are connected, and the sensing line S / L And the drain terminal of the memory cell Qm are connected. In this case, the plurality of upper word lines WL_1 to WL_m, the plurality of lower word lines BWL_1 to BWL_m, the bit line BL_1, and the sensing line S / L_1 maintain a low level state.

A plurality of lower word lines BWL_2 to BWL_m, except for the lower word line BWL_1 connected to the selected memory cell Q1, transition to a high level in a period t2. Accordingly, all of the plurality of memory cells Q2 to Qm except the selected memory cell Q1 are turned on so that the source terminal of the selected memory cell Q1 is connected to the ground voltage VSS.

At this time, all of the word lines WL_1 to WL_m maintain the ground voltage VSS state, so that the current flows between the bit line BL_1 and the sensing line S / L according to the polarity formed in the selected memory cell Q1.

When the sense amplifier enable signal S / A becomes high level in the period t3 and the sense amplifier 36 operates to apply the sensing voltage VS to the bit line BL_1, the bit line BL_1 is changed according to the state of the polarity stored in the selected memory cell Q1. The current flow is determined.

That is, as shown in FIG. 3B, when no current is applied to the bit line BL_1, it can be seen that data “1” is stored in the selected memory cell Q1.

On the other hand, as shown in FIG. 4B, it can be seen that when a current of a predetermined value or more is applied to the bit line BL_1, data “0” is stored in the selected memory cell Q1.

When the sense amplifier enable signal S / A becomes the ground voltage VSS in the period t4 and the operation of the sense amplifier 36 is stopped, the bit line BL_1 transitions to the low level to complete the sensing operation.

In the t5 period, the plurality of lower word lines BWL_2 to BWL_m except the lower word line BWL_1 to which the selected memory cell Q1 is connected transition to a low level, thereby turning off all the memory cells Q1 to Qm.

In the period t6, the first selection signals SEL_1 and the second SEL_2 transition to a low level, and the switching elements N1 and N2 are turned off.

As described above, according to the present invention, data of a cell is not destroyed during a read operation using a non-destructive read out (NDRO) method.

As described above, the float gate memory device according to the present invention has an effect of overcoming a scale down phenomenon in a memory cell structure using a nano gate-level float gate.

In addition, the float gate memory device according to the present invention has an effect of stacking a plurality of float gate cell arrays in a cross-sectional direction by using a plurality of cell insulating layers to increase the integrated capacity of a cell by the number of stacks of the cell array.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (18)

A plurality of serially connected memory cells in which data applied through a bit line is stored in a float gate according to a potential applied to upper and lower word lines, or data stored in the float gate is output to the bit line; A first switching element selectively connecting any one of a bit line and the plurality of memory cells according to a state of a first selection signal; And A second switching device for selectively connecting any one of the sensing line and the other of the plurality of memory cells in accordance with the state of the second selection signal, The plurality of memory cells A first insulating layer formed on the lower word line; A P-type float channel formed on the first insulating layer and having a resistance changed according to the polarity of the float gate; An N-type drain region and an N-type source region formed on both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The float gate formed on the second insulating layer; And And a third insulating layer formed above the float gate and below the upper word line. The method of claim 1, When writing data "1" to the selected memory cell, The first switching element and the second switching element are turned on, apply a negative voltage to the upper word line, apply a positive voltage to the lower word line, and the bit line and the sensing line. To a ground voltage. The method of claim 2, And the upper word line of all other memory cells except for the selected memory cell is connected to a ground voltage, and the lower word line is applied with a positive voltage. The method of claim 2, When data "1" stored in the selected memory cell is maintained, The first switching device maintains a turn on state, the second switching device maintains a turn off state, applies a positive voltage to the upper word line and the lower word line, and applies a positive voltage to the bit line. Floating gate memory device, characterized in that for applying. The method of claim 4, wherein And the upper word line of all other memory cells except for the selected memory cell is connected to a ground voltage. The method of claim 2, When data "0" is written to the selected memory cell, The first switching device remains turned on, the second switching device remains turned off, applies a positive voltage to the upper word line and the lower word line, and the bit line is connected to a ground voltage. Float gate memory device, characterized in that for connecting. The method of claim 6, And the upper word line of all other memory cells except for the selected memory cell is connected to a ground voltage. The method of claim 1, When sensing data stored in the selected memory cell, The first switching element and the second switching element maintain a turn-on state, and an upper word line, a lower word line, and the sensing line are connected to a ground voltage, and a sensing voltage is applied to the bit line. Float gate memory device. The method of claim 8, And the upper word line of all other memory cells except for the selected memory cell is connected to a ground voltage. A plurality of upper word lines and a plurality of lower word lines arranged laterally and parallel to each other; A plurality of bit lines arranged in the longitudinal direction; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; A plurality of memory cell arrays disposed in an area where the plurality of upper word lines and the plurality of lower word lines and the plurality of bit lines cross each other; And a plurality of sense amplifiers configured to sense and amplify data loaded on the bit lines in a one-to-one correspondence with the plurality of bit lines. Each of the plurality of memory cell arrays A plurality of serially connected memory cells in which data applied through a bit line is stored in a float gate according to a potential applied to upper and lower word lines, or data stored in the float gate is output to the bit line; A first switching element selectively connecting any one of a bit line and the plurality of memory cells according to a state of a first selection signal; And A second switching device for selectively connecting any one of the sensing line and the other of the plurality of memory cells in accordance with the state of the second selection signal, The plurality of memory cells A first insulating layer formed on the lower word line; A P-type float channel formed on the first insulating layer and having a resistance changed according to the polarity of the float gate; An N-type drain region and an N-type source region formed on both sides of the P-type float channel; A second insulating layer formed on the P-type float channel; The float gate formed on the second insulating layer; And And a third insulating layer formed above the float gate and below the upper word line. The method of claim 10, When writing data "1" to the selected memory cell, The first switching element and the second switching element are turned on, apply a negative voltage to the upper word line, apply a positive voltage to the lower word line, and the bit line and the sensing line. To a ground voltage. The method of claim 11, The upper word line of all other memory cells except the selected memory cell of the memory cell array to which the selected memory cell is connected is connected to a ground voltage, and the lower word line is applied with a positive voltage. Gate memory device. The method of claim 11, When data "1" stored in the selected memory cell is maintained, The first switching device maintains a turn on state, the second switching device maintains a turn off state, applies a positive voltage to the upper word line and the lower word line, and applies a positive voltage to the bit line. Floating gate memory device, characterized in that for applying. The method of claim 13, And the upper word line of all other memory cells except the selected memory cell in the memory cell array to which the selected memory cell is connected is connected to a ground voltage. The method of claim 11, When data "0" is written to the selected memory cell, The first switching device remains turned on, the second switching device remains turned off, applies a positive voltage to the upper word line and the lower word line, and the bit line is connected to a ground voltage. Float gate memory device, characterized in that for connecting. The method of claim 15, And the upper word line of all other memory cells except the selected memory cell in the memory cell array to which the selected memory cell is connected is connected to a ground voltage. The method of claim 10, When sensing data stored in the selected memory cell, The first switching element and the second switching element maintain a turn-on state, and an upper word line, a lower word line, and the sensing line are connected to a ground voltage, and a sensing voltage is applied to the bit line. Float gate memory device. The method of claim 17, And the upper word line of all other memory cells except the selected memory cell in the memory cell array to which the selected memory cell is connected is connected to a ground voltage.

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