KR100682180B1 - Non-volatile ferroelectric memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device, and discloses a technique for controlling read / write operations of a memory cell array whose channel resistance varies depending on the polarization state of the ferroelectric. According to the present invention, a switching operation of a plurality of memory cells connected in series is selectively controlled according to voltages applied to the plurality of word lines and the plurality of bottom word lines, and the first switching element is controlled according to the activation state of the first selection signal. Selectively switched to selectively connect the bit line and the plurality of memory cells, the second switching element is selectively switched in accordance with the activation state of the second selection signal to selectively connect the sensing line and the plurality of memory cells, the selected memory Control the read / write behavior of the cell.

Description

Non-volatile ferroelectric memory device

1 is a cross-sectional view of a cell of a nonvolatile ferroelectric memory device according to the prior art.

2A through 2C are cell cross-sectional views and symbols of a nonvolatile ferroelectric memory device according to the present invention;

3A to 3C are diagrams for explaining a high data write / read operation of a nonvolatile ferroelectric memory device according to the present invention;

4A to 4C are diagrams for explaining a low data write / read operation of a nonvolatile ferroelectric memory device according to the present invention;

5A and 5B are diagrams for explaining high data retention and read operations of a nonvolatile ferroelectric memory device according to the present invention;

6 illustrates a unit array of a nonvolatile ferroelectric memory device according to the present invention.

7 is a view for explaining a row data read operation of the present invention according to the embodiment of FIG.

8 is a view for explaining a high data read operation of the present invention according to the embodiment of FIG.

FIG. 9 is a detailed configuration diagram of the unit array shown in FIG. 6.

10 illustrates an array of nonvolatile ferroelectric memory devices in accordance with the present invention.

11 is a view for explaining a write operation of a nonvolatile ferroelectric memory device according to the present invention;

12 is a timing diagram related to a high data write operation of a nonvolatile ferroelectric memory device according to the present invention.

13 is an operation timing diagram relating to low data write operation and high data retention of a nonvolatile ferroelectric memory device according to the present invention;

14 is a timing diagram of cell data sensing of a nonvolatile ferroelectric memory device according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device, wherein a nanoscale memory device implements a memory cell whose channel resistance varies according to the polarization state of the ferroelectric in an array to control read / write operations of the nonvolatile memory cell. Technology.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

The unit cell of the conventional nonvolatile ferroelectric memory device includes one switching element connecting a sub bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and one connected between one end of the switching element and a plate line. Of nonvolatile ferroelectric capacitors.

Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

1 is a cross-sectional view of a cell of a nonvolatile ferroelectric memory device according to the prior art.

In a conventional 1-T (FET) field effect transistor (FET) type cell, an N-type drain region 2 and an N-type source region 3 are formed on a P-type region substrate 1. A ferroelectric layer 4 is formed on the channel region, and a word line 5 is formed on the ferroelectric layer 4.

A conventional nonvolatile ferroelectric memory device having such a configuration reads / writes data using a characteristic in which channel resistance of a memory cell varies depending on a polarization state of the ferroelectric layer 4. That is, when the polarity of the ferroelectric layer 4 induces a positive charge in the channel, the memory cell is turned off due to a high resistance state. In contrast, when the polarity of the ferroelectric layer 4 induces a negative charge to the channel, the memory cell is turned into a low resistance state.

However, in such a conventional nonvolatile ferroelectric memory device, when the cell size becomes small, the data retention characteristic is deteriorated, which makes normal cell operation difficult. In other words, when a cell read operation, voltage is applied to an adjacent cell, and data is destroyed, thereby causing interface noise between cells. In addition, since a write voltage is applied to an unselected cell during the write operation of the cell, data of the unselected cells is destroyed, thereby making it difficult to perform a random access operation.

The present invention was created to solve the above problems, and improves data retention characteristics by forming a floating channel layer including an N-type drain region, an N-type channel region, and an N-type source region between a word line and a bottom word line. By doing so, it is possible to improve the reliability of the cell.

In addition, an object of the present invention is to implement the above-described memory cells in an array to control the read / write operation of the memory cells to reduce the overall size of the cells.

In the nonvolatile ferroelectric memory device of the present invention, a switching operation is selectively controlled according to voltages applied to a plurality of word lines and a plurality of bottom word lines, and a plurality of memories having a floating channel layer connected in series. Cell; A first switching element for selectively connecting one of the bit lines and one of the plurality of memory cells according to the state of the first selection signal; And a second switching element configured to selectively connect the sensing line and any other memory cell among the plurality of memory cells according to the state of the second selection signal, each of the plurality of memory cells including a bottom word line; An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state, and a floating channel layer including an N-type drain region and an N-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And a word line formed on the ferroelectric layer.

And, the present invention is a plurality of bit lines arranged in the row direction; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; A plurality of memory cells arranged in rows and columns in a region where a plurality of bit lines and a plurality of sensing lines cross each other; And a plurality of sense amplifiers connected in a one-to-one correspondence with the plurality of bit lines, each of the plurality of memory cells comprising: an insulating layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state, and a floating channel layer including an N-type drain region and an N-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And a word line formed on the ferroelectric layer.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A and 2B are cross-sectional views of unit cells of a nonvolatile ferroelectric memory device according to the present invention.

2A is a cross-sectional view of a unit cell viewed in a direction parallel to a word line.

First, the bottom word line 10 formed in the lowermost layer and the word line 17 formed in the uppermost layer are arranged in parallel. Here, the bottom word line 10 and the word line 17 are selectively driven by the same row address decoder (not shown). In addition, an insulating layer 11 is formed on the bottom word line 10, and a floating channel layer 15 formed of an N-type channel region 12 is formed on the insulating layer 11. Is formed.

In addition, a ferroelectric layer 16 is formed on the floating channel layer 15, and a word line 17 is formed on the ferroelectric layer 16.

2B is a cross-sectional view of the unit cell viewed in a direction perpendicular to the word line.

First, the insulating layer 11 is formed on the bottom word line 10. In addition, a floating channel layer 15 is formed on the insulating layer 11. Here, the drain region 13 and the source region 14 of the floating channel layer 15 are made of N type, and the channel region 12 is made of N type to be in a floating state.

In addition, as the semiconductor of the floating channel layer 15, a material such as carbon nanotube, silicon, or Ge (germanium) may be used. In addition, a ferroelectric layer 16 is formed on the N-type channel region 12 of the floating channel layer 15, and a word line 17 is formed on the ferroelectric layer 16.

The present invention having such a configuration reads and writes data using the characteristic that the channel resistance of the floating channel layer 15 varies depending on the polarization state of the ferroelectric layer 16. That is, when the polarity of the ferroelectric layer 16 induces positive charge in the channel region 12, the memory cell is in a high resistance state and the channel is turned off. On the contrary, when the polarity of the ferroelectric layer 16 induces negative charge in the channel region 12, the memory cell is in a low resistance state and the channel is turned on.

The unit memory cell of the present invention having such a configuration is intended to be represented as a symbol shown in FIG. 2C.

3A to 3C are diagrams for describing a high data write / read operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 3A, a positive voltage <+ V> is applied to the bottom word line 10 and a negative voltage <-V> is applied to the word line 17 in the write operation mode of the data “1”. . At this time, the drain region 13 and the source region 14 are in a ground voltage <GND> state.

In this case, a voltage is applied between the N-type channel region 12 and the ferroelectric layer 16 of the floating channel layer 15 by the voltage distribution of the capacitor between the ferroelectric layer 16 and the insulating layer 11. Accordingly, positive charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 16, resulting in a high resistance state of the memory cell. Accordingly, data "1" can be written to all the memory cells in the write operation mode.

On the other hand, referring to FIGS. 3B and 3C, the ground voltage <GND> or the negative read voltage <-Vrd> is applied to the bottom word line 10 in the read operation mode of the data "1". Then, the ground voltage <GND> is applied to the word line 17.

At this time, the depletion layer 12a is formed under the channel region 12 by the read voltage <-Vrd> applied from the bottom word line 10. A negative charge is induced on the channel region 12 to form a depletion layer 12b. Accordingly, the channel of the channel region 12 is turned off by the depletion layers 12a and 12b formed in the channel region 12 to block the current path from the source region 14 to the drain region 13.

At this time, even if a slight voltage difference is applied between the drain region 13 and the source region 14, a small current flows because the channel region 12 is turned off. Accordingly, data "1" stored in the memory cell can be read in the read operation mode.

4A to 4C are diagrams for describing a low data write / read operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 4A, in the write operation mode of data "0", a positive voltage <+ V> is applied to the bottom word line 10 and a positive voltage <+ Vt / 2 to the word line 17. Apply>. Then, a negative voltage <-Vt / 2> is applied to the drain region 13 and the source region 14.

Here, the voltage Vt is defined as a threshold voltage whose polarity may be changed between the word line 17 and the channel region 12 of the ferroelectric memory cell. That is, the voltage Vt can be about 0.7V, defined as + Vt / 2 = 0.35V, the positive half voltage value of Vt, and -Vt / 2 = -0.35V, the negative half voltage value of Vt. do. Therefore, when a voltage equal to or greater than the threshold voltage Vt is applied between the word line 17 and the channel region 12, the polarity of the ferroelectric layer 16 provided therebetween changes.

At this time, a high voltage is formed between the positive voltage <+ Vt / 2> applied from the word line 17 and the negative voltage <-Vt / 2> formed in the channel region 12. Therefore, a negative charge is induced in the channel region 12 according to the polarity of the ferroelectric layer 16, resulting in a low resistance state of the memory cell. Accordingly, data "0" can be written to the memory cell in the write operation mode.

On the other hand, referring to FIGS. 4B and 4C, the ground voltage <GND> or the negative read voltage <-Vrd> is applied to the bottom word line 10 in the read operation mode of the data "0". Then, the ground voltage <GND> is applied to the word line 17.

At this time, the depletion layer 12a is formed under the channel region 12 by the read voltage <-Vrd> applied from the bottom word line 10. In addition, a positive charge is induced on the channel region 12 so that no depletion layer is formed. Accordingly, the channel region 12 is turned on so that current flows from the source region 14 to the drain region 13. Thus, data "0" stored in the memory cell can be read in the read operation mode. At this time, even if a slight voltage difference is applied to the drain region 13 and the source region 14, a large current flows because the channel region 12 is turned on.

Accordingly, since the voltage line is not applied to the ferroelectric layer 16 by controlling the word line 17 to ground in the read operation mode, the data retention characteristic of the cell can be improved.

5A and 5B are diagrams for explaining a high data retention operation of a nonvolatile ferroelectric memory device according to the present invention.

Referring to FIG. 5A, when data "1" is stored and preserved, a positive voltage <+ V> is applied to the bottom word line 10 and a positive voltage <+ Vt / 2 to the word line 17. Apply>. At this time, when the positive voltage <+ Vt / 2> is applied to the drain region 13 and the source region 14, the channel region 12 is turned off.

In this case, a voltage difference does not occur between the positive voltage of the channel region 12 in the floating state and the positive voltage <+ Vt / 2> of the word line 17. As a result, the polarity change of the ferroelectric layer 16 does not occur and the previous polarity state can be maintained to preserve the data " 1 ".

6 is a diagram illustrating a unit array of a nonvolatile ferroelectric memory device according to the present invention.

The present invention includes switching elements P1 and P2 and a plurality of memory cells Q1 to Qm. Here, the switching element P1 is connected between the bit line BL and the memory cell Q1 to receive the selection signal SEL_1 through the gate terminal. The switching element P2 is connected between the sensing line S / L and the memory cell Qm to apply the selection signal SEL_2 through the gate terminal.

In addition, the plurality of memory cells Q1 to Qm are connected in series between the switching elements P1 and P2 to selectively switch between the word lines WL_1 to WL_m and the bottom word lines BWL_1 to BWL_m. The detailed configuration of each memory cell Q1-Qm is as shown in FIG. 2B. Accordingly, the source terminal of the memory cell Q1 is connected to the switching element P1, and the drain terminal of the memory cell Qm is connected to the switching element P2.

FIG. 7 is a view for explaining a row data read operation of the present invention according to the embodiment of FIG. 6.

First, it is assumed that data "0" is stored in the selected memory cell Q1. In this case, ground voltage <GND> is applied to all word lines WL_1 to WL5, and a negative read voltage <-Vrd> is applied to bottom word line BWL_1 of the selected cell Q1. A positive voltage <+ V> is applied to the remaining plurality of bottom word lines BWL_2 to BWL_m that are not selected. Accordingly, the depletion layer 12a is not formed in the lower portion of the channel region 12 so that the channel is turned on.

On the other hand, in the selected memory cell Q1, the depletion layer 12a is formed under the channel region 12 by the read voltage <-Vrd> applied to the bottom word line 10. Then, a negative charge is induced on the channel region 12 so that a depletion layer does not occur. Accordingly, the channel region 12 is turned on so that current flows from the source region 14 to the drain region 13. Therefore, data "0" stored in the selected memory cell Q1 can be read in the read operation mode.

FIG. 8 is a diagram for describing a high data read operation of the present invention according to the embodiment of FIG. 6.

First, it is assumed that data "1" is stored in the selected memory cell Q1. In this case, ground voltage <GND> is applied to all word lines WL_1 to WL5, and a negative read voltage <-Vrd> is applied to bottom word line BWL_1 of the selected cell Q1. Then, a positive voltage <+ V> is applied to the remaining plurality of bottom word lines BWL_2 to BWL_m that are not selected. As a result, the depletion layer 12a is not formed below the channel region 12, and the channel is turned on.

On the other hand, in the selected memory cell Q1, depletion layers 12a and 12b are formed on and under the channel region 12 by the read voltage <-Vrd> applied to the bottom word line 10. Accordingly, the channel of the channel region 12 is turned off by the depletion layers 12a and 12b formed in the channel region 12 to block the current path from the source region 14 to the drain region 13. Thus, data "1" stored in the selected memory cell Q1 can be read in the read operation mode.

FIG. 9 is a diagram illustrating a connection relationship between the memory cells Q1 and Qm and the switching elements P1 and P2 illustrated in FIG. 6.

The switching elements P1 and P2 have an N-type channel region 21 formed on the insulating layer 20, and the P-type drain region 22 and the P-type source region 23 on both sides of the N-type channel region 21. Is formed. Here, the P-type source region 25 is connected to the bit line BL. The P-type drain region 22 is connected to the N-type source region 14 through the connection line L1. At this time, the connection line L1 connecting the memory cells Q1, Qm and the switching elements P1, P2 is made of a metallic conductor.

10 illustrates an array of nonvolatile ferroelectric memory devices in accordance with the present invention.

According to the present invention, a plurality of unit cell arrays 30 to 33 are provided in a region where a plurality of bit lines BL_1 to BL_n and a plurality of sensing lines S / L_1 to S / L_n cross each other and are arranged in a row and column direction. Each unit cell array 30 to 33 is configured as shown in FIG. 6. The plurality of bit lines BL_1 to BL_n are connected in one-to-one correspondence with the plurality of sense amplifiers 40.

11 illustrates a write operation of a nonvolatile ferroelectric memory device according to the present invention.

The write operation cycle of the present invention can be divided into two sub operation regions. That is, data "1" is written in the first sub-operation area, and data "0" is written in the second sub-operation area.

If data "1" is to be preserved, <+ Vt / 2> voltage is applied to the bit line BL in a predetermined period. Accordingly, the value of the data " 1 " written in the first sub-operation area can be stored in the memory cell.

12 is a timing diagram of data "1" write operation of the nonvolatile ferroelectric memory device according to the present invention.

First, it is assumed that the memory cell Q1 shown in FIG. 6 is selected during the write operation of data "1". The t0 section is defined as a precharge section of the memory cell.

When the selection signal SEL_1 transitions to a negative voltage and the selection signal SEL_2 transitions to a positive voltage in a period t1, the switching element P1 is turned on. Accordingly, the bit line BL is connected to the source terminal of the memory cell Q1.

At this time, the plurality of word lines WL_1 to WL_m maintain the ground state and the plurality of bottom word lines BWL_1 to BWL_m transition to positive voltages. The bit line BL_1 and the sensing line S / L_1 maintain the ground state.

Next, a negative voltage −V is applied to the word line WL_1 connected to the selected memory cell Q1 in the period t3. Accordingly, as shown in FIG. 3A, a high voltage is applied to the ferroelectric layer 16 between the word line WL_1 and the channel region 12 so that the data “1” can be written.

Subsequently, the word line WL_1 transitions to the ground state again in the period t5. When the selection signals SEL_1 and SEL_2 transition to the ground state in the period t7, the switching elements P1 and P2 are turned off. At this time, the sensing line S / L_1, the bit line BL_1, and the remaining unselected word lines WL_2 to WL_m maintain the ground state in all sections.

13 is an operation timing diagram relating to data "0" write operation and data "1" retention of a nonvolatile ferroelectric memory device according to the present invention.

First, it is assumed that the memory cell Q1 shown in Fig. 6 is selected during the write operation of data " 0 ". The t0 section is defined as a precharge section of the memory cell.

When the selection signal SEL_1 transitions to a negative voltage in a period t1, the switching element P1 is turned on. Accordingly, the bit line BL is connected to the source terminal of the memory cell Q1. Then, the selection signal SEL_2 transitions to the value of the positive voltage + V.

In this case, the plurality of word lines WL_1 to WL_m, the bit lines BL_1, and the sensing lines S / L_1 maintain the ground state. All bottom word lines BWL_2 to BWL_m transition to a positive voltage + V level to form a current path.

Accordingly, all of the memory cells Q1 to Qm are connected to the bit line BL through the bottom word lines BWL_1 to BWL_m so that data applied to the bit line BL can be transferred to all the cells Q1 to Qm.

Next, when the data to be written to the memory cell Q1 is "0" in the period t3, the bit line BL_1 transitions to the negative voltage <-Vt / 2> level. On the other hand, in the case where the data "1" stored in the memory cell Q1 is to be retained, the bit line BL_1 transitions to a positive voltage <+ Vt / 2> level.

Subsequently, the word line WL_1 transitions to a positive voltage <+ Vt / 2> level in a period t4. In this case, as shown in FIG. 4A, electrons are accumulated in the channel region 12 of the memory cell Q1 by the bottom word line BWL_1. Accordingly, a positive voltage <+ Vt / 2> is applied to the word line WL_1 and a polarity is formed such that a threshold voltage difference occurs to induce channel electrons in the ferroelectric layer 16. As a result, data "0" can be written in the memory cell Q1.

If the data "1" stored in the memory cell Q1 is to be kept as it is, a positive voltage <+ Vt / 2> is applied to the bit line BL_1 so that the voltage of the bit line BL_1 is applied to the memory cell Q1. Accordingly, data "1" can be preserved by preventing the formation of electrons in the channel region 12.

Subsequently, the word line WL_1 transitions to the ground state again in the period t5. In the period t7, the bottom word lines BWL_1 to BWL_m and the selection signals SEL_1 and SEL_2 transition to the ground state to complete the write operation.

14 is a timing diagram of cell data sensing of a nonvolatile ferroelectric memory device according to the present invention.

First, it is assumed that the memory cell Q1 shown in FIG. 6 is selected during the data sensing operation. The t0 section is defined as a precharge section of the memory cell.

When the selection signals SEL_1 and SEL_2 transition to negative voltages in the period t1, the switching elements P1 and P2 are turned on. Accordingly, the bit line BL and the source terminal of the memory cell Q1 are connected, and the sensing line S / L and the drain terminal of the memory cell Qm are connected.

At this time, the plurality of word lines WL_1 to WL_m and the plurality of bottom word lines BWL_1 to BWL_m maintain the ground state. The sense amplifier 40, the bit line BL_1, and the sensing line S / L_1 maintain the ground state.

Thereafter, the bottom word line BWL_1 connected to the selected memory cell Q1 transitions to a negative voltage in the period t2, and the remaining bottom word lines BWL_2 to BWL_m that are not selected transition to a positive voltage. Accordingly, the remaining memory cells Q2 to Qm except the selected memory cell Q1 are connected to the sensing line S / L_1.

At this time, all of the plurality of word lines WL_1 to WL_m maintain the ground state. Accordingly, the flow of current between the bit line BL_1 and the sensing line S / L is determined according to the polarity state formed in the memory cell Q1.

Subsequently, when the sense amplifier 40 operates in the period t3 and the sensing voltage is applied to the bit line BL_1, the current flow of the bit line BL_1 is determined according to the data stored in the memory cell Q1.

That is, as shown in FIG. 7, when a current equal to or greater than a predetermined value is applied to the bit line BL_1, data “0” is stored in the memory cell Q1. On the other hand, as shown in FIG. 8, it can be seen that data "1" is stored in the memory cell Q1 when no current is applied to the bit line BL_1.

Next, when the operation of the sense amplifier 40 is stopped in the period t4, the bit line BL_1 transitions to the ground state to complete the sensing operation. In addition, the bottom word lines BWL_1 to BWL_m transition to the ground state in a period t5. Thereafter, when the selection signals SEL_1 and SEL_2 transition to the ground state in the period t6, the switching elements P1 and P2 are turned off.

In the present invention, the floating channel layer 15 is composed of an N-type drain region 13, an N-type channel region 12 and an N-type source region 14 in the embodiment, but the present invention is not limited thereto. The floating channel layer 15 may be formed of a P-type drain region, a P-type channel region, and a P-type source region.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

As described above, the present invention does not destroy the data of the cell during the read operation using the Non Destructive Read Out (NDRO) method. Accordingly, the present invention can improve the reliability of the cell during the low voltage operation of the nano-scale ferroelectric cell and improve the read operation speed. In addition, by implementing a plurality of ferroelectric unit cells in an array to control the read / write operation to improve the integrated capacity of the cell and to reduce the overall size.

Claims (20)

A plurality of memory cells in which switching operations are selectively controlled according to voltages applied to the plurality of word lines and the plurality of bottom word lines, respectively, and in which floating channel layers are connected in series; A first switching element for selectively connecting a bit line and one of the plurality of memory cells according to a state of the first selection signal; And A second switching element for selectively connecting the sensing line and any other memory cell among the plurality of memory cells according to the state of the second selection signal, Each of the plurality of memory cells Bottom wordline; An insulating layer formed on the bottom word line; The floating channel layer formed on the insulating layer and having an N-type channel region maintaining a floating state, and an N-type drain region and an N-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And And a word line formed over the ferroelectric layer. The nonvolatile ferroelectric memory device of claim 1, wherein when the high data is written to the plurality of memory cells, the first switching device maintains a turn-on state and the second switching device maintains a turn-off state. . The memory device of claim 1, wherein the selected memory cell of the plurality of memory cells has a positive voltage applied to the bottom word line, a negative voltage applied to the word line, and the bit line and the sensing. A nonvolatile ferroelectric memory device, characterized in that high data is written when a ground voltage is applied to a line. The nonvolatile ferroelectric memory device of claim 3, wherein the floating channel layer is turned into a high resistance state when the polarity of the ferroelectric layer induces positive charge in the channel region. 4. The nonvolatile ferroelectric memory device of claim 3, wherein the plurality of word lines connected to unselected memory cells of the plurality of memory cells maintain a ground state and the plurality of bottom word lines maintain a positive voltage. . 2. The method of claim 1, wherein when writing low data to the plurality of memory cells, the first selection signal transitions to a negative voltage level, and the second selection signal transitions to a positive voltage level. Volatile ferroelectric memory device. 7. The memory cell of claim 1 or 6, wherein the selected memory cell of the plurality of memory cells has a positive voltage applied to the bottom word line and a positive half voltage value Vt / 2 applied to the word line. A threshold voltage at which the polarity of the channel region is changed) is applied, and a low data value is applied when a negative half voltage value -Vt / 2 (where Vt is a threshold voltage at which the polarity of the channel region is changed) is applied to the bit line. A nonvolatile ferroelectric memory device characterized by being light. The nonvolatile ferroelectric memory device of claim 7, wherein the floating channel layer is turned on when the polarity of the ferroelectric layer induces a negative charge in the channel region, thereby turning on the channel. 8. The nonvolatile ferroelectric memory of claim 7, wherein a plurality of word lines connected to unselected memory cells of the plurality of memory cells maintain a ground state and the plurality of bottom word lines maintain a positive voltage level. Device. The nonvolatile ferroelectric memory device of claim 1, wherein the first switching element and the second switching element maintain a turn-on state during a read operation of the plurality of memory cells. The floating channel of claim 1, wherein the selected memory cell of the plurality of memory cells is configured to have a floating voltage applied to a bottom word line and a ground voltage applied to the word line. A nonvolatile ferroelectric memory device, characterized in that it reads data according to a current value flowing in a layer. The nonvolatile ferroelectric of claim 1, wherein the floating channel layer further comprises a connection line connecting the N-type drain and source region, the first switching element, and the second switching element, and formed of a metallic conductor. Memory device. A plurality of bit lines arranged in a row direction; A plurality of sensing lines arranged in a vertical direction with the plurality of bit lines; A plurality of memory cells arranged in rows and columns in a region where the plurality of bit lines and the plurality of sensing lines cross each other; And And a plurality of sense amplifiers connected in one-to-one correspondence with the plurality of bit lines, Each of the plurality of memory cells An insulation layer formed on the bottom word line; The floating channel layer formed on the insulating layer and having an N-type channel region maintaining a floating state, and an N-type drain region and an N-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And And a word line formed over the ferroelectric layer. The method of claim 13, wherein each of the plurality of memory cells A first switching element for selectively connecting a bit line and the plurality of memory cells according to a state of a first selection signal; And And a second switching element for selectively connecting the sensing line and the plurality of memory cells in accordance with the state of the second selection signal. 15. The nonvolatile ferroelectric memory device of claim 14, wherein when the high data is written to the plurality of memory cells, the first switching element maintains a turn-on state and the second switching element maintains a turn-off state. The memory cell of claim 15, wherein a selected voltage of the plurality of memory cells is applied with a positive voltage to the bottom word line, a negative voltage to the word line, and a ground voltage to the bit line and the sensing line. A nonvolatile ferroelectric memory device, characterized in that is applied. 16. The method of claim 15, wherein when the row data is written to the plurality of memory cells, the first selection signal transitions to a negative voltage level, and the second selection signal transitions to a positive voltage level. Volatile ferroelectric memory device. 18. The method of claim 17, wherein the selected memory cell of the plurality of memory cells, a positive voltage is applied to the bottom word line and a positive half voltage value Vt / 2 to the word line, wherein Vt is the polarity of the channel region. The changing threshold voltage), and a negative half voltage value -Vt / 2 (where Vt is a threshold voltage at which the polarity of the channel region is changed) is applied to the bit line. The nonvolatile ferroelectric memory device of claim 15, wherein the first switching element and the second switching element maintain a turn-on state during a read operation of the plurality of memory cells. 20. The current flowing in the floating channel layer of claim 19, wherein a selected memory cell of the plurality of memory cells is configured to have a read voltage having a negative value applied to the bottom word line and a ground voltage applied to the word line. A nonvolatile ferroelectric memory device characterized by reading data according to a value.

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