KR100673116B1 - Non-volatile ferroelectric memory device - Google Patents

Abstract

A nonvolatile ferroelectric memory device is provided to improve the reliability of a cell and to reduce the size of the cell by controlling read/write operations of the cell using a floating channel layer with P type drain, channel and source regions between a word line and a bottom word line. An insulating layer(11) is formed on a bottom word line(10). A floating channel layer(15) is formed on the insulating layer. The floating channel layer is composed of a P type channel region(12), and P type source/drain regions at both sides of the P type channel region. A tunnel oxide layer(16) is formed on the floating channel layer. A ferroelectric layer(17) for storing data is formed on the tunnel oxide layer. A word line parallel with the bottom word line is formed on the ferroelectric layer.

Description

Non-volatile ferroelectric memory device

1 is a cross-sectional view of a cell of a nonvolatile ferroelectric memory device according to the prior art.

2A and 2B are cell cross-sectional views of a nonvolatile ferroelectric memory device in accordance with the present invention.

3A to 3C are diagrams for explaining a high data write / read operation of a nonvolatile ferroelectric memory device according to the present invention;

4A to 4C are diagrams for explaining a low data write / read operation of a nonvolatile ferroelectric memory device according to the present invention;

5 is a layout cross-sectional view of a nonvolatile ferroelectric memory device according to the present invention;

6A and 6B are cross-sectional views of a nonvolatile ferroelectric memory device in accordance with the present invention.

7 is a cross-sectional view of a nonvolatile ferroelectric memory device according to the present invention having a multilayer structure.

8A and 8B illustrate another embodiment of a nonvolatile ferroelectric memory device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device, which controls read / write operations of a nonvolatile memory cell by using a characteristic in which channel resistance of the memory cell is changed according to the polarization state of the ferroelectric in a nanoscale memory device. Technology.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

The unit cell of the conventional nonvolatile ferroelectric memory device includes one switching element connecting a sub bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and one connected between one end of the switching element and a plate line. Of nonvolatile ferroelectric capacitors.

Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

1 is a cross-sectional view of a cell of a nonvolatile ferroelectric memory device according to the prior art.

In a conventional 1-T (FET) field effect transistor (FET) type cell, an N-type drain region 2 and an N-type source region 3 are formed on a P-type region substrate 1. An insulation layer 4 is formed on the channel region, a ferroelectric layer 5 is formed on the insulation layer 4, and a word line is formed on the ferroelectric layer 5. 6) is formed.

A conventional nonvolatile ferroelectric memory device having such a configuration reads / writes data using a characteristic in which channel resistance of a memory cell varies depending on a polarization state of the ferroelectric layer 5. That is, when the polarity of the ferroelectric layer 5 induces a positive charge to the channel, the memory cell is turned off because of a high resistance state. In contrast, when the polarity of the ferroelectric layer 4 induces a negative charge to the channel, the memory cell is turned into a low resistance state.

However, in such a conventional nonvolatile ferroelectric memory device, when the cell size becomes small, the data retention characteristic is deteriorated, which makes normal cell operation difficult. In other words, when a cell read operation, voltage is applied to an adjacent cell, and data is destroyed, thereby causing interface noise between cells. In addition, since a write voltage is applied to an unselected cell during the write operation of the cell, data of the unselected cells is destroyed, thereby making it difficult to perform a random access operation.

In addition, in the case of the conventional metal ferroelectric insulator silicon (MFIS) and the metal ferroelectric metal insulator silicon (MFMIS) as shown in FIG.

That is, when an insulating oxide is present between the ferroelectric layer 5 and the silicon channel region, depolarization charges accumulate between the ferroelectric layer 5 and the insulating layer 4, resulting in deterioration in the storage characteristics of the MFIS. do. Similarly, when a metal insulating layer is present between the ferroelectric layer 5 and the channel region, a polarization charge is accumulated between the ferroelectric layer 5 and the metal, thereby degrading the storage characteristics of the MFMIS.

The present invention has been made to solve the above problems, and has the following object.

First, a floating channel layer including a P-type drain region, a P-type channel region, and a P-type source region is formed between the word line and the bottom word line to control the read / write operation of the memory cell, thereby improving cell reliability. The purpose is to reduce the overall size of the cell.

Second, a tunnel oxide layer is formed between the ferroelectric layer and the channel region to prevent impurities from the ferroelectric layer from diffusing into the channel region and to improve the storage characteristics of the ferroelectric layer.

Nonvolatile ferroelectric memory device of the present invention for achieving the above object, the insulating layer formed on the upper word line; A floating channel layer formed on the insulating layer to maintain a floating state and a P-type drain region and a P-type source region connected to both sides of the channel region; A tunnel oxide layer formed on top of the floating channel layer; A ferroelectric layer formed on the tunnel oxide layer to store data; And a word line formed in parallel with the bottom word line on the ferroelectric layer, and inducing different channel resistances in the channel region according to the polarity of the ferroelectric layer to read / write the data.

In addition, the present invention includes a plurality of bottom word lines; An insulation layer formed on the plurality of bottom word lines; A floating channel layer formed on the plurality of insulating layers and having a plurality of P-type channel regions and a plurality of P-type drain and source regions alternately connected in series with the plurality of P-type channel regions; A tunnel oxide layer formed on top of the floating channel layer; A ferroelectric layer formed on the tunnel oxide layer; And a unit cell array having a plurality of word lines formed in parallel with a plurality of bottom word lines, respectively, on the ferroelectric layer, wherein the unit cell array has different channels in a plurality of P-type channel regions according to polarity of the ferroelectric layer. Inductive resistance is characterized in that the read / write control of a plurality of data.

In addition, the present invention is an insulating layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state, and a floating channel layer including an N-type drain region and an N-type source region connected to both sides of the channel region; A tunnel oxide layer formed on top of the floating channel layer; A ferroelectric layer formed on the tunnel oxide layer to store data; And a word line formed in parallel with the bottom word line on the ferroelectric layer, and inducing different channel resistances in the channel region according to the polarity of the ferroelectric layer to read / write the data.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A and 2B are cross-sectional views of unit cells of a nonvolatile ferroelectric memory device according to the present invention.

2A is a cross-sectional view of a unit cell viewed in a direction parallel to a word line.

First, the bottom word line 10 formed in the lowermost layer and the word line 18 formed in the uppermost layer are arranged in parallel. Here, the bottom word line 10 and the word line 18 are selectively driven by the same row address decoder (not shown). In addition, an insulating layer 11 is formed on the bottom word line 10, and a floating channel layer 15 formed of a P-type channel region 12 is formed on the insulating layer 11. Is formed.

In addition, a tunnel oxide layer 16 is formed on the floating channel layer 15. A ferroelectric layer 17 is formed on the tunnel oxide layer 16, and a word line 18 is formed on the ferroelectric layer 17. Here, the bottom word line 10, the insulating layer 11, the floating channel layer 15, the tunnel oxide layer 16, the ferroelectric layer 17 and the word line 18 are all formed to have the same length.

2B is a cross-sectional view of the unit cell viewed in a direction perpendicular to the word line.

First, an insulating layer 11 having an extended length is formed on the bottom word line 10. In addition, a floating channel layer 15 is formed on the insulating layer 11. Here, the drain region 13 and the source region 14 of the floating channel layer 15 are made of P type, and the channel region 12 is made of P type to be in a floating state. As the semiconductor of the floating channel layer 15, a material such as carbon nanotube, silicon, Ge (germanium), or organic semiconductor may be used.

In addition, a tunnel oxide layer 16 is formed on the P-type channel region 12, the drain region 13, and the source region 14 of the floating channel layer 15. The ferroelectric layer 17 is formed on the tunnel oxide layer 16, and the word line 18 is formed on the ferroelectric layer 17. Here, the insulating layer 11, the floating channel layer 15, the tunnel oxide layer 16 and the ferroelectric layer 17 are all formed of the same length.

The present invention having such a configuration reads and writes data using the characteristic that the channel resistance of the floating channel layer 15 varies according to the polarization state of the ferroelectric layer 17. That is, when the polarity of the ferroelectric layer 17 induces a positive charge in the channel region 12, the memory cell is in a low resistance state and the channel is turned on. On the contrary, when the polarity of the ferroelectric layer 17 induces negative charge to the channel region 12, the memory cell is in a high resistance state and the channel is turned off.

3A and 3C are diagrams for describing a high data write / read operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 3A, the ground voltage <GND> or the negative voltage <-V> is applied to the bottom word line 10 in the write operation mode of the data "1", and the negative voltage is applied to the word line 17. Apply <-V>. At this time, the drain region 13 and the source region 14 are in a ground voltage <GND> state.

In this case, a voltage is applied between the ferroelectric layer 17 and the P-type channel region 12 of the floating channel layer 15 by the voltage distribution of the capacitor between the ferroelectric layer 17 and the insulating layer 11. Accordingly, positive charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 17, resulting in a low resistance state of the memory cell. Accordingly, data "1" can be written to all cells in the memory in the write operation mode.

3B and 3C, on the other hand, in the read operation mode of the data " 1 ", a positive read voltage <+ Vrd> is applied to the bottom word line 10 and the ground voltage is applied to the word line 18. Apply <GND>. At this time, the depletion layer 12a is formed under the channel region 12 by the read voltage <+ Vrd> applied from the bottom word line 10.

In addition, a positive charge is induced on the channel region 12 so that no depletion layer is formed. Accordingly, the channel region 12 is turned on so that current flows from the source region 14 to the drain region 13. Therefore, data "1" stored in the memory cell can be read in the read operation mode. At this time, even if a slight voltage difference is applied to the drain region 13 and the source region 14, a large current flows because the channel region 12 is turned on.

4A and 4B illustrate a low data write / read operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 4A, in the write operation mode of the data "0", the ground word <GND> or the voltage <-V> having a negative value is applied to the bottom word line 10 and the word line 18 is positive. Apply the voltage <+ V>. Then, the ground voltage <GND> is applied to the drain region 13 and the source region 14.

At this time, a high voltage is formed between the positive voltage <+ V> applied from the word line 18 and the ground voltage <GND> formed in the channel region 12. Accordingly, negative charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 17, resulting in a high resistance state of the memory cell. Accordingly, data "0" can be written to the memory cell in the write operation mode.

4B and 4C, on the other hand, in the read operation mode of the data " 0 ", a positive voltage <+ Vrd> is applied to the bottom word line 10, and the ground voltage is applied to the word line 18. FIG. Apply <GND>.

At this time, the depletion layer 12a is formed under the channel region 12 by the read voltage <+ Vrd> applied from the bottom word line 10. A negative charge is induced on the channel region 12 to form a depletion layer 12b. Accordingly, the channel of the channel region 12 is turned off by the depletion layers 12a and 12b formed in the channel region 12 to block the current path from the source region 14 to the drain region 13.

At this time, even if a slight voltage difference is applied between the drain region 13 and the source region 14, a small current flows because the channel region 12 is turned off. Accordingly, data "0" stored in the memory cell can be read in the read operation mode.

Accordingly, since the voltage line is not applied to the ferroelectric layer 17 by controlling the word line 18 and the bottom word line 10 to the ground in the read operation mode, the data retention characteristics of the cell can be improved.

In particular, since nanoscale-level ferroelectric memory cells have poor data retention characteristics at low voltage stress, it is difficult to apply arbitrary voltages to word lines during read operations as in the conventional method. Accordingly, the present invention solves this conventional problem by the above-described operation, thereby making it possible to improve low voltage operating characteristics in a cell including a nanoscale ferroelectric layer.

5 is a layout cross-sectional view of a nonvolatile ferroelectric memory device according to the present invention.

In the present invention, the word line WL and the bottom word line BWL are arranged in parallel in the same direction and provided in plural in the column direction. A plurality of bit lines BL are provided in a direction perpendicular to the word line WL. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL, a plurality of bottom word lines BWL, and a plurality of bit lines BL intersect.

6A and 6B are cross-sectional views of a cell array of a nonvolatile ferroelectric memory device according to the present invention.

FIG. 6A illustrates a cell array cross-sectional structure in the direction (A) parallel to the word line WL in the layout cross-sectional view of FIG. 5.

In the cell array of the present invention, the insulating layer 11 is formed on the bottom word line 10, and the floating channel layer 15 includes a plurality of P-type channel regions 12 on the insulating layer 11. Is formed. The tunnel oxide layer 16 is formed on the floating channel layer 15, and the ferroelectric layer 17 is formed on the tunnel oxide layer 16. In addition, a word line 18 is formed on the ferroelectric layer 17 in parallel with the bottom word line 10. Thus, a plurality of cells are connected between one word line WL_1 and one bottom word line BWL_1.

6B illustrates a cell array cross-sectional structure in a direction (B) perpendicular to the word line WL in the layout cross-sectional view of FIG. 5.

In the cell array of the present invention, an insulating layer 11 having an extended length is formed on each of the bottom word lines BWL_1, BWL_2, and BWL_3. In addition, the floating channel layer 15 having the P-type drain region 13, the P-type channel region 12, and the P-type source region 14 connected in series is formed on the insulating layer 11.

Here, the P-type drain region 13 may be used as a source region in an adjacent cell, and the P-type source region 14 may be used as a drain region in an adjacent cell. That is, the P-type region is commonly used as a drain region and a source region in adjacent cells.

Further, the tunnel oxide layer 16 is formed on the floating channel layer 15, the ferroelectric layer 17 is formed on the tunnel oxide layer 16, and the P-type channel region of the ferroelectric layer 17 ( The word lines WL_1, WL_2, and WL_3 are formed on the top of 12).

7 is a cross-sectional view of a nonvolatile ferroelectric memory device having a multilayer structure.

In the present invention having the multilayer structure shown in FIG. 7, the unit cell array of the present invention having the configuration as shown in FIG. 6B is stacked in a multilayer structure. Each unit cell array is separated from each other through the insulating layer 20.

In the present invention, the floating channel layer 15 is composed of the P-type drain region 13, the P-type channel region 12 and the P-type source region 14 in the embodiment, but the present invention is not limited thereto. As shown in FIG. 8, the floating channel layer 15 may include an N-type drain region 13, an N-type channel region 12, and an N-type source region 14.

As described above, the present invention provides the following effects.

First, data of a cell is not destroyed during a read operation using a non destructive read out (NDRO) method. Accordingly, the present invention can improve the reliability of the cell during the low voltage operation of the nano-scale ferroelectric cell and improve the read operation speed.

Second, by stacking a plurality of ferroelectric unit cell array to improve the integrated capacity of the cell provides an effect to reduce the overall size of the cell.

Third, a thin tunnel oxide layer is formed between the floating channel layer and the ferroelectric layer to prevent impurities from the ferroelectric layer from being diffused into the channel region in a fair manner. Accordingly, the depolarization charges between the ferroelectric layer and the oxide layer generated during programming are all emitted through the tunnel oxide layer, thereby providing an effect of improving retention characteristics of the ferroelectric layer.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

Claims (16)

An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer to maintain a floating state, and a P channel drain region and a P type source region connected to both sides of the channel region; A tunnel oxide layer formed on the floating channel layer; A ferroelectric layer formed on the tunnel oxide layer to store data; And A word line formed in parallel with the bottom word line on the ferroelectric layer, And a read / write control of data by inducing different channel resistances in the channel region according to the polarity of the ferroelectric layer. The nonvolatile ferroelectric memory device of claim 1, wherein the floating channel layer is formed of at least one of carbon nanotubes, silicon, germanium, and an organic semiconductor. The method of claim 1, wherein the floating channel layer The channel is turned on when the polarity of the ferroelectric layer induces positive charge in the channel region, and the channel is turned on. And off. Nonvolatile ferroelectric memory device. The channel of claim 1, wherein a ground voltage or a positive voltage is applied to the bottom word line, a negative voltage is applied to the word line, and a ground voltage is applied to the drain region and the source region. A nonvolatile ferroelectric memory device, characterized in that a positive charge is induced in a region to write high data. The channel region of claim 1, wherein a ground voltage or a negative voltage is applied to the bottom word line, a positive voltage is applied to the word line, and a ground voltage is applied to the drain region and the source region. A nonvolatile ferroelectric memory device, characterized in that a negative charge is induced to write low data. The method of claim 1, wherein a positive read voltage is applied to the bottom word line, a ground voltage is applied to the word line, and low data is read while the channel of the floating channel layer is turned off. A nonvolatile ferroelectric memory device, characterized in that high data is read while a channel of a floating channel layer is turned on. The nonvolatile ferroelectric memory device of claim 1, wherein the insulating layer, the floating channel layer, the tunnel oxide layer, and the ferroelectric layer are formed to have the same length in a direction perpendicular to the word line. A plurality of bottom word lines; An insulation layer formed on the bottom word lines; A floating channel layer formed on the plurality of insulating layers and having a plurality of P-type channel regions and a plurality of P-type drain and source regions alternately connected in series with the plurality of P-type channel regions; A tunnel oxide layer formed on the floating channel layer; A ferroelectric layer formed on the tunnel oxide layer; And A unit cell array including a plurality of word lines formed in parallel with the plurality of bottom word lines, respectively, on the ferroelectric layer; And the unit cell array is configured to read / write a plurality of data by inducing different channel resistances to the plurality of P-type channel regions according to the polarity of the ferroelectric layer. The nonvolatile ferroelectric memory device of claim 8, wherein the unit cell arrays are stacked in a plurality of layers to form a multi-layer structure, and the unit cell arrays are separated from each other by a cell insulating layer. The nonvolatile ferroelectric memory device of claim 8, wherein the floating channel layer is formed of at least one of carbon nanotubes, silicon, germanium, and an organic semiconductor. The method of claim 8, wherein the floating channel layer The channel is turned on when the polarity of the ferroelectric layer induces positive charge in the channel region, and the channel is turned on. When the polarity of the ferroelectric layer induces negative charge in the channel region, the channel is turned into a high resistance state. And off. Nonvolatile ferroelectric memory device. The channel of claim 8, wherein a ground voltage or a negative voltage is applied to the bottom word line, a negative voltage is applied to the word line, and a ground voltage is applied to the drain region and the source region. A nonvolatile ferroelectric memory device, characterized in that a positive charge is induced in a region to write high data. The channel region of claim 8, wherein a ground voltage or a negative voltage is applied to the bottom word line, a positive voltage is applied to the word line, and a ground voltage is applied to the drain region and the source region. A nonvolatile ferroelectric memory device, characterized in that a negative charge is induced to write low data. 10. The method of claim 8, wherein a positive read voltage is applied to the bottom word line, a ground voltage is applied to the word line, and low data is read while the channel of the floating channel layer is turned off. A nonvolatile ferroelectric memory device, characterized in that high data is read while a channel of a floating channel layer is turned on. The nonvolatile ferroelectric memory device of claim 8, wherein the insulating layer, the floating channel layer, the tunnel oxide layer, and the ferroelectric layer are formed to have the same length in a direction perpendicular to the word line. An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer and having an N-type channel region maintaining a floating state, and an N-type drain region and an N-type source region connected to both sides of the channel region; A tunnel oxide layer formed on the floating channel layer; A ferroelectric layer formed on the tunnel oxide layer to store data; And A word line formed in parallel with the bottom word line on the ferroelectric layer, And a read / write control of data by inducing different channel resistances in the channel region according to the polarity of the ferroelectric layer.

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