JPH04298079A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce an area for obtaining large capacity and high density of components by series-connecting a plurality of memory cells composed of the in parallel connected transistors for selection and transistors for memory and providing switching elements on both sides. CONSTITUTION:The transistors for selection CTR 1 to CTR 4 are composed of four pieces of selection gate electrodes CG 1 to CG 4, n<-> high-doped regions 142 to 146, channel regions 152 to 155 and a second insulating layer 16. Then, the switching elements STR 1, STR 2 are composed of two pieces of control electrodes SG 1, SG 2, n<-> high-doped regions 141 to 147, channel regions 151, 156 and a second insulating layer 16. Accordingly, a semiconductor layer 13 having n<-> high-doped regions 141 to 147 and channel regions 151 to 156 can be jointly owned by the transistors for memory MTR 1 to 4 the transistors for selection CTR 1 to CTR 4 and the switching elements STR 1, STR 2 so that a memory area can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device comprising a selection transistor and a memory transistor.

0002

2. Description of the Related Art FIG. 14 shows a conventional semiconductor memory device. That is, a memory transistor MTR made of an n-channel MNOS element and a switching transistor STR made of a MOS element are connected in series to form a memory cell, and these memory cells are connected in a matrix to form a memory array. . Thus, the gate of the memory transistor MTR and the switching transistor ST
A gate voltage is applied to the gate line GL connected to the gate of R, and a data signal is applied to the data line connected to the source and drain of the memory cell to write/erase data into the memory transistor MTR of a predetermined memory cell. I was going.

0003

[Problems to be Solved by the Invention] However, the conventional semiconductor memory device requires one switching transistor STR connected in series to one memory transistor MTR as a memory cell, so the area is large. Therefore, it was not suitable for highly integrated, large-capacity semiconductor storage devices.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a semiconductor memory device which can be reduced in area and is suitable for large capacity and high integration.

[0005]

[Means for Solving the Problems] In order to solve the above problems, the present invention connects a plurality of memory cells in series, each consisting of a selection transistor and a memory transistor connected in parallel, and has switching elements on both sides. It is characterized by the fact that it has been provided.

[0006]

According to the above means, a selection transistor is connected in parallel with a memory transistor to form a memory cell, so that a current flows through the selection transistor in the memory cell when selected. Furthermore, when reading a memory cell, by keeping the gate of the memory transistor at ground level, if the memory transistor is in the erased state when not selected, current flows through the channel of the memory transistor, and when not selected, the memory transistor If is in the write state, no current will flow. Therefore, since a semiconductor memory element can be formed with only one pair of switching elements for a large number of memory cells, the area can be reduced.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which is a 4-bit/cell NAND type EEPROM made of MNS elements. That is, on the insulating substrate 11 made of glass or the like, there are four memory gate electrodes MG1, MG made of Al or the like.
2, MG3, MG4 are formed, and on these four memory gate electrodes MG1, MG2, MG3, MG4 and the insulating substrate 11, the Si/N ratio is larger than the stoichiometric ratio (0.75), for example. A first insulating layer 12 made of silicon nitride with a thickness of 0.85 to 1.1 is formed. The first insulating layer 12 is made of, for example, polysilicon and has a thickness of 50 mm.
A semiconductor layer 13 having a thickness of 0 to 1500 angstroms is formed. This semiconductor layer 13 has an n+ high concentration region 14.
1,142,143,144,145,146,147
and channel regions 151, 152, 153, 154, 1
55,156 are formed. A second insulating layer 16 made of, for example, SiO2 is formed on the semiconductor layer 13 and the first insulating layer 12, and on this second insulating layer 16, four selection gate electrodes CG1, CG2, CG3, CG4 and two control gate electrodes SG1 and SG2 are formed. These four selection gate electrodes CG1, CG2, CG3, CG
4, on the two control gate electrodes SG1, SG2 and the second insulating layer 16, a third insulating layer 1 made of, for example, SiO2 is formed.
7 is formed, and on this third insulating layer 17, for example, Al is formed.
A drain electrode D and a source electrode S are formed to be connected to the n+ high concentration regions 141 and 147 at both ends in correspondence with each other, respectively. The four memory gate electrodes MG
1, MG2, MG3, MG4, the four selection gate electrodes CG1, CG2, CG3, CG4, and the two control gate electrodes SG1, SG2 each have a channel region 151.
, 152, 153, 154, 155, and 156. The four memory gate electrodes MG1, MG
2, MG3, MG4, n+ High concentration region 142, 143
, 144, 145, 146, channel region 152, 15
3,154,155 and four memory transistors MTR1, MTR2, MTR3, from the first insulating layer 12.
MTR4 is configured. In this case, the insulating layer 1 is made of silicon nitride with a Si/N ratio larger than the stoichiometric ratio.
2 has a memory function that captures electrons or holes and exhibits a hysteresis characteristic in VGS-IDS characteristics. The four selection gate electrodes CG1, CG2, CG3, CG4, n+
High concentration areas 142, 143, 144, 145, 146
, the channel regions 152, 153, 154, 155 and the second insulating layer 16, the selection transistors CTR1, C
TR2, CTR3, and CTR4 are configured. The two control gate electrodes SG1, SG2, n+ High concentration region 14
1, 142, 146, 147, channel region 151, 1
56 and the second insulating layer 16, the control transistor (
Switching elements) STR1 and STR2 are configured. Therefore, the semiconductor layer 13 having n+ high concentration regions 141 to 147 and channel regions 151 to 156 includes memory transistors MTR1 to MTR4, selection transistors CTR1 to CTR4, and control transistors ST.
Since it can be shared by R1 and STR2, the memory cell area can be reduced, and the capacity and integration can be increased.

FIG. 2 is a circuit diagram of FIG. 1. That is, the drain of the control transistor STR1 is connected to the drain electrode D, and the source of the control transistor STR1 is connected to the drain of the selection transistor CTR1 and to the drain of the memory transistor MTR1. The source of the selection transistor CTR1 and the source of the memory transistor MTR1 are commonly connected to the drain of the selection transistor CTR2 and the drain of the memory transistor MTR2, and the source of the selection transistor CTR2 and the memory transistor The sources of MTR2 are commonly connected to the drain of the selection transistor CTR3 and the drain of the memory transistor MTR3. The source of the selection transistor CTR3 and the source of the memory transistor MTR3 are commonly connected to the drain of the selection transistor CTR4 and the drain of the memory transistor MTR4,
The source of the selection transistor CTR4 and the source of the memory transistor MTR4 are commonly connected to the drain of the control transistor STR2, and the source of the control transistor STR2 is connected to the source electrode S.

FIG. 3(a) is a memory gate voltage VMG-drain current Id characteristic diagram of the memory transistors MTR1, MTR2, MTR3, and MTR4 in FIGS. 1 and 2. That is, memory transistors MTR1, MTR2,
When a positive voltage VP is applied to the memory gate voltage VMG of MTR3 and MTR4, writing is performed and output characteristic A is shown, and when a negative voltage -VP is applied, erasing is performed and output characteristic B is shown. For reading, memory gate voltage VMG
By setting 0V to 0V, the memory transistor MTR
If 1 to MTR4 are in erased state A, memory transistor M
A drain current of ION or more flows through each channel of TR1 to MTR4, and the memory transistors MTR1 to MT
If R4 is in write state B, the drain current flows only below IOFF. Now, suppose that in FIGS. 1 and 2, the selection transistor CT
Considering the case where R1, CTR2, CTR3, and CTR4 are not present, in order to read the write state B or erase state A of the memory transistor MTR2, voltage V'ON is applied to the gates of the control transistors ST1 and ST2. At the same time, other memory transistors MTR1, M
It is necessary to apply voltage V'ON to the gates of TR3 and MTR4 to turn them on, and to ground the gate of memory transistor MTR2. In this case, memory transistor MTR
If the memory transistor MTR2 is in the erased state A, a drain current of more than ION flows through the channel of the memory transistor MTR2, and if the memory transistor MTR2 is in the written state B, the drain current flows less than IOFF. However, as a characteristic of one memory transistor, if it is not selected during reading, the drain current will flow more than ION in either write state B or erase state A, and if it is selected during reading, the drain current will flow in write state B. In this case, the drain current flows only below IOFF, and in erase state A, the drain current must flow above ION.As a characteristic of memory transistors, the operating margin is very narrow, and when unselected during reading, Since the voltage V'ON is applied to the gate of the memory transistor, there is a drawback that the write state B or the erase state A of the memory transistor tends to fluctuate. Furthermore, ION, IOFF
are the maximum and minimum values of the current value as one bit in the memory cell required by the system, and are the NAND logic "
This is to identify ``1'' and ``0''.

FIG. 3(b) is a selection gate voltage VCG-drain current Id characteristic diagram of the selection transistors CTR1, CTR2, CTR3, and CTR4 in FIGS. 1 and 2. That is, the selection transistors CTR1, CTR2, CTR3,
When a selection gate voltage VON is applied to CTR4, a drain current ION flows.

FIG. 3(c) shows memory transistors MTR1, MTR2, MTR3, MTR4 and selection transistors CTR1, CTR2, CTR3, CTR in FIGS. 1 and 2.
FIG. 4 is a selection gate voltage VCG (memory gate voltage VMG)-drain current Id characteristic diagram of a circuit in which four transistors are connected in parallel. In this way, memory transistors MTR1, MTR2
, MTR3, MTR4 and selection transistor CTR1,
In a circuit in which CTR2, CTR3, and CTR4 are connected in parallel, the characteristics of one memory transistor are that if it is not selected during reading, there is no need to flow a drain current of ION or more, and when it is selected during reading, it is in the write state. The drain current is passed below IOFF in B, and the erase state A
Since the drain current needs to flow more than ION, the memory transistors MTR1, MTR2, MTR3, MTR4
Operation settings are easy. In addition, since the gate of the memory transistor only needs to be grounded even if it is not selected during reading, the write state of the memory transistor B
Alternatively, the erased state A does not change.

FIG. 4 is a circuit diagram for explaining the batch erasing operation of the 4-bit memory cells in FIG. 2. In FIG. 4, two 4-bit memory cells of FIG. 2 are connected in parallel to form two bit lines BL1 and BL2. That is,
Control transistor S for each bit line BL1, BL2
Control gate electrodes SG1, SG2 of TR1, STR2 and selection transistors C of each bit line BL1, BL2
Applying VON to selection gate electrodes CG1, CG2, CG3, CG4 of TR1, CTR2, CTR3, CTR4,
A voltage VP is applied to the drain side and source side of each bit line BL1, BL2, and each bit line BL1, BL
2 memory transistors MTR1, MTR2, MTR
3.Memory gate electrodes MG1, MG2, MG of MTR4
3. By grounding MG4, each bit line BL
1, BL2 memory transistors MTR1, MTR2
, MTR3, MTR4 have their drains and sources at voltage V
P, the gate electrode becomes 0V, and the memory gate -
Erasing is performed when the drain/source voltage VMG becomes -VP.

FIG. 5 shows the first bit line B in the circuit of FIG.
FIG. 3 is a circuit diagram when writing to the memory transistor MTR4 of L1. That is, each bit line BL1,
Control gate electrodes SG1, SG2 of control transistors STR1, STR2 of BL2 and each bit line BL1,
BL2 selection transistors CTR1, CTR2, CT
VON to selection gate electrodes CG1, CG2, CG3 of R3
At the same time, a voltage VOFF is applied to the selection gate electrode CG4 of the selection transistor CTR4 of each bit line BL1, BL2, 0V is applied to the drain side of the first bit line BL1, and the source of the first bit line BL1 is applied. A voltage VP is applied to the drain side and the source side of the second bit line BL2, and each bit line BL1,
BL2 memory transistors MTR1, MTR2, M
By grounding the memory gate electrodes MG1, MG2, and MG3 of TR3 and applying a voltage VP to the memory gate electrode MG4 of the memory transistor MTR4, the memory transistor MTR of the first bit line BL1 is grounded.
4, the memory gate electrode MG4 becomes the voltage VP, the drain becomes 0V, the source becomes the voltage VP, and the memory gate-drain voltage VMG becomes VP, and writing is performed. In this case, the memory transistors MTR1, MTR2, MTR3 of the first bit line BL1 have memory gate electrodes MG1, MG2, MG3 and drain/
The source becomes 0V and the erased state is maintained. Also, the second
Memory transistor MTR1 of bit line BL2 of
, MTR2, MTR3 have their drains and sources at voltage V
P, and the memory gate electrodes MG1, MG2, MG3
becomes 0V, the memory gate-drain/source voltage VMG becomes -VP, and the erased state is maintained. Furthermore, the memory transistor M of the second bit line BL2
In TR4, the drain and source are at voltage VP, and the memory gate electrode MG4 is at voltage VP, so that the erased state is maintained.

FIG. 6 shows the first bit line B in the circuit of FIG.
FIG. 4 is a circuit diagram when the write state of the memory transistor MTR4 of L1 is maintained. That is, the control transistors STR1 and STR of each bit line BL1 and BL2
2 control gate electrodes SG1, SG2 and selection transistors CTR1, CTR for each bit line BL1, BL2
2, CTR4 selection gate electrodes CG1, CG2, CG4
VON is applied to each bit line BL1, BL.
Selection gate electrode CG of No. 2 selection transistor CTR3
A voltage VOFF is applied to each bit line BL1,
Apply voltage VP to the drain side and source side of BL2,
Memory gate electrodes MG1, MG2 of memory transistors MTR1, MTR2 of each bit line BL1, BL2
and ground the memory transistors MTR3 and MT.
By applying the voltage VP to the memory gate electrodes MG3 and MG4 of R4, the memory transistor MTR4 of the first bit line BL1 is connected to the memory gate electrode MG4.
is the voltage VP, and the drain and source are the voltage VP
The write state is maintained. In this case, the memory transistor MTR3 of the first bit line BL1 and the memory transistor MT of the second bit line BL2
In R3 and MTR4, the memory gate electrodes MG3 and MG4 and the drain/source are at the voltage VP, and the erased state is maintained. In addition, the drain and source of the memory transistors MTR1 and MTR2 of each bit line BL1 and BL2 are at voltage VP, and the memory gate electrodes MG1 and M
G2 becomes 0V, the memory gate-drain/source voltage VMG becomes -VP, and the erased state is maintained.

FIG. 7 shows the first bit line B in the circuit of FIG.
FIG. 4 is a circuit diagram when the write state of the memory transistor MTR4 of L1 is maintained. That is, the voltage VOFF is applied to the control gate electrode SG1 of the control transistor STR1 of each bit line BL1, BL2, and the control transistor STR of each bit line BL1, BL2 is applied.
2 control gate electrode SG2 and each bit line BL1,
BL2 selection transistors CTR1, CTR2, CT
Selection gate electrodes CG1, CG2, CG of R3, CTR4
3. Apply VON to CG4, and each bit line BL1,
A voltage VP is applied to the drain side and source side of BL2, and a voltage VP is applied to the memory gate electrodes MG1, MG2, MG3, MG4 of the memory transistors MTR1, MTR2, MTR3, MTR4 of each bit line BL1, BL2.
By applying , the memory transistor MTR4 of the first bit line BL1 connects to the memory gate electrode
4 is the voltage VP, and the drain and source are the voltage VP.
The write state is maintained. In this case, the drain and source of the memory transistor MTR4 of the second bit line BL2 and the memory transistors MTR1, MTR2, MTR3 of each bit line BL1, BL2 are at voltage VP, and the memory gate electrodes MG1, MG
2, MG3 becomes voltage VP and the erased state is maintained. Note that a voltage VOFF is applied to the control gate electrode SG1 of the control transistor STR1 of each bit line BL1, BL2.
By applying , each bit line BL1, BL2
Even if 0V is applied to the drain side of the device, there is no effect on the operation.

FIG. 8 shows the first bit line B in the circuit of FIG.
The channel state of the semiconductor layer 13 constituting L1 is shown. That is, the control gate electrodes SG1, SG2 of the control transistors STR1, STR2 and the selection transistor CT
Apply VON to selection gate electrodes CG1, CG2, CG3, CG4 of R1, CTR2, CTR3, CTR4, apply voltage VP to drain electrode D and source electrode S,
Memory transistors MTR1, MTR2, MTR3,
Memory gate electrodes MG1, MG2, MG3 of MTR4,
By grounding MG4, control gate electrodes SG1,
SG2 and selection gate electrodes CG1, CG2, CG3, C
A channel CH is provided in the semiconductor layer 13 corresponding to each G4.
Can be done. Also, memory transistors MTR1, MTR
2. Since MTR3 and MTR4 are in the erased state, a channel CH is formed in the semiconductor layer 13 corresponding to the memory gate electrodes MG1, MG2, MG3, and MG4, respectively.

FIG. 9 shows the first bit line B in the circuit of FIG.
The channel state of the semiconductor layer 13 constituting L1 is shown. That is, the control gate electrodes SG1, SG2 of the control transistors STR1, STR2 and the selection transistor CT
Selection gate electrodes CG1, C of R1, CTR2, CTR3
At the same time, VON is applied to G2 and CG3, voltage VOFF is applied to the selection gate electrode CG4 of the selection transistor CTR4, 0V is applied to the drain electrode D, and the source electrode S
A voltage VP is applied to the memory transistor MTR1.
, MTR2, MTR3 memory gate electrodes MG1, MG
2. Ground MG3 and connect memory transistor MT
By applying the voltage VP to the memory gate electrode MG4 of R4, a channel is not formed in the semiconductor layer 13 corresponding to the selection gate electrode CG4, and since the memory transistor MTR4 is in the write state, the semiconductor layer corresponding to the memory gate electrode MG4 is formed. No channels are formed in layer 13. Further, channels CH are formed in the semiconductor layer 13 corresponding to the control gate electrodes SG1, SG2 and the selection gate electrodes CG1, CG2, CG3, respectively. Since the memory transistors MTR1, MTR2, and MTR3 are maintained in an erased state, a channel CH is formed in the semiconductor layer 13 corresponding to the memory gate electrodes MG1, MG2, and MG3, respectively.

FIG. 10 shows the channel state of the semiconductor layer 13 constituting the first bit line BL1 in the circuit of FIG. That is, the control gate electrodes SG1, SG2 of the control transistors STR1, STR2 and the selection transistor C
Selection gate electrode CG1 of TR1, CTR2, CTR4,
While applying VON to CG2 and CG4, a voltage VOFF is applied to the selection gate electrode CG3 of the selection transistor CTR3.
is applied, and a voltage V is applied to the drain electrode D and source electrode S.
P is applied, and the memory transistors MTR1 and MTR
By grounding the memory gate electrodes MG1 and MG2 of the memory transistors MTR3 and MTR4 and applying the voltage VP to the memory gate electrodes MG3 and MG4 of the memory transistors MTR3 and MTR4, a channel is not formed in the semiconductor layer 13 corresponding to the selection gate electrode CG3. , memory transistor MT
Since R4 maintains the write state, the memory gate electrode MG
No channel is formed in the semiconductor layer 13 corresponding to No. 4. Moreover, the control gate electrodes SG1, SG2 and the selection gate electrode C
Semiconductor layer 13 corresponding to G1, CG2, and CG4, respectively
A channel CH is created. Memory transistor MT
Since R1, MTR2, and MTR3 are maintained in the erased state, a channel CH is formed in the semiconductor layer 13 corresponding to the memory gate electrodes MG1, MG2, and MG3, respectively.

FIG. 11 shows the channel state of the semiconductor layer 13 constituting the first bit line BL1 in the circuit of FIG. That is, the voltage VOFF is applied to the control gate electrode SG1 of the control transistor STR1, and the voltage VOFF is applied to the control gate electrode SG2 of the control transistor STR2 and the selection gate electrodes CG1, CG2, CG3, CG4 of the selection transistors CTR1, CTR2, CTR3, CTR4. V.O.
N is applied, and a voltage V is applied to the drain electrode D and source electrode S.
P is applied, and the memory transistors MTR1 and MTR
2.Memory gate electrodes MG1, MTR3 and MTR4
By applying voltage VP to G2, MG3, and MG4, a channel is not formed in the semiconductor layer 13 corresponding to the control gate electrode SG1, and the memory transistor MT
Since R4 maintains the write state, the memory gate electrode MG
No channel is formed in the semiconductor layer 13 corresponding to No. 4. Moreover, the control gate electrode SG2 and the selection gate electrodes CG1, C
Semiconductor layer 13 corresponding to G2, CG3, and CG4, respectively
A channel CH is created. Memory transistor MT
Since R1, MTR2, and MTR3 are maintained in the erased state, a channel CH is formed in the semiconductor layer 13 corresponding to the memory gate electrodes MG1, MG2, and MG3, respectively.

FIG. 12 shows the channel state of the semiconductor layer 13 constituting the first bit line BL1 when reading from the circuit state of FIG. 7. That is, the control transistor ST
VON is applied to the control gate electrodes SG1, SG2 of R1, STR2 and the selection gate electrodes CG1, CG2, CG4 of the selection transistors CTR1, CTR2, CTR4, and the selection gate electrode C of the selection transistor CTR3.
By applying voltage VOFF to G3, grounding memory gate electrodes MG1, MG2, MG3, MG4 of memory transistors ST1, ST2, MTR3, MTR4, applying Vd to drain electrode D, and grounding source electrode S. , semiconductor layer 13 corresponding to selection gate electrode CG3
Since a channel is not formed in the memory transistor MTR4 and the memory transistor MTR4 is in the write state, the memory gate electrode MG
No channel is formed in the semiconductor layer 13 corresponding to No. 4. Moreover, the control gate electrodes SG1, SG2 and the selection gate electrode C
Semiconductor layer 13 corresponding to G1, CG2, and CG4, respectively
A channel CH is created. Memory transistor MT
Since R1, MTR2, and MTR3 are in the erased state, a channel CH is formed in the semiconductor layer 13 corresponding to the memory gate electrodes MG1, MG2, and MG3, respectively. In this way, at the time of reading, only the selection transistor of the read bit is turned off and the other selection transistors are turned on, so that NAND logic is satisfied.

FIG. 13 shows another embodiment of the present invention, in which a 4-bit/cell NAND type EEPROM made of MNS elements is formed using a single crystal semiconductor device and a TFT. That is, the single crystal silicon substrate 21 has an n+ high concentration region 22.
1,222,223,224,225,226,227
For example, Si
Control gate electrode SG1 via an insulating layer INS such as O2
, SG2 are formed. Said + high concentration regions 222 and 2
For example, between 23, 223 and 224, 224 and 225, and 225 and 226,
Select gate electrode CG via insulating layer INS such as iO2
1, CG2, CG3, and CG4 are formed, and a semiconductor layer 23 made of, for example, polysilicon is formed on the selection gate electrodes CG1, CG2, CG3, and CG4 via an insulating layer INS made of, for example, SiO2. This semiconductor layer 23 includes n+ high concentration regions 241, 242, 243, 244,
245 and channel regions 251, 252, 253, 25
4 is formed. This n+ high concentration region 241, 242
, 243, 244, 245 are the n+ high concentration regions 22
2, 223, 224, 225, and 226. The channel regions 251, 252, 253, 25
On top of 4, memory gate electrodes MG1 and MG are formed via an insulating layer INS made of silicon nitride or the like having a charge trapping function.
2, MG3, and MG4 are formed. A drain electrode D and a source electrode S made of, for example, Al are connected to the n+ high concentration regions 221 and 227, respectively, and are made of, for example, Si.
It is formed via an insulating layer INS of O2 or the like. Said single crystal silicon substrate 21, n+ high concentration regions 221, 222
, 226, 227, control transistors STR1, ST from the insulating layer INS and control gate electrodes SG1, SG2
R2 is configured. The single crystal silicon substrate 21, n+ high concentration region 222
, 223, 224, 225, 226, the insulating layer INS, and the selection transistors CTR1, CTR2, CTR3, C from the selection gate electrodes CG1, CG2, CG3, CG4.
TR4 is configured. The semiconductor layer 23, an insulating layer INS such as silicon nitride, and a memory gate electrode MG1
, MG2, MG3, MG4 from memory transistor M
TR1, MTR2, MTR3, and MTR4 are configured.

[0023] In this way, by combining a single crystal semiconductor device and a TFT, single crystal semiconductor technology can be used. In addition, in FIG. 13, the control transistor STR
1, STR2 and selection transistors CTR1, CTR
2, CTR3 and CTR4 are configured with single crystal semiconductor devices,
Memory transistors MTR1, MTR2, MTR3,
Although MTR4 is configured with a TFT, the memory transistors MTR1, MTR2, and MTR are not limited to this.
3.MTR4 is composed of a single crystal semiconductor device, and control transistors STR1, STR2 and selection transistor C
TR1, CTR2, CTR3, and CTR4 may be constructed of TFTs. Also, memory transistor M
TR was explained in the case of MNS FET, but in MNOS
FET, MONOS FET, etc. are also applicable. The semiconductor layer may be made of amorphous silicon, and the number of bits in one cell is not limited to 4 bits, but may also be 8 bits or 16 bits.

[0024]

As described above, according to the present invention, a plurality of memory cells each formed by connecting a selection transistor and a memory transistor in parallel are connected in series, and switching elements are provided on both sides to create a semiconductor memory. By configuring the device, the area can be reduced and it is suitable for increasing capacity and increasing integration. Furthermore, since the memory cell when selected causes current to flow through the selection transistor, the operating margin of the memory is wide and the characteristics can be easily designed. Furthermore, since the memory gate of the memory transistor only needs to be grounded during reading, the data retention characteristics of the memory transistor are improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of FIG. 1;

FIG. 3 is a characteristic diagram showing an example of gate voltage-drain current characteristics of a selection transistor and a memory transistor according to the present invention.

FIG. 4 is a circuit diagram for explaining a batch erase operation of the semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram for explaining a first write operation of the semiconductor memory device of the present invention.

FIG. 6 is a circuit diagram for explaining a second write operation of the semiconductor memory device of the present invention.

FIG. 7 is a circuit diagram for explaining a third write operation of the semiconductor memory device of the present invention.

8 is a cross-sectional explanatory diagram showing a channel state of a semiconductor layer in the operation of FIG. 4; FIG.

9 is an explanatory cross-sectional diagram showing the channel state of the semiconductor layer in the operation of FIG. 5; FIG.

FIG. 10 is an explanatory cross-sectional view showing the channel state of the semiconductor layer in the operation of FIG. 6;

11 is an explanatory cross-sectional view showing the channel state of the semiconductor layer in the operation of FIG. 7; FIG.

FIG. 12 is an explanatory cross-sectional view showing the channel state of a semiconductor layer in a read operation of the semiconductor memory device of the present invention.

FIG. 13 is a sectional view showing another embodiment of the present invention.

FIG. 14 is a circuit diagram for explaining a conventional semiconductor memory device.

[Explanation of symbols]

11... Insulating substrate, 12... First insulating layer, 13... Semiconductor layer, 141, 142, 143, 144, 145, 146,
147...n+ High concentration region, 151, 152, 153,
154, 155, 156...channel region, 16...second insulating layer, 17...third insulating layer, MG1, MG2, MG3
, MG4...Memory gate electrode, CG1, CG2, CG3
, CG4... selection gate electrode, SG1, SG2... control gate electrode, MTR1, MTR2, MTR3, MTR4... memory transistor, CTR1, CTR2, CTR3,
CTR4...selection transistor, STR1, STR2...
Control transistor.

Claims (5)

[Claims] 1. A semiconductor memory device characterized in that a plurality of memory cells each having a selection transistor and a memory transistor connected in parallel are connected in series, and switching elements are provided on both sides. 2. The semiconductor memory device according to claim 1, wherein one of the selection transistor and the memory transistor is formed of a single crystal semiconductor layer. 3. The semiconductor memory device according to claim 1, wherein the memory transistor is a memory transistor made of an electrically erasable nonvolatile semiconductor. 4. The semiconductor memory device according to claim 1, wherein the selection transistor and the memory transistor are formed of a polysilicon semiconductor layer. 5. The polysilicon semiconductor layer is disposed between the selection transistor and the memory transistor, and shares the source region and drain region of the selection transistor and the memory transistor. 5. The semiconductor memory device according to claim 4.