CN109244236B - Memory structure - Google Patents
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- CN109244236B CN109244236B CN201810866884.7A CN201810866884A CN109244236B CN 109244236 B CN109244236 B CN 109244236B CN 201810866884 A CN201810866884 A CN 201810866884A CN 109244236 B CN109244236 B CN 109244236B
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- 230000015654 memory Effects 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052755 nonmetal Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 238000003860 storage Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000012782 phase change material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 230000008901 benefit Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052946 acanthite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- OMZSGWSJDCOLKM-UHFFFAOYSA-N copper(II) sulfide Chemical compound [S-2].[Cu+2] OMZSGWSJDCOLKM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- XUARKZBEFFVFRG-UHFFFAOYSA-N silver sulfide Chemical compound [S-2].[Ag+].[Ag+] XUARKZBEFFVFRG-UHFFFAOYSA-N 0.000 description 1
- 229940056910 silver sulfide Drugs 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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Abstract
The invention discloses a memory structure, and belongs to the technical field of semiconductors. The memory structure includes: a substrate; word lines parallel to the substrate; a column inserted in the word line and perpendicular to the substrate; the first transistors are positioned at one end of the columns and correspond to the columns one to one or are shared by a plurality of columns; and the second transistors are positioned at the other ends of the columns and correspond to the columns one to one. According to the memory structure, the first transistors which are in one-to-one correspondence with the cylinders or can be shared by the cylinders are distributed at one end of the cylinder, on the premise that the performance of the memory structure is guaranteed, the current required by the memory structure during initialization and data writing is improved, the high-density requirement of the memory is met, the data writing is easier, the error rate is reduced, and the data writing speed is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory structure.
Background
Non-volatile memories, typically flash memories, are widely used in various products, such as mobile phones, notebooks, solid state drives, and other storage and communication devices, because of their data retention capability in case of power failure and their advantage of being able to write and erase data many times. Nowadays, flash memory has occupied most market share of nonvolatile semiconductor memory, however, with the increasing demand of people for large capacity, low cost, low power consumption, high performance, and the like in the information society and the rapid development of semiconductor technology, the existing flash memory technology has been difficult to meet the development demand of nonvolatile memory technology due to the factors of poor specific energy of its preparation technology, higher operating voltage, larger power consumption, and the like. In order to solve this problem, a new generation of nonvolatile Memory concept, resistive Random Access Memory (RRAM), is created. The resistive random access memory is completely based on a brand-new storage concept and completely different from the traditional flash memory concept based on threshold voltage change, and the resistive random access memory realizes storage of two states of '0' and '1' by using change of resistance. Compared with the traditional flash memory, the resistive random access memory has the advantages of simple structure, low power consumption, high speed, high storage density, simple manufacturing process and the like, so that the resistive random access memory becomes the most potential device of the next-generation nonvolatile memory.
However, in the current resistive random access memory, the current provided by the MOS transistor is limited, and the memory needs a larger current when writing data, including the current of the target memory cell and the leakage current of the adjacent memory cell, so that the current resistive random access memory limits the number of data written in the memory in parallel, i.e. the data writing speed; furthermore, the current provided by the MOS transistor is also used for initialization (initialization) of the memory cell, and the current provided by the MOS transistor is limited, thereby limiting the density of the memory cell.
Disclosure of Invention
The purpose of the invention is realized by the following technical scheme.
The invention provides a memory structure, comprising: a substrate; word lines parallel to the substrate; a pillar inserted in the word line and perpendicular to the substrate; the first transistors are positioned at one end of the columns, correspond to the columns one by one or are shared by a plurality of columns; and the second transistors are positioned at the other ends of the columns and correspond to the columns one to one.
Optionally, the column includes from outside to inside: an upper electrode, a resistance change layer and a lower electrode; or an upper electrode, a resistance change layer, a selection layer and a lower electrode; or an upper electrode, a selection layer, a resistance change layer, and a lower electrode.
Optionally, the resistance change layer is made of metal oxide, or is made of nonmetal oxide, or is made of a compound of metal and nonmetal, or is made of a phase change material.
Optionally, the columns are arranged in a matrix or honeycomb arrangement;
optionally, a plurality of pillars in each row, or a plurality of pillars in a plurality of rows, share one of the first transistors; alternatively, a plurality of pillars in each column, or a plurality of pillars in a plurality of columns, share one of the first transistors.
Optionally, the first transistor has a planar structure or a three-dimensional structure, and the second transistor has a planar structure or a three-dimensional structure.
Optionally, the size of the second transistor is smaller than the size of the shared first transistor.
Optionally, the memory structure is: resistive random access memory or phase change memory.
Optionally, the pillars are inserted into the word lines to form memory cells.
Optionally, the word line is one layer or multiple layers.
Optionally, when the word lines are multi-layered, data is written in the memory cells of one layer, or data is written in the memory cells of at least two layers at the same time.
The invention has the advantages that:
in the invention, one end of the column body is provided with the large-size first transistor shared by a plurality of column bodies, so that compared with the existing resistive random access memory structure, on one hand, the shared first transistor can greatly improve the current required by the memory structure during initialization, and the high-density requirement of the memory is met; on the other hand, the shared first transistor can greatly improve the current required by the memory structure when data is written, so that the energy of a write pulse is larger, the data is easier to write, the error rate is reduced, data can be written into a plurality of layers of memory cells simultaneously, and the data writing speed is improved; finally, the memory structure greatly ensures the safety and the performance of the memory structure while fully utilizing the electric energy.
Drawings
Various additional advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a memory structure according to an embodiment of the present invention;
FIG. 2 is a schematic top view of a column according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a sharing scheme of a first transistor according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a sharing scheme of a second first transistor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a sharing scheme of a third first transistor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a fourth exemplary sharing scheme of a first transistor according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a fifth sharing scheme of a first transistor according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a sharing scheme of a sixth first transistor according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating a sharing scheme of a seventh first transistor according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating an eighth sharing scheme for a first transistor according to an embodiment of the present invention;
FIG. 11 is a diagram illustrating the internal connections of a memory structure according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
According to an embodiment of the present invention, a memory structure is provided, as shown in fig. 1, including: a substrate; word lines parallel to the substrate; a Pillar (Pillar) inserted in the word line and vertical to the substrate; the first transistors are positioned at one end of the columns and correspond to the columns one to one or are shared by a plurality of columns; and the second transistors are positioned at the other ends of the columns and correspond to the columns one to one.
The source electrode of the second transistor is connected with a bit line, the drain electrode of the second transistor is connected with the top end of the column, the connection relation of the source electrode and the drain electrode can be interchanged, and the grid electrode of the second transistor is used for independent control or common control, preferably common control; the source electrode of the first transistor is connected with a source line, the drain electrode of the first transistor is connected with the bottom end of the column, the connection relation of the source electrode and the drain electrode can be interchanged, and the grid electrode of the first transistor is used for independent control or common control, preferably common control;
the first transistor in the invention can greatly improve the current required by the memory structure during initialization (initialization) and data writing, and on one hand, the high-density requirement of the memory structure is met; on the other hand, the energy of the writing pulse of the memory structure is larger, so that the data writing is easier, and the error rate is reduced; and the quantity of the data written simultaneously is increased, and the writing speed of the data is improved.
It should be noted that fig. 1 is only used for illustration and not for limitation, the positions of the first transistor and the second transistor can be interchanged, and the sharing manner of the first transistor and the number of pillars sharing the first transistor can be set according to the requirement.
According to an embodiment of the present invention, the substrate is preferably a silicon substrate.
According to the embodiment of the invention, the word line is one layer or a plurality of layers, and the pillar is inserted into the word line to form a memory unit; when the word lines are in multiple layers, the multiple layers of memory cells are stacked to form a memory cell array.
Furthermore, the pillars are inserted into the word lines to form a memory cell or two memory cells;
specifically, when the diameter of the pillar is smaller than that of the word line and the pillar is inserted into one word line, a memory cell is formed; when the diameter of the column is larger than the distance between two adjacent word lines, smaller than the sum of the distance between the two word lines and the width of the two word lines, and the column is inserted between the two adjacent word lines, two memory units are formed; when the diameter of the pillar is smaller than the distance between two adjacent word lines, and the pillar is inserted between the two adjacent word lines and connected with the two adjacent word lines, two memory units are formed.
It should be noted that the pillars are inserted into the word lines to form the memory cells, which are not limited to the above situation, and can be set according to the requirement.
Further, when the word line has a plurality of layers, data is written in one layer of memory cells, or data is written in at least two layers of memory cells simultaneously.
In the invention, the first transistor can provide large current, so that data can be written in the multilayer memory unit simultaneously, the data writing speed is greatly improved, and the error rate is reduced.
According to the embodiment of the invention, the memory structure can be a resistive random access memory and also can be a phase change memory; correspondingly, as shown in fig. 2, the column comprises from the outside to the inside: an upper electrode, a resistance change layer and a lower electrode; or an upper electrode, a resistance change layer, a selection layer and a lower electrode; or an upper electrode, a selection layer, a resistance change layer, and a lower electrode.
Wherein, the resistance changing layer is made of metal oxide, such as hafnium oxide, aluminum oxide, etc.; alternatively, the resistance change layer is composed of a non-metal oxide such as silicon dioxide or the like; or the resistance change layer is made of metal and nonmetal compounds, such as silver sulfide, copper sulfide, etc.; alternatively, the resistive layer is formed of a phase change material, such as Ge 2 Sb 2 Te 5 Etc.; which can be set by the user according to the requirements.
Furthermore, the metal oxide may contain only one metal element or may contain a plurality of metal elements; the non-metal oxide may contain only one non-metal element or may contain a plurality of non-metal elements.
Further, in the present invention, the upper electrode is connected to a word line; wherein, the upper electrode and the word line can be made of the same material or different materials
According to an embodiment of the present invention, the columns are arranged in a matrix or in a honeycomb arrangement;
specifically, as shown in the top views of fig. 3 to 6, a plurality of pillars in each row or a plurality of pillars in a plurality of rows share one first transistor; or as shown in the top views of fig. 7 to 10, a plurality of pillars in each column, or a plurality of pillars in a plurality of columns, share one first transistor; the column body of each row is specifically a column body connected by the same word line and different bit lines; each column of pillars is connected by the same bit line and different word lines; the pillars within the dashed box are the pillars sharing a first transistor.
More specifically, when the memory cell is initialized or data is written, and a plurality of pillars in each row or a plurality of pillars in a plurality of rows share one first transistor, the shared first transistor and the second transistor are simultaneously provided with current, or only the shared first transistor is provided with current, or only the second transistor is provided with current; when the memory cell is initialized or data is written, and a plurality of columns in each column or a plurality of columns in a plurality of columns share one first transistor, the shared first transistor and the second transistor are simultaneously provided with current, or only the shared first transistor is provided with current, or only the second transistor is provided with current.
It should be noted that the number of rows and columns of the pillar arrangement and the number of pillars sharing the first transistor can be set according to the requirement, and the drawings are only used for illustration.
Furthermore, when the pillars correspond to one first transistor one by one, when data is written in or the memory unit is initialized, the first transistor and the second transistor provide current at the same time, or only the first transistor provides current, so that the initialization of the memory or the writing of the data can be smoothly completed.
According to the embodiment of the invention, the first transistor may have a planar structure or a three-dimensional structure, and the second transistor may have a planar structure or a three-dimensional structure; and the size of the second transistor is smaller than the size of the shared first transistor.
Furthermore, the positions of the first transistor and the second transistor can be set according to requirements; for example, a first transistor is located in the substrate, the first transistor is connected to the bottom end of the corresponding pillar, and a second transistor is located at the top end of the pillar and connected to the top end of the corresponding pillar, as shown in fig. 11;
note that fig. 11 shows only a part of the structure of the memory, the substrate and the like are not shown, and the pillars are inserted into the word lines to form two memory cells, and the pillars in each column share one transistor.
Further, in the present invention, the inhibit voltage of the unselected memory cell may be half of the write voltage at the time of writing data, that is, the write voltage
E.g. V Writing in When =3V, V Suppression of =1.5V; the inhibit voltage may also be 1/3 and 2/3 of the write voltage, i.e.
And
e.g. V Writing in ＝3V，V Inhibition 1 =1V and V Inhibition 2 =2V. The two conditions can make the voltage applied to the upper and lower electrodes of the unselected memory cells equal to or less than half of the write voltage, and ensure that the data stored in the unselected memory cells are not interfered.
In the invention, the first transistors which are in one-to-one correspondence with the cylinders or the first transistors with large size which can be shared by a plurality of cylinders are arranged at one end of the cylinder, so that compared with the existing resistive random access memory structure, on one hand, the shared first transistors can greatly improve the current required by the memory structure during initialization, and the high-density requirement of the memory is met; on the other hand, the shared first transistor can greatly improve the current required by the memory structure when writing data, so that the energy of a write pulse is larger, the data is easier to write, the error rate is reduced, data can be written into a plurality of layers of memory cells simultaneously, and the data writing speed is improved; and finally, the safety and the performance of the memory structure are greatly guaranteed while the electric energy is fully utilized.
While the invention has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. A memory structure, comprising: a substrate; word lines parallel to the substrate; the cylinder is inserted in the word line and is vertical to the substrate; a first transistor located at one end of the pillar for sharing by the plurality of pillars; the second transistors are positioned at the other ends of the columns and correspond to the columns one to one;
the columns are arranged in a honeycomb shape; a plurality of pillars in each row, or a plurality of pillars in a plurality of rows, share one of the first transistors; or, a plurality of pillars in each column, or a plurality of pillars in a plurality of columns, share one of the first transistors; the columns of each row are connected by the same word line and different bit lines; the columns of each column are connected by the same bit line and different word lines;
the pillars are inserted into the word lines to form storage units; when the diameter of the column is smaller than that of the word line and the column is inserted into one word line, a memory unit is formed; when the diameter of the column is larger than the distance between two adjacent word lines, smaller than the sum of the distance between the two word lines and the width of the two word lines, and the column is inserted between the two adjacent word lines, two memory units are formed; when the diameter of the column body is smaller than the distance between two adjacent word lines, and the column body is inserted between the two adjacent word lines and connected with the two adjacent word lines, two storage units are formed;
the size of the second transistor is smaller than that of the shared first transistor; the source electrode of the second transistor is connected with a bit line, the drain electrode of the second transistor is connected with the top end of the column, or the source electrode of the second transistor is connected with the top end of the column, the drain electrode of the second transistor is connected with the bit line, and the grid electrode of the second transistor is used for independent control or common control; the source electrode of the first transistor is connected with a source line, the drain electrode of the first transistor is connected with the bottom end of the column, or the source electrode of the first transistor is connected with the bottom end of the column, the drain electrode of the first transistor is connected with the source line, and the grid electrode of the first transistor is used for independent control or common control.
2. The memory structure of claim 1, wherein the pillars comprise, from the outside inward: an upper electrode, a resistance change layer and a lower electrode; or an upper electrode, a resistance change layer, a selection layer and a lower electrode; or an upper electrode, a selection layer, a resistance change layer, and a lower electrode.
3. The memory structure of claim 2, wherein the resistive layer is comprised of a metal oxide, or a non-metal oxide, or a compound of a metal and a non-metal, or a phase change material.
4. The memory structure of claim 1, wherein the first transistor is in a planar or a three-dimensional configuration and the second transistor is in a planar or a three-dimensional configuration.
5. The memory structure of claim 1, wherein the memory structure is: resistive random access memory or phase change memory.
6. The memory structure of claim 1, wherein the word lines are one or more layers.
7. The memory structure according to claim 6, wherein when the word line has a plurality of layers, data is written in the memory cells of one layer, or data is written in the memory cells of at least two layers at the same time.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544049A (en) * | 2010-12-22 | 2012-07-04 | 中国科学院微电子研究所 | Three-dimensional semiconductor memory device and preparation method thereof |
| CN103390629A (en) * | 2013-07-15 | 2013-11-13 | 北京大学 | RRAM (resistive random access memory) and operation and manufacturing method thereof |
| US20160233224A1 (en) * | 2015-02-05 | 2016-08-11 | Conversant Intellectual Property Management Inc. | Access Transistor of a Nonvolatile Memory Device and Method for Fabricating Same |
| CN106409768A (en) * | 2016-04-19 | 2017-02-15 | 清华大学 | NAND memory structure, NAND memory structure formation method and three dimensional memory array |
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2018
- 2018-08-01 CN CN201810866884.7A patent/CN109244236B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544049A (en) * | 2010-12-22 | 2012-07-04 | 中国科学院微电子研究所 | Three-dimensional semiconductor memory device and preparation method thereof |
| CN103390629A (en) * | 2013-07-15 | 2013-11-13 | 北京大学 | RRAM (resistive random access memory) and operation and manufacturing method thereof |
| US20160233224A1 (en) * | 2015-02-05 | 2016-08-11 | Conversant Intellectual Property Management Inc. | Access Transistor of a Nonvolatile Memory Device and Method for Fabricating Same |
| CN106409768A (en) * | 2016-04-19 | 2017-02-15 | 清华大学 | NAND memory structure, NAND memory structure formation method and three dimensional memory array |
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