CN103390629A - RRAM (resistive random access memory) and operation and manufacturing method thereof - Google Patents
RRAM (resistive random access memory) and operation and manufacturing method thereof Download PDFInfo
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- CN103390629A CN103390629A CN2013103023710A CN201310302371A CN103390629A CN 103390629 A CN103390629 A CN 103390629A CN 2013103023710 A CN2013103023710 A CN 2013103023710A CN 201310302371 A CN201310302371 A CN 201310302371A CN 103390629 A CN103390629 A CN 103390629A
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Abstract
The invention provides an RRAM. The RRAM comprises a memory array. The memory array comprises a substrate, a substrate isolation layer arranged on the substrate, a plurality of laminated structures arranged on the substrate isolation layer, a plurality of comb-shaped metal layers and a plurality of resistive material layers, wherein the plurality of comb-shaped metal layers are arranged on the substrate isolation layer and the plurality of laminated structures in the length direction of the laminated structures, and the comb teeth of every comb-shaped metal layer are clamped between the neighboring laminated structures; every resistive material layer is formed between one corresponding comb-shaped metal layer and the substrate isolation layer and between one corresponding metal layer and the plurality of laminated structures. The invention further provides an operation and manufacturing method of the RRAM.
Description
Technical field
The disclosure relates to memory device, relates more specifically to resistance-variable storing device and method of operation thereof and manufacture method.
Background technology
At present, the development of microelectronics industry is promoting the continuous progress of memory technology, and improving integration density and reducing production costs is the target that the memory industry is pursued.Non-volatility memorizer has advantages of in the non-transformer confession at once still can keep data message, at area information storage, has very important status.
Adopt the novel non-volatility memorizer of resistive material to have at a high speed (＜1ns), low operating voltage (＜1.5V), high storage density, be easy to the advantages such as integrated, be the strong competitor of semiconductor memory of future generation.This resistance-variable storing device generally has M-I-M (Metal-Insulator-Metal, metal-insulator-metal type) structure, namely accompanies the resistive material layer between two metal electrodes.The resistive material can show two stable states, i.e. high-impedance state and low resistance state.Be commonly referred to programming or set (SET) operation by high-impedance state to the transformation of low resistance state, by low resistance state, to the transformation of high-impedance state, be commonly referred to and wipe or reset (RESET) operates.
Resistance-variable storing device comprises a plurality of resistance-change memory cellular arraies of arranging by row and column., according to the basic configuration of memory cell, resistance-variable storing device can be divided into two kinds of 1T-1R or 1D-1R.In the resistance-variable storing device of 1T-1R configuration, each memory cell is comprised of a gate transistor and a resistive element., by controlling the gate transistor of selected memory cell, can write to the memory cell of appointment or from its obliterated data.In the resistance-variable storing device of 1D-1R configuration, each memory cell is comprised of a diode and a resistive element.The chip area (footprint) that takies due to diode is less than transistorized chip area, and therefore, the resistance-variable storing device of 1D-1R configuration can be realized high storage density.In the resistance-variable storing device of 1D-1R configuration, diode is used for preventing the cross talk effects of bypass.Every delegation at resistance-variable storing device connects respectively gate transistor with being connected to list., by controlling the gate transistor of selected row and column, can write to the memory cell of appointment or obliterated data.Diode should be designed to the drive current that provides enough to guarantee the transformation of Resistance states.
, in order further to improve storage density, can adopt three-dimensional integrated resistance-variable storing device., by the resistance-change memory device of vertical stacking multilayer on substrate, storage density can be improved exponentially and not remarkable chip area and the increase manufacturing cost of increasing.Yet the resistance-variable storing device of employing 1T-1R configuration or 1D-1R configuration is because the existence of transistor or diode is difficult to three-dimensional integrated.Usually, the operating current of diode is directly proportional to its chip area.After the size of diode was dwindled, diode may be difficult to the drive current that provides enough large.
Summary of the invention
The disclosure provides resistance-variable storing device and method of operation and manufacture method.
Provide a kind of resistance-variable storing device according to an aspect of the present disclosure, comprised storage array, described storage array comprises: substrate; The substrate isolation layer, be arranged on substrate; A plurality of laminated construction, be arranged on the substrate isolation layer; A plurality of pectination metal levels, be arranged on substrate isolation layer and described a plurality of laminated construction along the length direction of described laminated construction, and the broach of each pectination metal level is clipped between adjacent laminated construction; And a plurality of resistive material layers, each resistive material layer is formed between a corresponding pectination metal level and described substrate isolation layer and between a corresponding pectination metal level and described a plurality of laminated construction.
Provide a kind of method that operates resistance-variable storing device as above according to another aspect of the present disclosure, wherein, described resistance-variable storing device comprises a plurality of memory cell, each memory cell comprise a metal level in laminated construction, a corresponding pectination metal level and both between the resistive material layer, described method comprises: apply erasing voltage, write voltage or read voltage by the memory cell to selected, realize respectively wiping, write or read operation.
Provide a kind of method of making resistance-variable storing device according to another aspect of the present disclosure, having comprised: formed the substrate isolation layer on substrate; Alternately form a plurality of metal levels and a plurality of separator on the substrate isolation layer; Use the substrate isolation layer as stop-layer, the described a plurality of metal levels of etching and a plurality of separator, a plurality of laminated construction that are arranged in parallel with formation; Deposit resistive material on described a plurality of laminated construction and substrate isolation layer; Form another metal level on the resistive material layer; Use substrate isolation layer and described a plurality of laminated construction as stop-layer, and described another metal level of etching and described resistive material, to form a plurality of pectination metal levels and corresponding a plurality of resistive material layer.
The three-dimensional high-density of having realized memory cell array according to the disclosure is integrated, has significantly improved integration density.The problem that the circuit capacity deficiency is provided that can avoid diode to occur after size is dwindled according to vertical memory cell structures of the present disclosure.According to manufacture method of the present disclosure, just can realize the memory array structure of multilayer by Twi-lithography, significantly reduced manufacturing cost, be fit to very much large-scale production.Overcome the problem that is difficult to random read-write of general cubical array according to reading/writing method of the present disclosure.
Description of drawings
Fig. 1 has schematically shown the structural representation according to the storage array of the exemplary resistance-variable storing device of disclosure embodiment.
Fig. 2 has schematically shown the schematic diagram according to the resistance-variable storing device of disclosure embodiment.
Fig. 3 has schematically shown according to the disclosure embodiment resistance-variable storing device shown in Figure 2 has been wiped/schematic diagram of write operation.
Fig. 4 shows and according to disclosure embodiment, resistance-variable storing device shown in Figure 2 is carried out the schematic diagram of read operation.
Fig. 5 shows the resistance-variable storing device manufacture method according to disclosure embodiment.
Embodiment
Hereinafter with reference to accompanying drawing, the disclosure is described in more detail.Whether in the following description, no matter be presented in different embodiment, similarly parts adopt same or similar Reference numeral to represent.In each accompanying drawing, for the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
Described hereinafter many specific details of the present disclosure, for example structure of device, material, size, treatment process and technology, in order to more clearly understand the disclosure.But such just as the skilled person will understand, can realize the disclosure not according to these specific details.Unless particularly point out hereinafter, the various piece in semiconductor device can consist of the known material of those skilled in the art, perhaps can adopt the material with similar functions of exploitation in the future.
Fig. 1 shows the structural representation according to the storage array 100 of the exemplary resistance-variable storing device of disclosure embodiment.As shown in Figure 1, this storage array 100 comprises substrate 101.Form substrate isolation layer 102 on substrate 101.Form a plurality of laminated construction 103-1,103-2 and the 103-3 that is arranged in parallel on substrate isolation layer 102.Can arrange according to actual needs than more or less laminated construction shown in Figure 1.Each laminated construction comprises and replaces stacking metal level 104-1,104-2 and 104-3 and separator 105-1,105-2 and 105-3.Can arrange as required than more or less metal level shown in Figure 1 and separator.On substrate isolation layer 102 and laminated construction 103-1,103-2 and 103-3, length direction along laminated construction forms a plurality of pectination metal level 106-1,106-2 and the 106-3 that is arranged in parallel, the length direction of described a plurality of pectination metal levels is vertical with the length direction of laminated construction, and the broach of each pectination metal level is clipped between adjacent laminated construction.Accompany resistive material layer 107-1,107-2 and 107-3 between each pectination metal level and corresponding laminated construction.Can arrange as required than more or less resistive material layer shown in Figure 1.
According to embodiment of the present disclosure, storage array 100 can comprise a plurality of memory cell.As shown in Figure 1, each memory cell can comprise a metal level in laminated construction, a corresponding pectination metal level and both between the resistive material layer.For example, as in Fig. 1 by as shown in the part of dotted line, exemplary memory unit 201 can comprise metal level 104-2, pectination metal level 106-1, and the resistive material layer 107-1 both.Therefore, storage array shown in Figure 1 comprises 3*3*3=27 memory cell altogether.
According to embodiment of the present disclosure, the material of substrate 101 can be Si, Ge or III-V compounds of group (as SiC, GaAs, indium arsenide, indium phosphide etc.).The material of substrate isolation layer 102 can be SiO
2Or Si
4N
3, thickness can be 10-300nm.Each metal level 104-1,104-2 in laminated construction 103-1,103-2 and 103-3 and the material of 104-3 can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni, and thickness can be 5-100nm.Each separator 105-1,105-2 in laminated construction 103-1,103-2 and 103-3 and the material of 105-3 can be SiO
2Or Si
4N
3, thickness can be 10-300nm.The width of laminated construction 103-1,103-2 and 103-3 can be 10-100nm.The material of pectination metal level 106-1,106-2 and 106-3 can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni.Each pectination metal level 106-1,106-2 and 106-3 can be 50-2000nm along the height H perpendicular to substrate surface, along the thickness T of laminated construction length direction, can be 5-100nm.
According to embodiment of the present disclosure, the thickness of resistive material layer can be 4-50nm.Resistive material layer 107-1,107-2 and 107-3 can only comprise the resistive material, can comprise that also one deck resistive material and one deck have the material of rectification characteristic.The resistive material can be by being selected from HfO
2, NiO, TiO
2, ZrO
2, ZnO, WO
3, Ta
2O
5, Al
2O
3, CeO
2, La
2O
3, Gd
2O
3And a kind of in the group that forms of combination in any.Material with rectification characteristic can be doped polycrystalline silicon or other oxide semiconductors, as CuO or ZnO.
Fig. 2 has schematically shown the schematic diagram according to the resistance-variable storing device 200 of disclosure embodiment.As shown in Figure 2, this resistance-variable storing device 200 comprises 2*2*3=12 memory cell, illustrates with the black round dot in the drawings.These memory cell for example can be corresponding to the resistive element of the laminated construction 103-1 in Fig. 1 and 103-2 and pectination metal level 106-1 and 106-2 and corresponding resistive material layer 107-1 and 107-2 formation.In Fig. 2, for the sake of clarity only show 12 memory cell, but more or less memory cell can be set as required.Resistance-variable storing device 200 also comprises word line WL1 and WL2 and bit line BL1, BL2 and BL3.Word line WL1 is connected with corresponding memory cell by word line selection logical transistor WT1, WT2 respectively with WL2.Bit line BL1 is connected with corresponding memory cell by bit line select transistor BT1-1, BT1-2.Bit line BL2 is connected with corresponding memory cell by bit line select transistor BT2-1, BT2-2.Bit line BL3 is connected with corresponding memory cell by bit line select transistor BT3-1, BT3-2.The grid of the bit line select transistor that is connected with corresponding lines not is connected to corresponding selection line.As shown in Figure 2, the grid of bit line select transistor BT1-1, BT2-1, BT3-1 is connected to and selects line SL1, the grid of bit line select transistor BT1-2, BT2-2, BT3-2 to be connected to selection line SL2.For convenience of description, numbering based on the logical transistor of the word line selection that connects and bit line select transistor is numbered the memory cell in resistance-variable storing device 200 respectively, namely, the memory cell that is connected to the logical transistor WT1 of word line selection and bit line select transistor BT1-1 is designated as SC111, the memory cell that is connected to the logical transistor WT1 of word line selection and bit line select transistor BT1-2 is designated as SC112, by that analogy.Correspondingly, the memory cell that is connected to the logical transistor WT2 of word line selection and bit line select transistor BT3-2 is designated as SC232.Like this, can be the memory cell number consecutively in resistance-variable storing device SC111, SC112, SC121, SC122, SC131, SC132, SC211, SC212, SC221, SC222, SC231, SC232.Show an exemplary memory unit SC221 with dashed circle in Fig. 2.
According to embodiment of the present disclosure, each memory cell for example can have the structure identical with memory cell shown in Figure 1 201.For brevity, only for Fig. 1 relevant with Fig. 2, partly describe.But,, based on instruction of the present disclosure, can be as required the remainder of Fig. 1 be similarly arranged.According to embodiment of the present disclosure, each pectination metal level shown in Figure 1 can be used as that a word line is drawn and with the logical transistor of a word line selection, is connected.For example, pectination metal level 106-1 can be used as word line WL1 and draws, and with the logical transistor WT1 of word line selection, is connected.Pectination metal level 106-2 can be used as word line WL1 and draws, and with the logical transistor WT2 of word line selection, is connected.Each metal level in each laminated construction shown in Figure 1 can at one end be connected with a bit line select transistor, and the source electrode of a plurality of bit line select transistors that are connected with the metal level that has equal height with respect to substrate surface is connected with the same bit line.For example, the source electrode of the bit line select transistor BT1-1 that is connected with metal level 104-1 in laminated construction 103-1 with laminated construction 103-2 in be connected to bit line BL1 with the source electrode that metal level 104-1 is in the bit line select transistor BT1-2 that the metal level of equal height is connected.The bit line select transistor BT that is connected with metal level 104-2 in laminated construction 103-1 with laminated construction 103-2 in be connected to bit line BL2 with the source electrode that metal level 104-2 is in the bit line select transistor that the metal level of equal height is connected.The bit line select transistor BT that is connected with metal level 104-3 in laminated construction 103-1 with laminated construction 103-2 in be connected to bit line BL3 with the source electrode that metal level 104-3 is in the bit line select transistor that the metal level of equal height is connected.The grid of the bit line select transistor that is connected with metal level in same laminated construction can be connected to same and select line.For example, with laminated construction 103-1 in metal level 104-1,104-2, bit line select transistor BT1-1, BT2-1, the BT3-1 that 104-3 is connected can be connected to selectivity SL1.Bit line select transistor BT1-2, BT2-2, the BT3-2 that is connected with three metal levels in laminated construction 103-2 can be connected to and select line SL2.
Below in conjunction with Fig. 3 and Fig. 4, method according to the operation resistance-variable storing device as shown in Figure 2 of disclosure embodiment is described.The operation of resistance-variable storing device is comprised and wipes/write process and read procedure.
Fig. 3 has schematically shown according to the disclosure embodiment resistance-variable storing device shown in Figure 2 has been wiped/schematic diagram of write operation.The erase process of resistance-variable storing device refers to a device R ESET to high-impedance state, and ablation process refers to that a device SET is to low resistance state.RESET except the required voltage that applies is different, does not have other differences with the SET process.Fig. 3 shows to wipe/write in process and executes alive situation on each word line and bit line.As shown in Figure 3, by selecting word line, bit line and selection line, select the memory cell that will wipe/write, apply on the memory cell of choosing and wipe (perhaps writing) required magnitude of voltage, this device is wiped (perhaps writing).The voltage that unchecked memory cell is applied is no more than half of wiping (perhaps writing) required voltage value, by selecting suitable resistive material, make memory cell, under half erasable voltage, the situation of by accident, being wiped/writing can not occur, this array just can be correct wiping/write the memory cell that any one is chosen, and do not affect the state of other all memory cell.For example, as shown in Figure 3,, if memory cell SC221 is wiped/write operation, the word line WL2 that is connected with memory cell SC221 is applied and wipes/write voltage V
Reset/ V
set, with bit line BL2 ground connection (GND), and to selecting line SL1 to apply cut-in voltage V
on.Like this, apply the required voltage V of erase operation on memory cell SC221
ResetOr the required voltage V of write operation
setThereby, realize wiping/write operation., for other memory cell, apply less than wiping/write voltage V on coupled word line WL1
Reset/ V
setThe voltage of half, float coupled bit line and selection line (F) simultaneously, and the voltage that makes these memory cell two ends be applied in all is no more than half of wiping (perhaps writing) required voltage value, thereby it is not wiped/write operation.According to wiping/write method of the present disclosure, each memory cell can by independently, access randomly, and need to be on each memory cell series diode, the problem that can avoid bypass to disturb.
Fig. 4 shows and according to disclosure embodiment, resistance-variable storing device shown in Figure 2 is carried out the schematic diagram of read operation.The process that reads of resistance-variable storing device is to apply and read voltage to the memory cell that will read, and by the detecting amplifier of with this memory cell, connecting, measures the electric current that passes through this memory cell.Judge that based on the electric current of measuring this memory cell is in high-impedance state or low resistance state, to determine the data value of this cell stores.As shown in Figure 4, when carrying out read operation, with all bit line BL1～BL3 ground connection.Select one to select line (in this example, SL1) and apply the required cut-in voltage V of bit line select transistor
on, will select all bit line select transistors that line SL1 controls to open.Simultaneously, select a word line (in this example, WL2), to apply and read voltage V
Read, other bit line ground connection (GND).All be applied in and read voltage V like this, and on the selection line SL1 that chooses and all memory cell SC211, SC221 between selected word line WL2, SC231
Read, there is no on selected memory cell not apply voltage.Every bit lines is connected with a detecting amplifier, can read the electric current on memory cell chosen by correspondence, to determine the data value of storing in memory cell.As shown in Figure 4, bit line BL1, BL2 are connected with SA3 with detecting amplifier SA1, SA2 respectively with BL3.Detecting amplifier SA1, SA2 and SA3 detect respectively electric current by memory cell SC211, SC221 and SC231 to determine the wherein data value of storage.Can read simultaneously the data value of a plurality of cell stores according to read method of the present disclosure, thereby improve the efficiency that reads.
Below in conjunction with the resistance-variable storing device manufacture method of Fig. 5 description according to disclosure embodiment.As shown in the part (a) of Fig. 5, form substrate isolation layer 102 by deposition or thermal oxidation on substrate 101.The material of substrate 101 can be Si, Ge or III-V compounds of group (as SiC, GaAs, indium arsenide, indium phosphide etc.).The material of separator 102 can be SiO
2Or Si
4N
3, thickness can be 10-300nm.Then, continuous alternating deposition metal level and separator 104-1,105-1,104-2,105-2,104-3 and 105-3.The thickness of every layer of metal level can be 5-100nm, and material can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir, Ni.The thickness of every layer of separator can be 5-300nm, and material can be SiO
2Or Si
4N
3.Only schematically show alternately 3 metal levels and separator in Fig. 5, but can arrange according to actual needs more multi-layered.Then, utilize the chemical wet etching technology to carry out etching to metal level and separator 104-1,105-1,104-2,105-2,104-3 and the 105-3 that replaces, described etching stopping is in substrate isolation layer 102.Form 3 laminated construction 103-1,103-2 and 103-3 by etching.The width of each laminated construction can be 5-100nm.Then, deposition resistive material layer 107 on laminated construction and substrate isolation layer.Can utilize ald (ALD) to form the resistive material layer.The thickness of resistive material layer can be 4-50nm, and can only comprise the material (for example metal oxide) with resistive characteristic, also can not only comprise the material with resistive characteristic but also comprise the material with rectification characteristic.Material with resistive characteristic can be by being selected from HfO
2, NiO, TiO
2, ZrO
2, ZnO, WO
3, Ta
2O
5, Al
2O
3, CeO
2, La
2O
3, Gd
2O
3And a kind of in the group that forms of combination in any.Material with rectification characteristic can be doped polycrystalline silicon and or other oxide semiconductors, as CuO or ZnO.Then deposited metal 106 on this structure.Can utilize physical vapour deposition (PVD) (PVD) to form metal level 106.Metal level 106 can be 50-1000nm along the size perpendicular to substrate surface, and material can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir, Ni.Utilize photoetching technique or lithographic technique,, take the described a plurality of laminated construction of substrate isolation layer as stop-layer etching sheet metal 106 and resistive material layer, form pectination metal level 106-1,106-2 and 106-3 and corresponding resistive material layer 107-1,107-2,107-3.The length direction of pectination metal level 106-1,106-2 and 106-3 is vertical with the length direction of laminated construction 103-1,103-2 and 103-3.Each pectination metal level 106-1,106-2 and 106-3 can be 10-100nm along the size of laminated construction length direction.So just formed storage array 100 as shown in Figure 2.Next, prepare the logical transistor of word line, bit line, selection line, word line selection, bit line select transistor etc., and the common process of the follow-up semiconductor machining such as lead-in wire, passivation, encapsulation, to form the resistance-variable storing device according to disclosure embodiment.
A concrete example making storage array according to disclosure embodiment is below described.This example can comprise the following steps:
1. thermal oxidation thickness is the SiO of 10-300nm on silicon substrate
2Layer is as the substrate isolation layer.
2. utilize the TiN layer of the method deposition 5-100nm of physical vapour deposition (PVD) (PVD) on said structure.
3. utilize the SiO of the method deposition 5-300nm of chemical vapour deposition (CVD) (CVD) on said structure
2Layer.
4. repeating step 2 and more than 3 time are to form TiN layer and SiO
2The lamination of layer.
5. use the substrate isolation layer as stop-layer, with photoetching and lithographic technique, above-mentioned lamination is carried out etching, obtaining width is a plurality of laminated construction of 5-100nm.
6. utilize the method deposition resistive material layer HfO of ald (ALD) on said structure
2, thickness is 4-50nm.
7. utilize the method depositing TiN metal level of physical vapour deposition (PVD) PVD on said structure, thickness is 50-2000nm.
8. utilize photoetching and lithographic technique etching TiN metal level, obtaining a plurality of width is the pectination metal level of 10-100nm.
9. prepare gate transistor, and the common process of the follow-up semiconductor machining such as lead-in wire, passivation, encapsulation.
Although embodiment illustrates and has described the disclosure with reference to disclosure particular example, yet it will be appreciated by those skilled in the art that, under the prerequisite that does not break away from the spirit and scope of the present disclosure that limited by claims and equivalent thereof, can carry out change on various forms and details to the disclosure.The scope of the present disclosure is not limited to above-mentioned example, and spirit of the present disclosure should be determined jointly by claims and its equivalent.
Claims (19)
1. a resistance-variable storing device, comprise storage array, and described storage array comprises:
Substrate;
The substrate isolation layer, be arranged on substrate;
A plurality of laminated construction, be arranged on the substrate isolation layer;
A plurality of pectination metal levels, be arranged on substrate isolation layer and described a plurality of laminated construction along the length direction of described laminated construction, and the broach of each pectination metal level is clipped between adjacent laminated construction; And
A plurality of resistive material layers, each resistive material layer are formed between a corresponding pectination metal level and described substrate isolation layer and between a corresponding pectination metal level and described a plurality of laminated construction.
2. resistance-variable storing device according to claim 1, wherein, each laminated construction comprises and replaces stacking metal level and separator.
3. resistance-variable storing device according to claim 1, wherein, the length direction of described a plurality of pectination metal levels intersects with the length direction of laminated construction.
4. resistance-variable storing device according to claim 1, wherein, the resistive material layer only comprises the resistive material, or comprises that one deck resistive material and one deck have the material of rectification characteristic.
5. resistance-variable storing device according to claim 1, wherein, described resistance-variable storing device also comprises:
Many word lines, by extracting described a plurality of pectination metal levels to form described many word lines via the logical transistor of a word line selection respectively;
Multiple bit lines, each metal level in each laminated construction at one end is connected with a bit line select transistor, and the source electrode of a plurality of bit line select transistors that are connected with the metal level that has equal height with respect to substrate surface is connected to a corresponding bit line; And
Select lines for many, the grid of the bit line select transistor that is connected with metal level in same laminated construction is connected to a corresponding selection line.
6. resistance-variable storing device according to claim 1, wherein, the substrate isolation layer comprises SiO
2Or Si
4N
3, the thickness of substrate isolation layer is 10-300nm.
7. resistance-variable storing device according to claim 1, wherein:
Each metal level in laminated construction comprises any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni, and the thickness of described each metal level is 5-100nm; And
Each separator in laminated construction comprises SiO
2Or Si
4N
3, the thickness of described each separator is 5-300nm.
8. resistance-variable storing device according to claim 1, wherein:
The pectination metal level comprises any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni; And
Each pectination metal level is 50-2000nm along the height perpendicular to substrate surface, along the thickness of the length direction of laminated construction, is 5-100nm.
9. resistance-variable storing device according to claim 5, wherein:
The thickness of resistive material layer is 4-50nm;
The resistive material comprises and is selected from HfO
2, NiO, TiO
2, ZrO
2, ZnO, WO
3, Ta
2O
5, Al
2O
3, CeO
2, La
2O
3, Gd
2O
3And a kind of in the group that forms of combination in any; And
Material with rectification characteristic comprises doped polycrystalline silicon or other oxide semiconductors.
One kind the operation resistance-variable storing device according to claim 1 method, wherein, described resistance-variable storing device comprises a plurality of memory cell, each memory cell comprise a metal level in laminated construction, a corresponding pectination metal level and both between the resistive material layer
Described method comprises:
Apply erasing voltage, write voltage or read voltage by the memory cell to selected, realize respectively wiping, write or read operation.
11. method according to claim 10, wherein, described resistance-variable storing device also comprises:
Many word lines, the memory cell that is connected to same pectination metal level is connected to a corresponding word line via the logical transistor of a word line selection;
Multiple bit lines, the source electrode of a plurality of bit line select transistors that are connected with the memory cell that has equal height with respect to substrate surface is connected to a corresponding bit line; And
Select lines for many, the grid of the bit line select transistor that is connected with memory cell in same laminated construction is connected to a corresponding selection line,
Described method also comprises:
By selecting word line, bit line and selection line to carry out select storage unit.
12. method according to claim 11 comes select storage unit to comprise by selecting word line, bit line and selection line:
When carrying out erase operation: for the memory cell that will select, the word line is applied erasing voltage, with bit line ground connection, and to selecting line to apply cut-in voltage; And, for other memory cell, at the word line, apply less than half voltage of erasing voltage bit line and select line to float simultaneously;
When carrying out write operation: for the memory cell that will select, the word line is applied and writes voltage, with bit line ground connection, and to selecting line to apply cut-in voltage; And, for other memory cell, at the word line, apply less than writing half voltage of voltage bit line and select line to float simultaneously; And
When carrying out read operation, with all bit line ground connection, the selection line that the memory cell with reading is associated applies cut-in voltage, and the word line that the memory cell with reading is associated applies and reads voltage, with other bit line ground connection.
13. a method of making resistance-variable storing device comprises:
Form the substrate isolation layer on substrate;
Alternately form a plurality of metal levels and a plurality of separator on the substrate isolation layer;
Use the substrate isolation layer as stop-layer, the described a plurality of metal levels of etching and a plurality of separator, a plurality of laminated construction that are arranged in parallel with formation;
Deposit resistive material on described a plurality of laminated construction and substrate isolation layer;
Form another metal level on the resistive material layer;
Use substrate isolation layer and described a plurality of laminated construction as stop-layer, and described another metal level of etching and described resistive material, to form a plurality of pectination metal levels and corresponding a plurality of resistive material layer.
14. method according to claim 13 also comprises:
Deposit and etching have the material of rectification characteristic, thereby described a plurality of resistive material layer comprises the material of described rectification characteristic.
15. method according to claim 13 also comprises:
Form many word lines, by described a plurality of pectination metal levels are extracted and form described many word lines via the logical transistor of a word line selection respectively;
Form multiple bit lines, each metal level in each laminated construction at one end is connected with a bit line select transistor, and the source electrode of a plurality of bit line select transistors that are connected with the metal level that has equal height with respect to substrate surface is connected to a corresponding bit line; And
Form many and select lines, the grid of the bit line select transistor that is connected with metal level in same laminated construction is connected to a corresponding selection line.
16. method according to claim 13, wherein, the substrate isolation layer comprises SiO
2Or Si
4N
3, the thickness of substrate isolation layer is 10-300nm.
17. method according to claim 13, wherein:
Each metal level in laminated construction comprises any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni, and the thickness of described each metal level is 5-100nm; And
Each separator in laminated construction comprises SiO
2Or Si
4N
3, the thickness of described each separator is 5-300nm.
18. method according to claim 13, wherein:
The pectination metal level comprises any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni; And
Each pectination metal level is 50-2000nm along the height perpendicular to substrate surface, along the thickness of the length direction of laminated construction, is 5-100nm.
19. method according to claim 14, wherein:
The thickness of resistive material layer is 4-50nm;
The resistive material comprises and is selected from HfO
2, NiO, TiO
2, ZrO
2, ZnO, WO
3, Ta
2O
5, Al
2O
3, CeO
2, La
2O
3, Gd
2O
3And a kind of in the group that forms of combination in any; And
Material with rectification characteristic comprises doped polycrystalline silicon or other oxide semiconductors.
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