CN103390629B - Resistance-variable storing device and operational approach thereof and manufacture method - Google Patents
Resistance-variable storing device and operational approach thereof and manufacture method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 96
- 239000002184 metal Substances 0.000 claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 70
- 238000010276 construction Methods 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000007789 sealing Methods 0.000 claims abstract description 53
- 230000008859 change Effects 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052718 tin Inorganic materials 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- 229910004166 TaN Inorganic materials 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229910052741 iridium Inorganic materials 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052697 platinum Inorganic materials 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 4
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 claims description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000007667 floating Methods 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims 3
- 239000013078 crystal Substances 0.000 claims 2
- 239000000284 extract Substances 0.000 claims 2
- 238000005240 physical vapour deposition Methods 0.000 description 9
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- GNRSAWUEBMWBQH-UHFFFAOYSA-N nickel(II) oxide Inorganic materials [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- 102100023696 Histone-lysine N-methyltransferase SETDB1 Human genes 0.000 description 1
- 101710168120 Histone-lysine N-methyltransferase SETDB1 Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Semiconductor Memories (AREA)
Abstract
Providing a kind of resistance-variable storing device, including storage array, described storage array includes: substrate；Substrate sealing coat, is arranged on substrate；Multiple laminated construction, are arranged on substrate sealing coat；Multiple comb metal layers, the length direction along described laminated construction is arranged on substrate sealing coat and the plurality of laminated construction, and the comb of each comb metal layer is clipped between adjacent laminated construction；And multiple resistance change material layer, each resistance change material layer is formed between a corresponding comb metal layer and described substrate sealing coat and between a corresponding comb metal layer and the plurality of laminated construction.Additionally provide operational approach and the manufacture method of this resistance-variable storing device.
Description
Technical field
It relates to memory device, relate more specifically to resistance-variable storing device and operational approach thereof and manufacture method.
Background technology
At present, the development of microelectronics industry promotes the continuous progressive of memory technology, improves integration density and reduction production cost is the target that memorizer industry is pursued.Non-volatility memorizer has at non-transformer at once remaining to keep the advantage of data message, has very important status at area information storage.
The novel non-volatility memorizer using resistive material has (＜ 1ns), low operating voltage (＜ 1.5V) at high speed, high storage density, the advantage such as it is easily integrated, is the strong competitor of generation semiconductor memorizer.This resistance-variable storing device typically has M-I-M (Metal-Insulator-Metal, metal-insulator-metal type) structure, i.e. accompanies resistance change material layer between two metal electrodes.Resistive material can show two stable states, i.e. high-impedance state and low resistance state.By the transformation of high-impedance state to low resistance state commonly referred to programming or set (SET) operation, by the transformation of low resistance state to high-impedance state commonly referred to erasing or (RESET) operation that resets.
Resistance-variable storing device includes the array of the multiple variable-resistance memory unit being arranged in rows.According to the basic configuration of memory element, resistance-variable storing device can be divided into 1T-1R or 1D-1R two kinds.In the resistance-variable storing device of 1T-1R configuration, each memory element is made up of a gating transistor and a resistive element.By controlling the gating transistor of selected memory cell, to the memory element write specified or data can be wiped from it.In the resistance-variable storing device of 1D-1R configuration, each memory element is made up of a diode and a resistive element.The chip area (footprint) taken due to diode is less than the chip area of transistor, and therefore, the resistance-variable storing device of 1D-1R configuration can realize high storage density.In the resistance-variable storing device of 1D-1R configuration, diode is for preventing the cross talk effects of bypass.Every a line and every string of resistance-variable storing device connect gating transistor respectively.By controlling the gating transistor of selected row and column, can be to the memory element write specified or erasing data.Diode should be designed to provide enough and drive electric current to guarantee the transformation of Resistance states.
In order to improve memory density further, three-dimensionally integrated resistance-variable storing device can be used.By the resistive memory of vertical stacking multilamellar on substrate, memory density can be improved exponentially and do not dramatically increase chip area and increase manufacturing cost.But, the resistance-variable storing device of employing 1T-1R configuration or 1D-1R configuration is difficult to three-dimensionally integrated due to the existence of transistor or diode.Generally, the operating current of diode is directly proportional to its chip area.After the size reduction of diode, diode is likely difficult to provide sufficiently large driving electric current.
Summary of the invention
Present disclose provides resistance-variable storing device and operational approach thereof and manufacture method.
Providing a kind of resistance-variable storing device according to an aspect of this disclosure, including storage array, described storage array includes: substrate；Substrate sealing coat, is arranged on substrate；Multiple laminated construction, are arranged on substrate sealing coat；Multiple comb metal layers, the length direction along described laminated construction is arranged on substrate sealing coat and the plurality of laminated construction, and the comb of each comb metal layer is clipped between adjacent laminated construction；And multiple resistance change material layer, each resistance change material layer is formed between a corresponding comb metal layer and described substrate sealing coat and between a corresponding comb metal layer and the plurality of laminated construction.
A kind of method operating resistance-variable storing device as above is provided according to another aspect of the present disclosure, wherein, described resistance-variable storing device includes multiple memory element, each memory element includes a metal level in laminated construction, a corresponding comb metal layer and resistance change material layer therebetween, described method includes: by applying erasing voltage, write voltage or read voltage to selected memory element, realize erasing, write or read operation respectively.
A kind of method manufacturing resistance-variable storing device is provided according to another aspect of the present disclosure, including: on substrate, form substrate sealing coat；Substrate sealing coat is alternatively formed multiple metal level and multiple sealing coat；Using substrate sealing coat as stop-layer, etch the plurality of metal level and multiple sealing coat, to form multiple laminated construction arranged in parallel；The plurality of laminated construction and substrate sealing coat deposit resistive material；Resistance change material layer forms another metal level；Using substrate sealing coat and the plurality of laminated construction as stop-layer, etching another metal level described and described resistive material, to form multiple comb metal layer and corresponding multiple resistance change material layer.
The three-dimensional high-density achieving memory cell array according to the disclosure is integrated, significantly improves integration density.Vertical memory cell structures according to the disclosure can avoid the problem that offer circuit capacity that diode occurs after size reduction is not enough.According to the manufacture method of the disclosure, just can be realized the memory array structure of multilamellar by Twi-lithography, significantly reduce manufacturing cost, be especially suitable for large-scale production.Reading/writing method according to the disclosure overcomes the problem being difficult to random read-write of general cubical array.
Accompanying drawing explanation
Fig. 1 diagrammatically illustrates the structural representation of the storage array of the exemplary resistance-variable storing device according to disclosure embodiment.
Fig. 2 diagrammatically illustrates the schematic diagram of the resistance-variable storing device according to disclosure embodiment.
Fig. 3 diagrammatically illustrates, according to disclosure embodiment, the resistance-variable storing device shown in Fig. 2 is wiped the/schematic diagram of write operation.
Fig. 4 shows the schematic diagram being read the resistance-variable storing device shown in Fig. 2 according to disclosure embodiment.
Fig. 5 shows the resistance-variable storing device manufacture method according to disclosure embodiment.
Detailed description of the invention
It is more fully described the disclosure hereinafter with reference to accompanying drawing.In the following description, regardless of whether display is in different embodiments, similar parts use same or similar reference to represent.In various figures, for the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.
Describe hereinafter the many specific structure of details, such as device, material, size, process technique and the technology of the disclosure, in order to be more clearly understood that the disclosure.But the most as the skilled person will understand, the disclosure can not be realized according to these specific details.Unless hereinafter particularly pointed out, the various piece in semiconductor device can be made up of material well known to those skilled in the art, or can use the material with similar functions of exploitation in the future.
Fig. 1 shows the structural representation of the storage array 100 of the exemplary resistance-variable storing device according to disclosure embodiment.As it is shown in figure 1, this storage array 100 includes substrate 101.Form substrate sealing coat 102 on the substrate 101.Substrate sealing coat 102 is formed multiple laminated construction 103-1,103-2 and 103-3 arranged in parallel.The more or less of laminated construction than shown in Fig. 1 can be set according to actual needs.Each laminated construction includes metal level 104-1,104-2 and 104-3 and sealing coat 105-1,105-2 and the 105-3 being alternately stacked.More or less of metal level and sealing coat can be arranged as required to than shown in Fig. 1.On substrate sealing coat 102 and laminated construction 103-1,103-2 and 103-3, length direction along laminated construction forms multiple comb metal layer 106-1,106-2 and 106-3 arranged in parallel, the length direction of the plurality of comb metal layer is vertical with the length direction of laminated construction, and the comb of each comb metal layer is clipped between adjacent laminated construction.Resistance change material layer 107-1,107-2 and 107-3 is accompanied between each comb metal layer and corresponding laminated construction.The more or less of resistance change material layer than shown in Fig. 1 can be arranged as required to.
According to embodiment of the disclosure, storage array 100 can include multiple memory element.As it is shown in figure 1, each memory element can include a metal level in laminated construction, a corresponding comb metal layer and resistance change material layer therebetween.Such as, as shown in the part by dotted line in Fig. 1, exemplary memory unit 201 can include metal level 104-2, comb metal layer 106-1, and resistance change material layer 107-1 therebetween.Therefore, the storage array shown in Fig. 1 includes 3*3*3=27 memory element altogether.
According to embodiment of the disclosure, the material of substrate 101 can be Si, Ge or III-V (such as SiC, GaAs, indium arsenide, indium phosphide etc.).The material of substrate sealing coat 102 can be SiO2Or Si4N3, thickness can be 10-300nm.The material of each metal level 104-1,104-2 and 104-3 in laminated construction 103-1,103-2 and 103-3 can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni, and thickness can be 5-100nm.The material of each sealing coat 105-1,105-2 and 105-3 in laminated construction 103-1,103-2 and 103-3 can be SiO2Or Si4N3, thickness can be 10-300nm.The width of laminated construction 103-1,103-2 and 103-3 can be 10-100nm.The material of comb metal layer 106-1,106-2 and 106-3 can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni.It can be 50-2000nm that each comb metal layer 106-1,106-2 and 106-3 edge is perpendicular to the height H of substrate surface, and the thickness T along laminated construction length direction can be 5-100nm.
According to embodiment of the disclosure, the thickness of resistance change material layer can be 4-50nm.Resistance change material layer 107-1,107-2 and 107-3 can only include resistive material, it is also possible to include one layer of resistive material and one layer of material with rectification characteristic.Resistive material can be by selected from HfO2、NiO、TiO2、ZrO2、ZnO、WO3、Ta2O5、Al2O3、CeO2、La2O3、Gd2O3And the one in the group of combination in any composition.The material with rectification characteristic can be DOPOS doped polycrystalline silicon or other oxide semiconductors, such as CuO or ZnO.
Fig. 2 diagrammatically illustrates the schematic diagram of the resistance-variable storing device 200 according to disclosure embodiment.As in figure 2 it is shown, this resistance-variable storing device 200 includes 2*2*3=12 memory element, illustrate with black round dot in the drawings.These memory element such as can correspond to the resistive element that laminated construction 103-1 and 103-2 and comb metal layer 106-1 and 106-2 in Fig. 1 and corresponding resistance change material layer 107-1 and 107-2 is formed.In fig. 2, for the sake of clarity illustrate only 12 memory element, but more or less of memory element can be arranged as required to.Resistance-variable storing device 200 also includes wordline WL1 and WL2 and bit line BL1, BL2 and BL3.Wordline WL1 is connected with corresponding memory element by wordline gating transistor WT1, WT2 respectively with WL2.Bit line BL1 is connected with corresponding memory element by bit line select transistor BT1-1, BT1-2.Bit line BL2 is connected with corresponding memory element by bit line select transistor BT2-1, BT2-2.Bit line BL3 is connected with corresponding memory element by bit line select transistor BT3-1, BT3-2.It is connected to the grid of bit line select transistor that not corresponding lines is connected corresponding select line.As in figure 2 it is shown, the grid of bit line select transistor BT1-1, BT2-1, BT3-1 is connected to select line SL1, the grid of bit line select transistor BT1-2, BT2-2, BT3-2 is connected to select line SL2.For convenience of description, memory element in resistance-variable storing device 200 is numbered by based on the wordline gating transistor connected and bit line select transistor numbering respectively, i.e., the memory element being connected to wordline gating transistor WT1 and bit line select transistor BT1-1 is designated as SC111, the memory element being connected to wordline gating transistor WT1 and bit line select transistor BT1-2 is designated as SC112, by that analogy.Correspondingly, the memory element being connected to wordline gating transistor WT2 and bit line select transistor BT3-2 is designated as SC232.As such, it is possible to be SC111, SC112, SC121, SC122, SC131, SC132, SC211, SC212, SC221, SC222, SC231, SC232 the memory element number consecutively in resistance-variable storing device.Fig. 2 shows exemplary memory unit SC221 with dashed circle.
According to embodiment of the disclosure, each memory element such as can have the structure identical with the memory element 201 shown in Fig. 1.For brevity, illustrate only for Fig. 1 part relevant with Fig. 2.But, teaching based on the disclosure, the setting that can as required the remainder of Fig. 1 be similar to.According to embodiment of the disclosure, each comb metal layer shown in Fig. 1 can be drawn as a wordline and be connected with a wordline gating transistor.Such as, comb metal layer 106-1 can draw as wordline WL1, and is connected with wordline gating transistor WT1.Comb metal layer 106-2 can draw as wordline WL1, and is connected with wordline gating transistor WT2.Each metal level in each laminated construction shown in Fig. 1 can at one end be connected with a bit line select transistor, is connected with same bit line with the source electrode relative to substrate surface with multiple bit line select transistors that mutually level metal level is connected.Such as, the source electrode of the bit line select transistor BT1-1 being connected with the metal level 104-1 in laminated construction 103-1 and be connected to bit line BL1 with the source electrode being in the bit line select transistor BT1-2 that mutually level metal level is connected in laminated construction 103-2 with metal level 104-1.The bit line select transistor BT that is connected with the metal level 104-2 in laminated construction 103-1 and be connected to bit line BL2 with the source electrode being in the bit line select transistor that mutually level metal level is connected in laminated construction 103-2 with metal level 104-2.The bit line select transistor BT that is connected with the metal level 104-3 in laminated construction 103-1 and be connected to bit line BL3 with the source electrode being in the bit line select transistor that mutually level metal level is connected in laminated construction 103-2 with metal level 104-3.The grid of the bit line select transistor being connected with the metal level in same laminated construction may be coupled to same and selects line.Such as, bit line select transistor BT1-1, BT2-1, BT3-1 of being connected with metal level 104-1,104-2, the 104-3 in laminated construction 103-1 may be coupled to selectivity SL1.Bit line select transistor BT1-2, BT2-2, the BT3-2 being connected with three metal levels in laminated construction 103-2 may be coupled to select line SL2.
The method describing the resistance-variable storing device as shown in Figure 2 of the operation according to disclosure embodiment below in conjunction with Fig. 3 and Fig. 4.Operation to resistance-variable storing device includes wiping/write process and read procedure.
Fig. 3 diagrammatically illustrates, according to disclosure embodiment, the resistance-variable storing device shown in Fig. 2 is wiped the/schematic diagram of write operation.The erase process of resistance-variable storing device refer to device R ESET to high-impedance state, and ablation process refers to that a device SET is to low resistance state.RESET with SET process, in addition to the voltage of required applying is different, does not has other to distinguish.Fig. 3 shows and executes alive situation on each bar wordline and bit line during wiping/writing.As it is shown on figure 3, by selecting wordline, bit line and selection line to select the memory element to wipe/to write, the memory element chosen applies the magnitude of voltage needed for erasing (or write), this device is wiped (or write).The voltage applying unchecked memory element is less than the half of erasing (or write) required voltage value, by selecting suitable resistive material, make memory element will not occur by the situation of unexpected wiping/write under half erasable voltage, this array just can be correct wiping/write any one memory element chosen, and do not affect the state of other all memory element.Such as, if as it is shown on figure 3, memory element SC221 to be wiped/write operation, then apply to wipe/write voltage V to wordline WL2 being connected with memory element SC221reset/Vset, by bit line BL2 ground connection (GND), and to select line SL1 apply cut-in voltage Von.So, memory element SC221 applies the voltage V needed for erasing operationresetOr the voltage V needed for write operationset, thus realize wiping/write operation.For other memory element, coupled wordline WL1 applies less than wiping/write voltage Vreset/VsetThe voltage of half, simultaneously by coupled bit line and selection line floating (F), the voltage that these memory element two ends are applied in no more than wipes the half of (or write) required voltage value, thus it is not wiped/write operation.According to the wiping/write method of the disclosure, each memory element by independently, access randomly, and can need not series diode in each memory element, the problem that can avoid bypass interference.
Fig. 4 shows the schematic diagram being read the resistance-variable storing device shown in Fig. 2 according to disclosure embodiment.The reading process of resistance-variable storing device is to apply read voltage to memory element to be read, by the detection amplifier measuring electric current by this memory element connected with this memory element.Judge that this memory element is in high-impedance state or low resistance state, to determine the data value that this memory element stores based on the electric current measured.As shown in Figure 4, when being read, by all of bit line BL1～BL3 ground connection.One is selected to select line (in this example, SL1) and apply the cut-in voltage V needed for bit line select transistoron, all bit line select transistors selecting line SL1 to control are opened.Meanwhile, select a wordline (in this example, WL2), apply read voltage Vread, other wordline ground connection (GND).So, all memory element SC211 and between selection line SL1 and selected word line WL2 chosen, SC221, SC231 have been applied in read voltage Vread, there is no in selected memory element the most not apply voltage.Every bit lines and a detection amplifier connect, and can read by the corresponding electric current chosen in memory element, to determine the data value of storage in memory element.As shown in Figure 4, bit line BL1, BL2 and BL3 is connected with detection amplifier SA1, SA2 and SA3 respectively.Detection amplifier SA1, SA2 and SA3 detect respectively by memory element SC211, SC221 and SC231 electric current to determine the data value wherein stored.Read method according to the disclosure can read the data value of multiple memory element storage simultaneously, thus improves the efficiency of reading.
Below in conjunction with Fig. 5, the resistance-variable storing device manufacture method according to disclosure embodiment is described.As shown in the part (a) of Fig. 5, form substrate sealing coat 102 by deposition or thermal oxide on the substrate 101.The material of substrate 101 can be Si, Ge or III-V (such as SiC, GaAs, indium arsenide, indium phosphide etc.).The material of sealing coat 102 can be SiO2Or Si4N3, thickness can be 10-300nm.Then, continuous alternating deposition metal level and sealing coat 104-1,105-1,104-2,105-2,104-3 and 105-3.The thickness of every layer of metal level can be 5-100nm, and material can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir, Ni.The thickness of every layer of sealing coat can be 5-300nm, and material can be SiO2Or Si4N3.Fig. 5 schematically show only 3 metal levels alternately and sealing coat, but more layers can be set according to actual needs.Then, utilizing chemical wet etching technology to perform etching metal level alternately and sealing coat 104-1,105-1,104-2,105-2,104-3 and 105-3, described etching stopping is in substrate sealing coat 102.3 laminated construction 103-1,103-2 and 103-3 are formed by etching.The width of each laminated construction can be 5-100nm.Then, deposition resistance change material layer 107 on laminated construction and substrate sealing coat.Ald (ALD) can be utilized to form resistance change material layer.The thickness of resistance change material layer can be 4-50nm, and can only include the material (such as metal-oxide) with resistive characteristic, it is also possible to not only includes having the material of resistive characteristic but also include the material with rectification characteristic.The material with resistive characteristic can be by selected from HfO2、NiO、TiO2、ZrO2、ZnO、WO3、Ta2O5、Al2O3、CeO2、La2O3、Gd2O3And the one in the group of combination in any composition.Have the material of rectification characteristic can be DOPOS doped polycrystalline silicon and or other oxide semiconductors, such as CuO or ZnO.Deposited metal 106 the most on this structure.Physical vapour deposition (PVD) (PVD) can be utilized to form metal level 106.Metal level 106 can be 50-1000nm along the size being perpendicular to substrate surface, and material can be any one in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir, Ni.Utilize photoetching technique or lithographic technique, with the plurality of laminated construction of substrate sealing coat for stop-layer etching sheet metal 106 and resistance change material layer, form comb metal layer 106-1,106-2 and 106-3 and corresponding resistance change material layer 107-1,107-2,107-3.Comb metal layer 106-1,106-2 are vertical with the length direction of laminated construction 103-1,103-2 and 103-3 with the length direction of 106-3.Each comb metal layer 106-1,106-2 and 106-3 can be 10-100nm along the size of laminated construction length direction.Material is thus formed storage array 100 as shown in Figure 2.It follows that preparation wordline, bit line, selection line, wordline gating transistor, bit line select transistor etc., and go between, be passivated, the common process of the Subsequent semiconductor processing such as encapsulation, with formation according to the resistance-variable storing device of disclosure embodiment.
The concrete example manufacturing storage array according to disclosure embodiment is below described.This example may comprise steps of:
Thermal oxide thickness is the SiO of 10-300nm the most on a silicon substrate2Layer is as substrate sealing coat.
2. said structure above with physical vapour deposition (PVD) (PVD) method deposit 5-100nm TiN layer.
3. deposit the SiO of the method deposition 5-300nm of (CVD) above with chemical gaseous phase at said structure2Layer.
4. repeat step 2 and more than 3 time to form TiN layer and SiO2The lamination of layer.
5. use substrate sealing coat as stop-layer, with photoetching and lithographic technique, above-mentioned lamination is performed etching, obtain multiple laminated construction that width is 5-100nm.
6. on said structure, utilize the method deposition resistance change material layer HfO of ald (ALD)2, thickness is 4-50nm.
7. utilizing the method depositing TiN metal level of physical vapour deposition (PVD) PVD on said structure, thickness is 50-2000nm.
8. utilize photoetching and lithographic technique etching TiN metal level, obtain the comb metal layer that multiple width is 10-100nm.
9. preparation gating transistor, and go between, be passivated, common process that the Subsequent semiconductor such as encapsulation is processed.
Although illustrate and describing the disclosure with reference to disclosure particular example embodiment, but it will be appreciated by those skilled in the art that, on the premise of the spirit and scope without departing from the disclosure being defined by the appended claims and the equivalents thereof, the disclosure can be carried out the change on various forms and details.The scope of the present disclosure is not limited to above-mentioned example, and the spirit of the disclosure should be determined jointly by claims and its equivalent.
Claims (16)
1. a resistance-variable storing device, including storage array, described storage array includes:
Substrate；
Substrate sealing coat, is arranged on substrate；
Multiple laminated construction, are arranged on substrate sealing coat；
Multiple comb metal layers, the length direction along described laminated construction be arranged on substrate sealing coat and
On the plurality of laminated construction, the comb of each comb metal layer is clipped between adjacent laminated construction,
Described comb metal layer includes the comb of solid cylindrical and the crossbeam at the top of each comb of connection；Many
Individual resistance change material layer, each resistance change material layer is formed at a corresponding comb metal layer and described lining
Between end sealing coat and a corresponding comb metal layer and the plurality of laminated construction it
Between；
A plurality of wordline, by gating crystal via a wordline respectively by the plurality of comb metal layer
Pipe extracts the described a plurality of wordline of formation；
Multiple bit lines, each metal level in each laminated construction at one end with a bit line strobe crystalline substance
Body pipe connects, and has, with relative to substrate surface, multiple bit lines that mutually level metal level is connected
The source electrode of gating transistor is connected to a corresponding bit line；And
A plurality of selection line, the bit line select transistor being connected with the metal level in same laminated construction
Grid is connected to a corresponding selection line.
Resistance-variable storing device the most according to claim 1, wherein, each laminated construction includes
The metal level being alternately stacked and sealing coat.
Resistance-variable storing device the most according to claim 1, wherein, the plurality of comb metal
The length direction of layer intersects with the length direction of laminated construction.
Resistance-variable storing device the most according to claim 1, wherein, resistance change material layer only includes
Resistive material, or include one layer of resistive material and one layer of material with rectification characteristic.
Resistance-variable storing device the most according to claim 1, wherein, substrate sealing coat includes SiO2
Or Si4N3, the thickness of substrate sealing coat is 10-300nm.
Resistance-variable storing device the most according to claim 1, wherein:
Each metal level in laminated construction include TiN, TaN, Pt, Au, W, Cu, Al,
Any one in Ti, Ir and Ni, the thickness of described each metal level is 5-100nm；And
Each sealing coat in laminated construction includes SiO2Or Si4N3, the thickness of described each sealing coat
Degree is 5-300nm.
Resistance-variable storing device the most according to claim 1, wherein:
Comb metal layer includes in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni
Any one；And
It is 50-2000nm that each comb metal layer edge is perpendicular to the height of substrate surface, ties along lamination
The thickness of the length direction of structure is 5-100nm.
Resistance-variable storing device the most according to claim 4, wherein:
The thickness of resistance change material layer is 4-50nm；
Resistive material includes selected from HfO2、NiO、TiO2、ZrO2、ZnO、WO3、Ta2O5、
Al2O3、CeO2、La2O3、Gd2O3And the one in the group of combination in any composition；And
The material with rectification characteristic includes DOPOS doped polycrystalline silicon or other oxide semiconductors.
9. the method operating resistance-variable storing device according to claim 1, wherein, institute
State resistance-variable storing device to include:
Multiple memory element, each memory element includes a metal level in laminated construction, corresponding
A comb metal layer and resistance change material layer therebetween, described comb metal layer includes solid
The crossbeam at the top of the comb of column and each comb of connection；
A plurality of wordline, is connected to the memory element of same comb metal layer via a wordline gating crystalline substance
Body pipe is connected to a corresponding wordline；
Multiple bit lines, is connected many with having mutually level memory element relative to substrate surface
The source electrode of individual bit line select transistor is connected to a corresponding bit line；And
A plurality of selection line, the bit line select transistor being connected with the memory element in same laminated construction
Grid be connected to a corresponding selection line,
Described method includes:
By selecting wordline, bit line and selection line to carry out select storage unit；And
By applying erasing voltage, write voltage or read voltage to selected memory element, divide
Do not realize erasing, write or read operation.
Method the most according to claim 9, by selecting wordline, bit line and selection line
Select storage unit includes:
When carrying out erasing operation: for memory element to be selected, wordline is applied erasing voltage,
By bit line, and to selecting line to apply cut-in voltage；And for other memory element, at word
Line applies the voltage less than erasing voltage half, and bit line and selection line are floating simultaneously；
When carrying out write operation: for memory element to be selected, wordline is applied write voltage,
By bit line, and to selecting line to apply cut-in voltage；And for other memory element, at word
Line applies the voltage less than write voltage half, and bit line and selection line are floating simultaneously；And
When being read, by all of bit line, to memory element phase to be read
The selection line of association applies cut-in voltage, applies the wordline being associated with memory element to be read
Read voltage, by other wordline ground connection.
11. 1 kinds of methods manufacturing resistance-variable storing device, including:
Substrate is formed substrate sealing coat；
Substrate sealing coat is alternatively formed multiple metal level and multiple sealing coat；
Using substrate sealing coat as stop-layer, etch the plurality of metal level and multiple sealing coat, with
Form multiple laminated construction arranged in parallel；
The plurality of laminated construction and substrate sealing coat deposit resistive material；
Resistance change material layer forms another metal level；
Using substrate sealing coat and the plurality of laminated construction as stop-layer, etching another metal described
Layer and described resistive material, to form multiple comb metal layer and corresponding multiple resistance change material layer,
Described comb metal layer includes the comb of solid cylindrical and the crossbeam at the top of each comb of connection；
Form a plurality of wordline, by being gated via a wordline respectively by the plurality of comb metal layer
Transistor extracts the described a plurality of wordline of formation；
Forming multiple bit lines, each metal level in each laminated construction at one end selects with a bit line
Logical transistor connects, multiple with have that mutually level metal level is connected relative to substrate surface
The source electrode of bit line select transistor is connected to a corresponding bit line；And
Form a plurality of selection line, the bit line strobe crystal being connected with the metal level in same laminated construction
The grid of pipe is connected to a corresponding selection line.
12. methods according to claim 11, also include:
Deposit and etch the material with rectification characteristic, thus the plurality of resistance change material layer includes
The material of described rectification characteristic.
13. methods according to claim 11, wherein, substrate sealing coat includes SiO2Or
Si4N3, the thickness of substrate sealing coat is 10-300nm.
14. methods according to claim 11, wherein:
Each metal level in laminated construction include TiN, TaN, Pt, Au, W, Cu, Al,
Any one in Ti, Ir and Ni, the thickness of described each metal level is 5-100nm；And
Each sealing coat in laminated construction includes SiO2Or Si4N3, the thickness of described each sealing coat
Degree is 5-300nm.
15. methods according to claim 11, wherein:
Comb metal layer includes in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni
Any one；And
It is 50-2000nm that each comb metal layer edge is perpendicular to the height of substrate surface, ties along lamination
The thickness of the length direction of structure is 5-100nm.
16. methods according to claim 12, wherein:
The thickness of resistance change material layer is 4-50nm；
Resistive material includes selected from HfO2、NiO、TiO2、ZrO2、ZnO、WO3、Ta2O5、
Al2O3、CeO2、La2O3、Gd2O3And the one in the group of combination in any composition；And
The material with rectification characteristic includes DOPOS doped polycrystalline silicon or other oxide semiconductors.
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| CN104752609B (en) * | 2013-12-26 | 2017-06-20 | 北京有色金属研究总院 | A kind of resistance-variable storing device and preparation method thereof |
| CN104485418A (en) * | 2014-12-26 | 2015-04-01 | 中国科学院微电子研究所 | Self-gating resistive random access memory unit and preparation method thereof |
| US10608177B2 (en) | 2014-12-26 | 2020-03-31 | Institute of Microelectronics, Chinese Academy of Sciences | Self-gated RRAM cell and method for manufacturing the same |
| CN106205681A (en) * | 2015-04-29 | 2016-12-07 | 复旦大学 | The framework disturbed for three-dimensional vertical stacking resistance-variable storing device suppression IR drop voltage drop and read-write and operative algorithm |
| CN108305936A (en) * | 2017-01-12 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | Resistive RAM memory unit and preparation method thereof, electronic device |
| CN109244236B (en) * | 2018-08-01 | 2022-11-04 | 宁涉洋 | Memory structure |
| CN109962161A (en) * | 2018-12-03 | 2019-07-02 | 复旦大学 | 3D square crossing array and preparation method thereof based on built-in linear R RAM |
| CN113054101A (en) * | 2021-02-24 | 2021-06-29 | 中国科学院微电子研究所 | 3D vertical stacking integrated structure of RRAM and integration method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840995A (en) * | 2009-01-13 | 2010-09-22 | 三星电子株式会社 | Resistor-type random access memory and manufacture method thereof |
| CN102969328A (en) * | 2012-12-06 | 2013-03-13 | 北京大学 | Crossed array structure of resistive random access memory and manufacture method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010192800A (en) * | 2009-02-20 | 2010-09-02 | Toshiba Corp | Nonvolatile semiconductor memory device |
-
2013
- 2013-07-15 CN CN201310302371.0A patent/CN103390629B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840995A (en) * | 2009-01-13 | 2010-09-22 | 三星电子株式会社 | Resistor-type random access memory and manufacture method thereof |
| CN102969328A (en) * | 2012-12-06 | 2013-03-13 | 北京大学 | Crossed array structure of resistive random access memory and manufacture method thereof |
Non-Patent Citations (2)
| Title |
|---|
| HfOx Based Vertical Resistive Random Access Memory for Cost-Effective 3D Cross-Point Architecture without Cell Selector;Hong-Yu Chen,et al;《2012 Electron Devices Meeting》;20121213;20.7.1-70.7.4 * |
| Self-Recitifying Bipolar TaOx/TiO2 RRAM with Superior Endurance over 1012 Cycles For High-Density Storage-Class Memory;Chung-Wei Hsu,et al;《2013 Symposium on VLSI Technology》;20130613;T166 - T167 * |
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