CN103390629B - Resistance-variable storing device and operational approach thereof and manufacture method - Google Patents

Abstract

Provided is a resistive variable memory, including a storage array, and the storage array includes: a substrate; a substrate isolation layer arranged on the substrate; a plurality of stacked structures arranged on the substrate isolation layer; a plurality of comb-shaped The metal layer is arranged on the substrate isolation layer and the plurality of stacked structures along the length direction of the stacked structure, and the comb teeth of each comb-shaped metal layer are sandwiched between adjacent stacked structures; and multiple resistive switching material layers, each resistive switching material layer is formed between a corresponding one of the comb-shaped metal layers and the substrate isolation layer and between the corresponding one of the comb-shaped metal layers and the plurality of stacked structures . The operating method and manufacturing method of the resistive variable memory are also provided.

Description

Resistive memory and its operating method and manufacturing method

technical field

The present disclosure relates to memory devices, and more particularly to resistive memory devices and methods of operating and manufacturing the same.

Background technique

At present, the development of the microelectronics industry promotes the continuous progress of memory technology, and increasing integration density and reducing production costs are the goals pursued by the memory industry. Non-volatile memory has the advantage of maintaining data information when there is no power supply, and plays a very important role in the field of information storage.

The new non-volatile memory using resistive switching materials has the advantages of high speed (<1ns), low operating voltage (<1.5V), high storage density, and easy integration, and is a strong competitor for the next generation of semiconductor memory. Such a resistive variable memory generally has an M-I-M (Metal-Insulator-Metal, metal-insulator-metal) structure, that is, a resistive variable material layer is sandwiched between two metal electrodes. Resistive switching materials can exhibit two stable states, namely a high-resistance state and a low-resistance state. A transition from a high resistance state to a low resistance state is generally called a program or set (SET) operation, and a transition from a low resistance state to a high resistance state is generally called an erase or reset (RESET) operation.

The resistive memory includes an array of resistive memory cells arranged in rows and columns. According to the basic configuration of the storage unit, the resistive memory can be divided into two types: 1T-1R or 1D-1R. In a 1T-1R configured RRAM, each memory cell is composed of a pass transistor and a resistive element. Data can be written to or erased from a given memory cell by controlling the pass transistor of the selected memory cell. In the 1D-1R configuration resistive memory, each memory cell is composed of a diode and a resistive element. Since the chip area (footprint) occupied by the diode is smaller than that of the transistor, the resistive variable memory configured in 1D-1R can achieve high storage density. In the 1D-1R configuration RRAM, the diode is used to prevent the crosstalk effect of the bypass. A gate transistor is respectively connected to each row and each column of the RRAM. Data can be written or erased to a given memory cell by controlling the pass transistors of the selected row and column. The diode should be designed to provide sufficient drive current to ensure the transition of the resistive state.

In order to further increase the storage density, a three-dimensional integrated resistive memory can be used. By vertically stacking multiple layers of resistive switching memory devices on a substrate, the storage density can be doubled without significantly increasing the chip area and increasing the manufacturing cost. However, the RRAM adopting the 1T-1R configuration or the 1D-1R configuration is difficult to three-dimensionally integrate due to the existence of transistors or diodes. Generally, the operating current of a diode is directly proportional to its chip area. After the size of the diode shrinks, it may be difficult for the diode to provide a large enough driving current.

Contents of the invention

The present disclosure provides a resistive variable memory, an operating method and a manufacturing method thereof.

According to one aspect of the present disclosure, there is provided a resistive variable memory, including a storage array, and the storage array includes: a substrate; a substrate isolation layer disposed on the substrate; a plurality of stacked structures disposed on the substrate isolation layer On: a plurality of comb-shaped metal layers, arranged on the substrate isolation layer and the plurality of laminated structures along the length direction of the stacked structure, the comb teeth of each comb-shaped metal layer are sandwiched between adjacent stacked layers between the structures; and a plurality of resistive material layers, each resistive material layer is formed between a corresponding comb-shaped metal layer and the substrate isolation layer and between the corresponding comb-shaped metal layer and the multiple between stacked structures.

According to another aspect of the present disclosure, there is provided a method for operating the resistive memory as described above, wherein the resistive memory includes a plurality of memory cells, and each memory cell includes a metal layer in a stacked structure, corresponding A comb-shaped metal layer and a resistive material layer between the two, the method includes: respectively implementing erasing, writing or read operations.

According to another aspect of the present disclosure, there is provided a method for manufacturing a resistive variable memory, including: forming a substrate isolation layer on a substrate; alternately forming a plurality of metal layers and a plurality of isolation layers on the substrate isolation layer; The bottom isolation layer is used as a stop layer, and the plurality of metal layers and the plurality of isolation layers are etched to form a plurality of stacked structures arranged in parallel; a resistive switch is deposited on the plurality of stacked structures and the substrate isolation layer. material; forming another metal layer on the resistive material layer; using the substrate isolation layer and the plurality of stacked structures as stop layers, etching the other metal layer and the resistive material to form a plurality of combs metal layer and corresponding multiple resistive material layers.

According to the present disclosure, the three-dimensional high-density integration of the memory cell array is realized, and the integration density is significantly improved. The vertical memory cell structure according to the present disclosure can avoid the problem of insufficient circuit capability of the diode after the size is reduced. According to the manufacturing method of the present disclosure, a multi-layer memory array structure can be realized by two photolithography steps, which significantly reduces the manufacturing cost and is very suitable for mass production. The reading and writing method according to the present disclosure overcomes the problem of difficulty in random reading and writing of general three-dimensional arrays.

Description of drawings

FIG. 1 schematically shows a schematic structural view of a storage array of an exemplary RRAM according to an embodiment of the present disclosure.

FIG. 2 schematically shows a schematic diagram of a resistive variable memory according to an embodiment of the present disclosure.

FIG. 3 schematically shows a schematic diagram of erasing/writing operations on the resistive variable memory shown in FIG. 2 according to an embodiment of the present disclosure.

FIG. 4 shows a schematic diagram of a read operation of the RRAM shown in FIG. 2 according to an embodiment of the present disclosure.

FIG. 5 shows a manufacturing method of a resistive variable memory according to an embodiment of the present disclosure.

detailed description

Hereinafter, the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, similar components are denoted by the same or similar reference numerals whether they are shown in different embodiments or not. In the various drawings, for the sake of clarity, various parts in the drawings are not drawn to scale.

In the following, many specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of devices, are described for a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details. Unless otherwise specified below, each part in the semiconductor device may be composed of materials known to those skilled in the art, or materials having similar functions developed in the future may be used.

FIG. 1 shows a schematic structural diagram of a memory array 100 of an exemplary RRAM according to an embodiment of the present disclosure. As shown in FIG. 1 , the memory array 100 includes a substrate 101 . A substrate isolation layer 102 is formed on a substrate 101 . A plurality of stacked structures 103 - 1 , 103 - 2 and 103 - 3 arranged in parallel are formed on the substrate isolation layer 102 . More or fewer stacked structures than those shown in FIG. 1 can be provided according to actual needs. Each stack structure includes alternately stacked metal layers 104-1, 104-2, and 104-3 and isolation layers 105-1, 105-2, and 105-3. More or fewer metal layers and isolation layers than those shown in FIG. 1 can be provided as required. On the substrate isolation layer 102 and the laminated structures 103-1, 103-2 and 103-3, a plurality of comb-like metal layers 106-1, 106-2 and 106- 3. The length direction of the plurality of comb-shaped metal layers is perpendicular to the length direction of the laminated structure, and the teeth of each comb-shaped metal layer are sandwiched between adjacent laminated structures. Resistive material layers 107-1, 107-2 and 107-3 are sandwiched between each comb-shaped metal layer and the corresponding stacked structure. More or fewer resistive material layers than those shown in FIG. 1 can be provided as required.

According to an embodiment of the present disclosure, the memory array 100 may include a plurality of memory cells. As shown in FIG. 1 , each memory cell may include a metal layer in a laminated structure, a corresponding comb-shaped metal layer, and a resistive material layer between them. For example, as shown in the portion surrounded by a dotted line in FIG. 1 , an exemplary memory cell 201 may include a metal layer 104-2, a comb-shaped metal layer 106-1, and a resistive material layer 107-1 therebetween. Therefore, the memory array shown in FIG. 1 includes 3*3*3=27 memory cells in total.

According to an embodiment of the present disclosure, the material of the substrate 101 may be Si, Ge or III-V group compound (such as SiC, GaAs, InAs, InP, etc.). The material of the substrate isolation layer 102 may be SiO ₂ or Si ₄ N ₃ , and the thickness may be 10-300 nm. The material of each metal layer 104-1, 104-2 and 104-3 in the laminated structure 103-1, 103-2 and 103-3 may be TiN, TaN, Pt, Au, W, Cu, Al, Ti Any one of , Ir and Ni, the thickness can be 5-100nm. The material of each isolation layer 105-1, 105-2 and 105-3 in the laminated structures 103-1, 103-2 and 103-3 may be SiO ₂ or Si ₄ N ₃ , and the thickness may be 10-300 nm. The width of the stacked structures 103-1, 103-2 and 103-3 may be 10-100 nm. The material of the comb metal layers 106-1, 106-2 and 106-3 may be any one of TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni. The height H of each comb-shaped metal layer 106-1, 106-2 and 106-3 perpendicular to the substrate surface may be 50-2000 nm, and the thickness T along the length direction of the stacked structure may be 5-100 nm.

According to an embodiment of the present disclosure, the thickness of the resistive material layer may be 4-50 nm. The resistive switch material layers 107-1, 107-2 and 107-3 may only include resistive switch material, or may include a layer of resistive switch material and a layer of material with rectification properties. The resistive switch material can be selected from HfO ₂ , NiO, TiO ₂ , ZrO ₂ , ZnO, WO ₃ , Ta ₂ O ₅ , Al ₂ O ₃ , CeO ₂ , La ₂ O ₃ , Gd ₂ O ₃ and any combination thereof One of the formed groups. The material with rectifying properties can be doped polysilicon or other oxide semiconductors, such as CuO or ZnO.

FIG. 2 schematically shows a schematic diagram of a resistive variable memory 200 according to an embodiment of the present disclosure. As shown in FIG. 2 , the RRAM 200 includes 2*2*3=12 memory cells, which are shown by black dots in the figure. These memory cells, for example, may correspond to the resistive structures formed by the stacked structures 103-1 and 103-2, the comb-shaped metal layers 106-1 and 106-2 and the corresponding resistive material layers 107-1 and 107-2 in FIG. change unit. In FIG. 2, only 12 storage units are shown for clarity, but more or fewer storage units may be provided as required. The RRAM 200 further includes word lines WL1 and WL2 and bit lines BL1 , BL2 and BL3 . Word lines WL1 and WL2 are connected to corresponding memory cells through word line gate transistors WT1 and WT2 respectively. The bit line BL1 is connected to the corresponding memory cell through the bit line gate transistors BT1-1, BT1-2. The bit line BL2 is connected to the corresponding memory cell through the bit line gate transistors BT2-1, BT2-2. The bit line BL3 is connected to the corresponding memory cell through the bit line gate transistors BT3-1 and BT3-2. The gates of bit line pass transistors connected to different bit lines are connected to corresponding select lines. As shown in Figure 2, the gates of the bit line selection transistors BT1-1, BT2-1, BT3-1 are connected to the selection line SL1, and the gates of the bit line selection transistors BT1-2, BT2-2, BT3-2 Connect to select line SL2. For the convenience of description, the memory cells in the resistive variable memory 200 are numbered based on the numbers of the connected word line selection transistors and bit line selection transistors, that is, connected to the word line selection transistor WT1 and the bit line selection transistor BT1- The memory cell of 1 is denoted as SC111, the memory cell connected to the word line gate transistor WT1 and the bit line gate transistor BT1-2 is denoted as SC112, and so on. Correspondingly, the memory cell connected to word line pass transistor WT2 and bit line pass transistor BT3-2 is denoted SC232. In this way, the memory cells in the RRAM can be sequentially numbered as SC111, SC112, SC121, SC122, SC131, SC132, SC211, SC212, SC221, SC222, SC231, SC232. An exemplary memory cell SC221 is shown in a dotted circle in FIG. 2 .

According to an embodiment of the present disclosure, each storage unit may have the same structure as the storage unit 201 shown in FIG. 1 , for example. For the sake of brevity, only the part of FIG. 1 related to FIG. 2 will be described. However, based on the teachings of the present disclosure, similar arrangements can be made to the rest of FIG. 1 as desired. According to an embodiment of the present disclosure, each comb-shaped metal layer shown in FIG. 1 can be drawn out as a word line and connected to a word line gate transistor. For example, the comb-shaped metal layer 106-1 can be drawn out as a word line WL1 and connected to the word line gate transistor WT1. The comb metal layer 106-2 can be drawn out as a word line WL1 and connected to the word line gate transistor WT2. Each metal layer in each stack structure shown in FIG. 1 can be connected at one end to a bit line gate transistor, and to multiple bit line gate transistors connected to a metal layer having the same height with respect to the substrate surface The source is connected to the same bit line. For example, the source of the bit line gate transistor BT1-1 connected to the metal layer 104-1 in the stacked structure 103-1 and the metal layer at the same height as the metal layer 104-1 in the stacked structure 103-2 The source of the associated bit line pass transistor BT1-2 is connected to the bit line BL1. The bit line gate transistor BT connected to the metal layer 104-2 in the stack structure 103-1 and the bit line gate transistor connected to the metal layer at the same height as the metal layer 104-2 in the stack structure 103-2 The source of is connected to bit line BL2. The bit line gate transistor BT connected to the metal layer 104-3 in the stack structure 103-1 and the bit line gate transistor connected to the metal layer at the same height as the metal layer 104-3 in the stack structure 103-2 The source of is connected to bit line BL3. The gates of bit line pass transistors connected to metal layers in the same stack structure can be connected to the same select line. For example, bit line gate transistors BT1-1, BT2-1, BT3-1 connected to metal layers 104-1, 104-2, 104-3 in stack structure 103-1 may be connected to select SL1. The bit line gate transistors BT1-2, BT2-2, BT3-2 connected to the three metal layers in the stack structure 103-2 may be connected to the selection line SL2.

A method for operating the RRAM as shown in FIG. 2 according to an embodiment of the present disclosure will be described below with reference to FIGS. 3 and 4 . Operations on RRAM include erase/write process and read process.

FIG. 3 schematically shows a schematic diagram of erasing/writing operations on the resistive variable memory shown in FIG. 2 according to an embodiment of the present disclosure. The erasing process of the RRAM refers to RESET the device to a high-impedance state, and the writing process refers to SET the device to a low-impedance state. There is no difference between the RESET and SET processes except for the required applied voltage. FIG. 3 shows the voltage applied to each word line and bit line during the erase/write process. As shown in Figure 3, the memory cell to be erased/written is selected by selecting the word line, the bit line and the selection line, and the voltage value required for erasing (or writing) is applied to the selected memory cell to control the device. Erase (or write). The voltage applied to the unselected memory cells does not exceed half of the voltage required for erasing (or writing). By selecting a suitable resistive material, the memory cells will not be accidentally erased/written under the half-erased voltage. In this case, the array can correctly erase/write any selected memory cell without affecting the state of all other memory cells. For example, as shown in FIG. 3, if the erase/write operation is to be performed on the memory cell SC221, the erase/write voltage V _reset /V _set is applied to the word line WL2 connected to the memory cell SC221, and the bit line BL2 is grounded (GND ), and apply the turn-on voltage V _on to the selection line SL1. In this way, the voltage V _reset required for the erasing operation or the voltage V _set required for the writing operation is applied to the memory cell SC221 , thereby realizing the erasing/writing operation. For other memory cells, apply a voltage less than half of the erase/write voltage V _reset /V _set on the word line WL1 connected to it, and at the same time float the bit line and selection line connected to it (F), so that both ends of these memory cells The applied voltage does not exceed half of the voltage value required for erasing (or writing), so that no erasing/writing operation is performed on it. According to the erasing/writing method of the present disclosure, each storage unit can be accessed independently and randomly, and there is no need to connect a diode in series with each storage unit, which can avoid the problem of bypass interference.

FIG. 4 shows a schematic diagram of a read operation of the RRAM shown in FIG. 2 according to an embodiment of the present disclosure. The reading process of the RRAM is to apply a reading voltage to the memory cell to be read, and measure the current passing through the memory cell through a sense amplifier connected in series with the memory cell. Based on the measured current, it is judged whether the storage unit is in a high-resistance state or a low-resistance state, so as to determine the data value stored by the storage unit. As shown in FIG. 4, when performing a read operation, all the bit lines BL1-BL3 are grounded. Selecting a select line (SL1 in this example) and applying the turn-on voltage V _on required for the bit line pass transistors turns on all the bit line pass transistors controlled by the select line SL1. At the same time, one word line (in this example, WL2 ) is selected, the read voltage V _read is applied, and the other word lines are grounded (GND). In this way, the read voltage V _read is applied to all the memory cells SC211 , SC221 , SC231 between the selected selection line SL1 and the selected word line WL2 , while no voltage is applied to the unselected memory cells. Each bit line is connected to a sense amplifier, which can read the current passing through the corresponding selected memory cell to determine the data value stored in the memory cell. As shown in FIG. 4, bit lines BL1, BL2 and BL3 are connected to sense amplifiers SA1, SA2 and SA3, respectively. Sense amplifiers SA1, SA2, and SA3 sense current through memory cells SC211, SC221, and SC231, respectively, to determine data values stored therein. According to the reading method of the present disclosure, the data values stored in multiple storage units can be read simultaneously, thereby improving the reading efficiency.

The manufacturing method of the RRAM according to the embodiment of the present disclosure will be described below with reference to FIG. 5 . As shown in part (a) of FIG. 5 , a substrate isolation layer 102 is formed on the substrate 101 by deposition or thermal oxidation. The material of the substrate 101 can be Si, Ge or III-V compound (such as SiC, GaAs, InAs, InP, etc.). The material of the isolation layer 102 may be SiO ₂ or Si ₄ N ₃ , and the thickness may be 10-300 nm. Then, metal layers and isolation layers 104-1, 105-1, 104-2, 105-2, 104-3, and 105-3 are successively and alternately deposited. The thickness of each metal layer can be 5-100nm, and the material can be any one of TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir, Ni. The thickness of each isolation layer can be 5-300nm, and the material can be SiO ₂ or Si ₄ N ₃ . FIG. 5 only schematically shows three alternate metal layers and isolation layers, but more layers can be provided according to actual needs. Then, the alternating metal layers and isolation layers 104-1, 105-1, 104-2, 105-2, 104-3, and 105-3 are etched using a photolithographic etching technique, and the etching stops at the liner Bottom isolation layer 102. Three stacked structures 103-1, 103-2 and 103-3 are formed by etching. The width of each stacked structure may be 5-100 nm. Then, a resistive material layer 107 is deposited on the stacked structure and the substrate isolation layer. The resistive material layer may be formed using atomic layer deposition (ALD). The thickness of the resistive material layer may be 4-50nm, and may only include materials with resistive properties (such as metal oxides), or may include both materials with resistive properties and materials with rectifying properties. The material with resistive properties can be selected from HfO ₂ , NiO, TiO ₂ , ZrO ₂ , ZnO, WO ₃ , Ta ₂ O ₅ , Al ₂ O ₃ , CeO ₂ , La ₂ O ₃ , Gd ₂ O ₃ and One of the groups formed by any combination thereof. Materials with rectifying properties can be doped polysilicon and or other oxide semiconductors, such as CuO or ZnO. A metal layer 106 is then deposited over the structure. Metal layer 106 may be formed using physical vapor deposition (PVD). The metal layer 106 may be 50-1000 nm in size perpendicular to the substrate surface, and the material may be any one of TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir, Ni. Using photolithography technology or etching technology, the metal layer 106 and the resistive material layer are etched with the plurality of stacked structures of the substrate isolation layer as a stop layer to form comb-shaped metal layers 106-1, 106-2 and 106- 3 and corresponding resistive material layers 107-1, 107-2, 107-3. The length direction of the comb-shaped metal layers 106-1, 106-2 and 106-3 is perpendicular to the length direction of the stacked structures 103-1, 103-2 and 103-3. The dimension of each comb-shaped metal layer 106-1, 106-2 and 106-3 along the length direction of the stacked structure may be 10-100 nm. In this way, the storage array 100 shown in FIG. 2 is formed. Next, prepare word lines, bit lines, select lines, word line gate transistors, bit line gate transistors, etc., as well as lead wires, passivation, packaging and other subsequent conventional semiconductor processing processes, so as to form resistors according to embodiments of the present disclosure. Variable memory.

A specific example of fabricating a memory array according to an embodiment of the present disclosure is described below. This example could include the following steps:

1. Thermally oxidize a _SiO2 layer with a thickness of 10-300nm on a silicon substrate as a substrate isolation layer.

2. Deposit a 5-100 nm TiN layer on the above structure by physical vapor deposition (PVD).

3. A 5-300nm SiO ₂ layer is deposited on the above structure by chemical vapor deposition (CVD).

4. Repeat steps 2 and 3 multiple times to form a stack of TiN layer and _SiO2 layer.

5. Using the substrate isolation layer as a stop layer, the above-mentioned laminated layers are etched by photolithography and etching techniques to obtain multiple laminated structures with a width of 5-100 nm.

6. Deposit a resistive material layer HfO ₂ on the above structure by atomic layer deposition (ALD), with a thickness of 4-50 nm.

7. Deposit a TiN metal layer with a thickness of 50-2000nm on the above structure by physical vapor deposition PVD method.

8. Etching the TiN metal layer by photolithography and etching techniques to obtain multiple comb-shaped metal layers with a width of 10-100 nm.

9. Preparation of gate transistors, and conventional processes for subsequent semiconductor processing such as leads, passivation, and packaging.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Various changes in form and detail were made. The scope of the present disclosure is not limited to the examples described above, and the spirit of the present disclosure should be determined by the appended claims and their equivalents.

Claims (16)

1. a resistance-variable storing device, including storage array, described storage array includes:

Substrate；

Substrate sealing coat, is arranged on substrate；

Multiple laminated construction, are arranged on substrate sealing coat；

Multiple comb metal layers, the length direction along described laminated construction be arranged on substrate sealing coat and On the plurality of laminated construction, the comb of each comb metal layer is clipped between adjacent laminated construction, Described comb metal layer includes the comb of solid cylindrical and the crossbeam at the top of each comb of connection；Many Individual resistance change material layer, each resistance change material layer is formed at a corresponding comb metal layer and described lining Between end sealing coat and a corresponding comb metal layer and the plurality of laminated construction it Between；

A plurality of wordline, by gating crystal via a wordline respectively by the plurality of comb metal layer Pipe extracts the described a plurality of wordline of formation；

Multiple bit lines, each metal level in each laminated construction at one end with a bit line strobe crystalline substance Body pipe connects, and has, with relative to substrate surface, multiple bit lines that mutually level metal level is connected The source electrode of gating transistor is connected to a corresponding bit line；And

A plurality of selection line, the bit line select transistor being connected with the metal level in same laminated construction Grid is connected to a corresponding selection line.

Resistance-variable storing device the most according to claim 1, wherein, each laminated construction includes The metal level being alternately stacked and sealing coat.

Resistance-variable storing device the most according to claim 1, wherein, the plurality of comb metal The length direction of layer intersects with the length direction of laminated construction.

Resistance-variable storing device the most according to claim 1, wherein, resistance change material layer only includes Resistive material, or include one layer of resistive material and one layer of material with rectification characteristic.

Resistance-variable storing device the most according to claim 1, wherein, substrate sealing coat includes SiO₂ Or Si₄N₃, the thickness of substrate sealing coat is 10-300nm.

Resistance-variable storing device the most according to claim 1, wherein:

Each metal level in laminated construction include TiN, TaN, Pt, Au, W, Cu, Al, Any one in Ti, Ir and Ni, the thickness of described each metal level is 5-100nm；And

Each sealing coat in laminated construction includes SiO₂Or Si₄N₃, the thickness of described each sealing coat Degree is 5-300nm.

Resistance-variable storing device the most according to claim 1, wherein:

Comb metal layer includes in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni Any one；And

It is 50-2000nm that each comb metal layer edge is perpendicular to the height of substrate surface, ties along lamination The thickness of the length direction of structure is 5-100nm.

Resistance-variable storing device the most according to claim 4, wherein:

The thickness of resistance change material layer is 4-50nm；

Resistive material includes selected from HfO₂、NiO、TiO₂、ZrO₂、ZnO、WO₃、Ta₂O₅、 Al₂O₃、CeO₂、La₂O₃、Gd₂O₃And the one in the group of combination in any composition；And

The material with rectification characteristic includes DOPOS doped polycrystalline silicon or other oxide semiconductors.

9. the method operating resistance-variable storing device according to claim 1, wherein, institute State resistance-variable storing device to include:

Multiple memory element, each memory element includes a metal level in laminated construction, corresponding A comb metal layer and resistance change material layer therebetween, described comb metal layer includes solid The crossbeam at the top of the comb of column and each comb of connection；

A plurality of wordline, is connected to the memory element of same comb metal layer via a wordline gating crystalline substance Body pipe is connected to a corresponding wordline；

Multiple bit lines, is connected many with having mutually level memory element relative to substrate surface The source electrode of individual bit line select transistor is connected to a corresponding bit line；And

A plurality of selection line, the bit line select transistor being connected with the memory element in same laminated construction Grid be connected to a corresponding selection line,

Described method includes:

By selecting wordline, bit line and selection line to carry out select storage unit；And

By applying erasing voltage, write voltage or read voltage to selected memory element, divide Do not realize erasing, write or read operation.

Method the most according to claim 9, by selecting wordline, bit line and selection line Select storage unit includes:

When carrying out erasing operation: for memory element to be selected, wordline is applied erasing voltage, By bit line, and to selecting line to apply cut-in voltage；And for other memory element, at word Line applies the voltage less than erasing voltage half, and bit line and selection line are floating simultaneously；

When carrying out write operation: for memory element to be selected, wordline is applied write voltage, By bit line, and to selecting line to apply cut-in voltage；And for other memory element, at word Line applies the voltage less than write voltage half, and bit line and selection line are floating simultaneously；And

When being read, by all of bit line, to memory element phase to be read The selection line of association applies cut-in voltage, applies the wordline being associated with memory element to be read Read voltage, by other wordline ground connection.

11. 1 kinds of methods manufacturing resistance-variable storing device, including:

Substrate is formed substrate sealing coat；

Substrate sealing coat is alternatively formed multiple metal level and multiple sealing coat；

Using substrate sealing coat as stop-layer, etch the plurality of metal level and multiple sealing coat, with Form multiple laminated construction arranged in parallel；

The plurality of laminated construction and substrate sealing coat deposit resistive material；

Resistance change material layer forms another metal level；

Using substrate sealing coat and the plurality of laminated construction as stop-layer, etching another metal described Layer and described resistive material, to form multiple comb metal layer and corresponding multiple resistance change material layer, Described comb metal layer includes the comb of solid cylindrical and the crossbeam at the top of each comb of connection；

Form a plurality of wordline, by being gated via a wordline respectively by the plurality of comb metal layer Transistor extracts the described a plurality of wordline of formation；

Forming multiple bit lines, each metal level in each laminated construction at one end selects with a bit line Logical transistor connects, multiple with have that mutually level metal level is connected relative to substrate surface The source electrode of bit line select transistor is connected to a corresponding bit line；And

Form a plurality of selection line, the bit line strobe crystal being connected with the metal level in same laminated construction The grid of pipe is connected to a corresponding selection line.

12. methods according to claim 11, also include:

Deposit and etch the material with rectification characteristic, thus the plurality of resistance change material layer includes The material of described rectification characteristic.

13. methods according to claim 11, wherein, substrate sealing coat includes SiO₂Or Si₄N₃, the thickness of substrate sealing coat is 10-300nm.

14. methods according to claim 11, wherein:

Each metal level in laminated construction include TiN, TaN, Pt, Au, W, Cu, Al, Any one in Ti, Ir and Ni, the thickness of described each metal level is 5-100nm；And

Each sealing coat in laminated construction includes SiO₂Or Si₄N₃, the thickness of described each sealing coat Degree is 5-300nm.

15. methods according to claim 11, wherein:

Comb metal layer includes in TiN, TaN, Pt, Au, W, Cu, Al, Ti, Ir and Ni Any one；And

It is 50-2000nm that each comb metal layer edge is perpendicular to the height of substrate surface, ties along lamination The thickness of the length direction of structure is 5-100nm.

16. methods according to claim 12, wherein:

The thickness of resistance change material layer is 4-50nm；

Resistive material includes selected from HfO₂、NiO、TiO₂、ZrO₂、ZnO、WO₃、Ta₂O₅、 Al₂O₃、CeO₂、La₂O₃、Gd₂O₃And the one in the group of combination in any composition；And

The material with rectification characteristic includes DOPOS doped polycrystalline silicon or other oxide semiconductors.