KR102507303B1 - Memory device - Google Patents

Abstract

The memory device includes a first conductive line extending in a first direction, a second conductive line extending in a second direction crossing the first direction on the first conductive line, and extending in the first direction on the second conductive line. a third conductive line; a first memory cell disposed at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer; and a second memory cell disposed at an intersection of the third conductive line and the second conductive line and including a second selection element layer and a second variable resistance layer; A first height along a third direction perpendicular to the first and second directions is different from a second height along the third direction of the second selection element layer.

Description

Memory device {Memory device}

The technical idea of the present invention relates to a memory device, and more particularly, to a memory device having a cross point array structure.

[0003] With the trend of light, thin and miniaturized electronic products, there is an increasing demand for high integration of semiconductor devices. In addition, a memory device having a three-dimensional cross-point structure in which a memory cell is disposed at an intersection between two electrodes crossing each other has been proposed. However, as down-scaling of the memory device of the cross-point structure is continuously required, the thickness of all layers constituting the memory device needs to be reduced, and thus exposure to high temperatures during the manufacturing process of the memory device. As a result, the layers are easily deteriorated or damaged, and electrical characteristics of the memory device may be deteriorated.

A technical problem to be achieved by the technical idea of the present invention is to provide a cross point array type memory device having uniform operating characteristics.

Memory device according to the technical idea of the present invention for achieving the above technical problem, a plurality of first direction extending in a first direction parallel to the upper surface of the substrate on a substrate and separated from each other in a second direction crossing the first direction 1 conductive line; a plurality of second conductive lines extending in the second direction on the plurality of first conductive lines and separated from each other in the first direction; a plurality of third conductive lines extending in the first direction on the plurality of second conductive lines and separated from each other in the second direction; a plurality of first memory cells disposed at intersections of the plurality of first conductive lines and the plurality of second conductive lines, each including a first selection element layer and a first variable resistance layer; and a plurality of second memory cells disposed at intersections of the plurality of third conductive lines and the plurality of second conductive lines, each including a second selection element layer and a second variable resistance layer; A first height of the first selection element layer along a third direction perpendicular to the first and second directions is different from a second height of the second selection element layer along the third direction.

In example embodiments, a difference between a first threshold voltage of the first selection device layer and a second threshold voltage of the second selection device layer may be less than 10% of the first threshold voltage.

In example embodiments, a difference between a threshold voltage of the first selection device layer and a threshold voltage of the second selection device layer may be less than 0.5 V.

In example embodiments, the level of the threshold voltage of the first selection element layer may be 90% to 110% of the level of the threshold voltage of the second selection element layer.

In example embodiments, the first height of the first selection element layer may be greater than the second height of the second selection element layer.

In example embodiments, a word line selection voltage is applied to one of the plurality of first conductive lines or one of the plurality of third conductive lines, and a cut-off voltage is applied to the plurality of second conductive lines. and the word line selection voltage may be greater than the cut-off voltage.

In example embodiments, the second height of the second selection element layer may be 50% to 90% of the first height of the first selection element layer.

In example embodiments, the first height of the first selection element layer may be smaller than the second height of the second selection element layer.

In example embodiments, the first height of the first selection element layer may be 50% to 90% of the second height of the second selection element layer.

In example embodiments, a word line selection voltage is applied to one of the plurality of first conductive lines or one of the plurality of third conductive lines, and a cut-off voltage is applied to the plurality of second conductive lines. and the word line selection voltage may be smaller than the cut-off voltage.

In example embodiments, the first selection device layer and the second selection device layer may have ovonic threshold switching characteristics.

In example embodiments, each of the plurality of first memory cells further includes a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of first conductive lines, and Each of the second memory cells may further include a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of third conductive lines.

In example embodiments, each of the plurality of first memory cells may further include a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of second conductive lines, and Each of the second memory cells may further include a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of second conductive lines.

A memory device according to the technical spirit of the present invention for achieving the above technical problem includes a plurality of first conductive lines extending in a first direction parallel to an upper surface of the substrate on a substrate; a plurality of second conductive lines extending on the plurality of first conductive lines in a second direction different from the first direction and parallel to the upper surface of the substrate; a plurality of third conductive lines extending in the first direction on the plurality of second conductive lines; The first selection element layers are disposed at intersections of the plurality of first conductive lines and the plurality of second conductive lines and are laminated at a difference ? m in a third direction perpendicular to the first and second directions. and a plurality of first memory cells including a first variable resistance layer; and second selection elements disposed at intersections of the plurality of third conductive lines and the plurality of second conductive lines, each stacked at a difference ? m in a third direction perpendicular to the first and second directions. and a plurality of second memory cells including a layer and a second variable resistance layer, wherein a thickness of the first selection element layer in the third direction is greater than a thickness of the second selection element layer in the third direction.

In example embodiments, the thickness of the second selection element layer may be 50 to 90% of the thickness of the first selection element layer.

In example embodiments, a difference between a threshold voltage of the first selection device layer and a threshold voltage of the second selection device layer may be less than 0.5 V.

In example embodiments, the thickness of the first selection device layer may be 10 to 500 nm, and the thickness of the second selection device layer may be 5 to 450 nm.

In example embodiments, the selection element layer and the variable resistance layer may include a chalcogen element.

In example embodiments, each of the plurality of first memory cells further includes a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of first conductive lines, and Each of the second memory cells may further include a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of third conductive lines.

In example embodiments, each of the plurality of first memory cells may further include a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of second conductive lines, and Each of the second memory cells may further include a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of second conductive lines.

According to the memory device according to the technical concept of the present invention, the magnitude of the first threshold voltage of the first selection element layer in the first memory cell and the magnitude of the second threshold voltage of the second selection element layer in the second memory cell The first selection element layer and the second selection element layer may have different vertical heights such that they are substantially the same. Since the difference between the threshold voltages of the first memory cell and the second memory cell is small, a sensing margin in a read/write operation of the memory device may be improved, and a read/write failure due to the small sensing margin may be prevented. . The memory device may have excellent reliability.

1 is an equivalent circuit diagram of a memory device according to example embodiments.
FIG. 2 is a perspective view illustrating a memory device according to example embodiments, and FIG. 3 is a cross-sectional view taken along lines AA′ and BB′ of FIG. 2 .
4 is a graph schematically illustrating a voltage-current curve of an OTS device exhibiting ovonic threshold switching (OTS) characteristics.
5A and 5B are schematic diagrams illustrating an operating method of a memory device having a cross-point stacked structure.
6 is a voltage-current graph when a positive voltage and a negative voltage are applied to the OTS device, respectively.
7 to 13 are cross-sectional views illustrating memory devices according to example embodiments.
FIG. 14 is a perspective view illustrating a memory device 200 according to example embodiments, and FIG. 15 is a cross-sectional view taken along line 2A-2A′ of FIG. 14 .
16A to 16I are cross-sectional views illustrating a manufacturing method of a memory device according to exemplary embodiments according to a process sequence.
Fig. 17 is a block configuration diagram of a memory device according to an exemplary embodiment.
18 is a block diagram of an electronic system according to example embodiments.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various forms and various changes may be applied. However, the description of the present embodiments is provided to complete the disclosure of the present invention, and to completely inform those skilled in the art of the scope of the invention to which the present invention belongs. In the accompanying drawings, the size of the components is enlarged from the actual size for convenience of description, and the ratio of each component may be exaggerated or reduced.

It should be understood that when an element is described as being “on” or “adjacent to” another element, it may be in direct contact with or connected to the other element, but another element may exist in the middle. something to do. On the other hand, when a component is described as being “directly on” or “directly in contact with” another component, it may be understood that another component does not exist in the middle. Other expressions describing the relationship between components, such as "between" and "directly between" can be interpreted similarly.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may only be used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present invention.

Singular expressions include plural expressions unless the context clearly dictates otherwise. The terms "include" or "has" are used to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, and includes one or more other features or numbers, It can be interpreted that steps, actions, components, parts, or combinations thereof may be added.

Terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those skilled in the art unless otherwise defined.

1 is an equivalent circuit diagram of a memory device 100 according to example embodiments.

Referring to FIG. 1 , the memory device 100 includes lower word lines WL1 and WL2, upper word lines W21 and WL22, common bit lines (BL1, BL2, BL3, and BL4), and a first memory cell MC1. ), and a second memory cell MC2.

The lower word lines WL1 and WL2 extend along a first direction (ie, the X direction in FIG. 1 ) and are spaced apart in a second direction perpendicular to the first direction (ie, the Y direction in FIG. 1 ), and the upper word line (WL21, W22) are spaced apart in a third direction perpendicular to the first direction (ie, Z direction in FIG. 1) on the lower word lines (WL11, WL12), extend along the first direction, and are spaced apart from each other in the second direction. It can be. Also, the common bit lines BL1 , BL2 , BL3 , and BL4 may be spaced apart from the upper word lines WL21 and WL22 and the lower word lines WL11 and WL12 in a third direction and may extend along the second direction. The common bit lines BL1 , BL2 , BL3 , and BL4 may be spaced apart from each other in the first direction.

The first and second memory cells MC1 and MC2 are formed between common bit lines BL1 , BL2 , BL3 , and BL4 and lower word lines WL11 and WL12 and common bit lines BL1 , BL2 , BL3 , and BL4 and the upper word lines WL21 and WL22, respectively. Specifically, the first memory cell MC1 may be disposed at an intersection of the common bit lines BL1, BL2, BL3, and BL4 and the lower word lines WL11 and WL12, and may include a variable resistance layer ME for storing information. and a selection element (SW) for selecting a memory cell. In addition, the second memory cell MC2 may be disposed at an intersection of the common bit lines BL1, BL2, BL3, and BL4 and the upper word lines WL21 and WL22, and may include a variable resistance layer ME for storing information. and a selection element (SW) for selecting a memory cell. Meanwhile, the selection element SW may also be referred to as a switching element layer or an access element layer.

The first memory cell MC1 and the second memory cell MC2 may be arranged to have the same structure in the third direction. As exemplarily shown in FIG. 1 , in the first memory cell MC1 disposed between the lower word line WL11 and the common bit line BL1, the variable resistance layer ME includes the common bit line BL1 , the selection element SW is electrically connected to the lower word line WL11, and the variable resistance layer ME and the selection element SW may be connected in series. In addition, in the second memory cell MC2 disposed between the upper word line WL21 and the common bit line BL1, the variable resistance layer ME is electrically connected to the upper word line WL21, and the selection element (SW) is electrically connected to the common bit line BL1, and the variable resistance layer ME and the selection element SW may be connected in series.

However, the technical spirit of the present invention is not limited thereto. Unlike that shown in FIG. 1 , the positions of the selection element SW and the variable resistance layer ME in each of the first memory cell MC1 and the second memory cell MC2 may be changed. For example, the first memory cell MC1 and the second memory cell MC2 may be disposed in a symmetrical structure about the common bit lines BL1 , BL2 , BL3 , and BL4 along the third direction. That is, in the first memory cell MC1, the variable resistance layer ME is connected to the lower word line WL11, the selection element SW is connected to the common bit lines BL1 BL2, BL3, and BL4, and the second memory In the cell MC2, the variable resistance layer ME is connected to the upper word lines WL21 and W22 and the selection element SW is connected to the common bit lines BL1, BL2, BL3 and BL4, thereby forming the common bit line BL1. ), the first memory cell MC1 and the second memory cell MC2 may be disposed symmetrically with each other.

Hereinafter, a method of driving the memory device 100 will be described.

For example, through the word lines WL11, WL12, WL21, and WL22 and the common bit lines BL1, BL2, BL3, and BL4, the variable resistance of the first memory cell MC1 or the second memory cell MC1 or MC2 When a voltage is applied to the layer ME, a current may flow through the variable resistance layer ME. For example, the variable resistance layer ME may include a phase change material layer capable of reversibly transitioning between a first state and a second state. However, the variable resistance layer ME is not limited thereto, and may include any variable resistance body whose resistance value varies according to an applied voltage. For example, the resistance of the variable resistance layer ME may reversibly transition between a first state and a second state according to a voltage applied to the variable resistance layer ME of the selected memory cells MC1 and MC2.

According to the resistance change of the variable resistance layer ME, digital information such as “0” or “1” is stored in the memory cells MC1 and MC2, and the digital information can be erased from the memory cells MC1 and MC2. do. For example, data can be written in the memory cells MC1 and MC2 in a high-resistance state “0” and a low-resistance state “1”. Here, writing from the high-resistance state “0” to the low-resistance state “1” may be referred to as a “set operation”, and writing from the low-resistance state “1” to the high-resistance state “0” may be referred to as a “reset operation”. can However, the memory cells MC1 and MC2 according to the embodiments of the present invention are not limited to the digital information of the high resistance state “0” and the low resistance state “1”, and can store various resistance states. .

Arbitrary memory cells MC1 and MC2 can be addressed by selecting word lines WL11, WL12, WL21, and WL22 and common bit lines BL1, BL2, BL3, and BL4, and word lines WL11, WL12, A predetermined signal is applied between the WL21 and WL22 and the common bit lines BL1, BL2, BL3, and BL4 to program the memory cells MC1 and MC2 and the common bit lines BL1, BL2, BL3, and BL4. Information according to the resistance value of the variable resistor constituting the corresponding memory cells MC1 and MC2 may be read by measuring the current value.

In the memory device 100 according to the present invention, the selection device SW of the first memory cell MC1 has substantially the same threshold voltage as that of the selection device SW of the second memory cell MC2. can For example, the difference between the magnitude of the first threshold voltage of the selection element SW of the first memory cell MC1 and the magnitude of the second threshold voltage of the selection element SW of the second memory cell MC2 is It may be less than 10% of the magnitude of the voltage. For example, the difference in magnitude of the threshold voltage may be less than about 0.5 V. Since the difference between the threshold voltages of the first memory cell MC1 and the second memory cell MC2 is small, the sensing margin in the read/write operation of the memory device 100 may be improved, and the sensing margin may be reduced due to the small sensing margin. Read/write failures can be prevented. The memory device 100 may have excellent reliability.

FIG. 2 is a perspective view illustrating a memory device 100 according to example embodiments, and FIG. 3 is a cross-sectional view taken along lines A-A' and B-B' of FIG. 2 .

2 and 3 , the memory device 100 includes a first conductive line layer 110L, a second conductive line layer 120L, a third conductive line layer 130L disposed on a substrate 101, A first memory cell layer MCL1 and a second memory cell layer MCL2 may be included.

As shown, an interlayer insulating film 105 may be disposed on the substrate 101 . The interlayer insulating layer 105 may be formed of an oxide such as silicon oxide or a nitride such as silicon nitride, and may serve to electrically separate the first conductive line layer 110L from the substrate 101 .

The first conductive line layer 110L may include a plurality of first conductive lines 110 extending in a first direction (X direction) and separated from each other in a second direction (Y). The second conductive line layer 120L is disposed on the first conductive line layer 110L, extends in a second direction (Y direction) perpendicular to the first direction, and is separated from each other in the first direction (X). It may include second conductive lines 120 . In addition, the third conductive line layer 130L is disposed on the second conductive line layer 120L, and extends in a first direction (X direction) and is separated from each other in a second direction (Y). s (130). Meanwhile, the plurality of third conductive lines 130 may be substantially the same as the plurality of first conductive lines 110 in an extension direction or arrangement structure.

In terms of driving the memory device, the plurality of first conductive lines 110 and the plurality of third conductive lines 130 are word lines (eg, word lines W11, W12, W21, and W22 of FIG. 1). )), and the plurality of second conductive lines 120 may correspond to bit lines (eg, bit lines BL1 , BL2 , BL3 , and Bl4 of FIG. 1 ). In addition, on the contrary, the plurality of first conductive lines 110 and the plurality of third conductive lines 130 correspond to bit lines (eg, bit lines BL1, BL2, BL3, and Bl4 of FIG. 1) And, the plurality of second conductive lines 120 may correspond to word lines (eg, word lines W11, W12, W21, and W22 of FIG. 1). When the plurality of first conductive lines 110 and the plurality of third conductive lines 130 correspond to word lines, the plurality of first conductive lines 110 are lower word lines, for example, FIG. 1 corresponds to the lower word lines W11 and W12, and the plurality of third conductive lines 130 correspond to the upper word lines (eg, the upper word lines W21 and W22 of FIG. 1), Since the plurality of second conductive lines 120 are shared by the lower word lines and the upper word lines, they may correspond to a common bit line.

The plurality of first conductive lines 110, the plurality of second conductive lines 120, and the plurality of third conductive lines 130 are each made of metal, conductive metal nitride, conductive metal oxide, or a combination thereof. can For example, the plurality of first conductive lines 110, the plurality of second conductive lines 120, and the plurality of third conductive lines 130 may be W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, an alloy thereof, or a combination thereof. In addition, the plurality of first conductive lines 110, the plurality of second conductive lines 120, and the plurality of third conductive lines 130 each include a metal film and a conductive barrier layer covering at least a portion of the metal film. can include The conductive barrier layer may be formed of, for example, Ti, TiN, Ta, TaN, or a combination thereof.

The first memory cell layer MCL1 may include a plurality of first memory cells 140 - 1 (MC1 in FIG. 1 ) arranged two-dimensionally apart from each other in the first and second directions. The second memory cell layer MCL2 may include a plurality of second memory cells 140 - 2 (MC2 in FIG. 1 ) spaced apart from each other in the first and second directions.

As shown in FIG. 2 , the plurality of first conductive lines 110 and the plurality of second conductive lines 120 cross each other, and the plurality of second conductive lines 120 and the plurality of third conductive lines cross each other. Fields 130 may cross each other. The first memory cells 140-1 include a plurality of first conductive lines 110 and a plurality of second conductive lines 120 between the first conductive line layer 110L and the second conductive line layer 120L. It can be placed in these intersecting parts. The second memory cells 140-2 include a plurality of second conductive lines 120 and a plurality of third conductive lines 130 between the second conductive line layer 120L and the third conductive line layer 130L. It can be placed in these intersecting parts.

The first memory cells 140 - 1 and the second memory cells 140 - 2 may be formed in a square pillar-shaped pillar structure. Of course, the structures of the first memory cells 140-1 and the second memory cells 140-2 are not limited to rectangular pillars. For example, the first memory cells 140-1 and the second memory cells 140-2 may have various pillar shapes, such as cylindrical pillars, elliptical pillars, and polygonal pillars. Also, depending on the formation method, the first memory cells 140 - 1 and the second memory cells 140 - 2 may have a structure in which the lower part is wider than the upper part or the upper part is wider than the lower part. In addition, the first memory cells 140 - 1 and the second memory cells 140 - 2 may be formed such that side surfaces are substantially vertical, so that there is little difference in area between the top and bottom. 2 and 3, the first memory cells 140-1 and the second memory cells 140-2 are illustrated with vertical sides in all of the drawings below, but this is for convenience of illustration. , the first memory cells 140-1 and the second memory cells 140-2 may have a structure in which a lower part is wider than an upper part or an upper part is wider than a lower part.

The first memory cells 140-1 include a first electrode layer 141-1, a first selection device layer 143-1, a second electrode layer 145-1, a third electrode layer 147-1, a first It includes a variable resistance layer 149-1 and a fourth electrode layer 148-1, and the second memory cells 140-2 include a fifth electrode layer 141-2 and a second selection element layer 143-2. , the sixth electrode layer 145-2, the seventh electrode layer 147-2, the second variable resistance layer 149-2, and the eighth electrode layer 148-2. Since the structures of the first memory cells 140-1 and the second memory cells 140-2 are substantially the same, for convenience of description, the first memory cells 140-1 will be described below.

In example embodiments, the variable resistance layer 149 - 1 (corresponding to ME in FIG. 1 ) may include a phase change material that reversibly changes between an amorphous state and a crystalline state according to a heating time. For example, the phase of the variable resistance layer 149-1 can be reversibly changed by Joule heat generated by a voltage applied to both ends of the variable resistance layer 149-1. A material whose resistance can be changed by a phase change may be included. Specifically, the phase change material may be in a high-resistance state in an amorphous state and may be in a low-resistance state in a crystalline state. By defining the high resistance state as “0” and the low resistance state as “1”, data can be stored in the variable resistance layer 149-1.

In some embodiments, the variable resistance layer 149 - 1 may include one or more elements (chalcogen elements) from a group of the periodic table and optionally, one or more chemical modifiers from a group IV or group. . For example, the variable resistance layer 149-1 may include Ge-Sb-Te. The chemical composition notation indicated by a hyphen (-) used herein indicates an element contained in a specific mixture or compound, and may indicate all chemical structures including the indicated element. For example, Ge-Sb-Te may be a material such as Ge ₂ Sb ₂ Te ₅ , Ge ₂ Sb ₂ Te ₇ , Ge ₁ Sb ₂ Te ₄ , or Ge ₁ Sb ₄ Te ₇ .

The variable resistance layer 149 - 1 may include various phase change materials in addition to the aforementioned Ge-Sb-Te. For example, the variable resistance layer 149-1 may be Ge-Te, Sb-Te, In-Se, Ga-Sb, In-Sb, As-Te, Al-Te, Bi-Sb-Te (BST), In-Sb-Te (IST), Ge-Sb-Te, Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te , In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te, Sn-Sb-Bi, Ge-Te-O, Te -Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb -Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn -Pd, and at least one of Ge-Te-Sn-Pt, In-Sn-Sb-Te, and As-Ge-Sb-Te, or a combination thereof.

Each element constituting the variable resistance layer 149-1 may have various chemical composition ratios (stoichiometry). The crystallization temperature, melting temperature, phase change rate according to crystallization energy, and data retention characteristics of the variable resistance layer 149 - 1 may be adjusted according to the chemical composition ratio of each element.

The variable resistance layer 149-1 may further include at least one impurity among carbon (C), nitrogen (N), silicon (Si), oxygen (O), bismuth (Bi), and tin (Sn). . The driving current of the memory device 100 may be changed by the impurities. Also, the variable resistance layer 149 - 1 may further include metal. For example, the variable resistance layer 149-1 may include aluminum (Al), gallium (Ga), zinc (Zn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt ( Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium ( At least one of Tl), lead (Pb), and polonium (Po) may be included. These metal materials may increase the electrical conductivity and thermal conductivity of the variable resistance layer 149 - 1 , and accordingly, increase the crystallization rate and increase the set rate. In addition, the metal materials may improve data retention characteristics of the variable resistance layer 149-1.

The variable resistance layer 149-1 may have a multilayer structure in which two or more layers having different physical properties are stacked. The number or thickness of the plurality of layers can be chosen freely. A barrier layer may be further formed between the plurality of layers. The barrier layer may serve to prevent material diffusion between the plurality of layers. That is, the barrier layer may reduce diffusion of a preceding layer when forming a subsequent layer among a plurality of layers.

Also, the variable resistance layer 149 - 1 may have a super-lattice structure in which a plurality of layers including different materials are alternately stacked. For example, the variable resistance layer 149 - 1 may include a structure in which a first layer made of Ge-Te and a second layer made of Sb-Te are alternately stacked. However, the materials of the first layer and the second layer are not limited to Ge-Te and Sb-Te, and may include various materials described above, respectively.

Although a phase change material has been exemplified as the variable resistance layer 149 - 1 above, the technical spirit of the present invention is not limited thereto. The variable resistance layer 149 - 1 of the memory device 100 may include various materials having resistance change characteristics.

In some embodiments, when the variable resistance layer 149 - 1 includes a transition metal oxide, the memory device 100 may be a Resistive RAM (ReRAM). In the variable resistance layer 149-1 including the transition metal oxide, at least one electrical path may be created or destroyed in the variable resistance layer 149-1 by a program operation. When the electrical passage is created, the variable resistance layer 149-1 may have a low resistance value, and when the electrical passage disappears, the variable resistance layer 149-1 may have a high resistance value. The memory device 100 may store data by using the difference in resistance of the variable resistance layer 149-1.

When the variable resistance layer 149-1 is made of a transition metal oxide, the transition metal oxide is selected from Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, or Cr. It may contain at least one metal. For example, the transition metal oxide may be Ta ₂ O _5-x , ZrO _{2 -x} , TiO _{2 -x} , HfO _{2 -x} , MnO _{2- x} , Y ₂ O _{3 -x} , NiO _{1 -y} , Nb ₂ O _{5 -x} , Cu _{O1 -y} , or Fe ₂ O _{3 -x} may be formed of a single layer or multiple layers made of at least one material selected. In the materials exemplified above, x and y may be selected within the ranges of 0≤x≤1.5 and 0≤y≤0.5, respectively, but are not limited thereto.

In other embodiments, when the variable resistance layer 149-1 has a magnetic tunnel junction (MTJ) structure including two electrodes made of a magnetic material and a dielectric material interposed between the two magnetic electrodes, the memory element ( 100) may be MRAM (Magnetic RAM).

Each of the two electrodes may be a magnetization-fixed layer and a magnetization-free layer, and the dielectric interposed therebetween may be a tunnel barrier layer. The magnetization pinned layer may have a magnetization direction fixed in one direction, and the magnetization free layer may have a magnetization direction changeable so as to be parallel or antiparallel to the magnetization direction of the magnetization pinned layer. Magnetization directions of the magnetization-fixed layer and the magnetization-free layer may be parallel to one surface of the tunnel barrier layer, but are not limited thereto. Magnetization directions of the magnetization pinned layer and the magnetization free layer may be perpendicular to one surface of the tunnel barrier layer.

When the magnetization direction of the free magnetization layer is parallel to the magnetization direction of the fixed magnetization layer, the variable resistance layer 149 - 1 may have a first resistance value. Meanwhile, when the magnetization direction of the free magnetization layer is antiparallel to the magnetization direction of the magnetization pinned layer, the variable resistance layer 149 - 1 may have a second resistance value. The memory device 100 may store data by using the difference in resistance value. A magnetization direction of the free magnetization layer may be changed by spin torque of electrons in a program current.

The magnetization-fixed layer and the magnetization-free layer may include a magnetic material. In this case, the magnetization-fixed layer may further include an antiferromagnetic material for fixing a magnetization direction of the ferromagnetic material in the magnetization-fixed layer. The tunnel barrier may be made of an oxide of any one material selected from Mg, Ti, Al, MgZn, and MgB, but is not limited to the above example.

The selection element layer 143-1 (corresponding to SW in FIG. 1) may be a current control layer capable of controlling the flow of current. The selection element layer 143-1 may include a material layer whose resistance may change according to the magnitude of a voltage applied across the selection element layer 143-1. For example, the selection element layer 143-1 may include a material layer having ovonic threshold switching (OTS) characteristics. Briefly explaining the function of the selection element layer 143-1 based on the OTS material layer, when a voltage smaller than the threshold voltage is applied to the selection element layer 143-1, the selection element layer 143-1 generates a current maintains a high resistance state in which almost no flows, and when a voltage greater than a threshold voltage is applied to the selection element layer 143-1, it becomes a low resistance state and current begins to flow. In addition, when the current flowing through the selection element layer 143-1 becomes smaller than the holding current, the selection element layer 143-1 may change to a high resistance state. Meanwhile, the ovonic threshold switching characteristics of the selection element layer 143-1 will be described later with reference to FIG. 4 in detail.

The selection device layer 143-1 may include a chalcogenide material as an OTS material layer. Representative chalcocenide materials may include one or more elements from groups of the periodic table (chalcogen elements) and optionally one or more chemical modifiers from groups III, IV or V. Sulfur (S), selenium (Se), and tellurium (Te) are the most common chalcogen elements that can be included in the selection element layer 143-1. Chalcogen elements are characterized by divalent bonding and the presence of a lone pair electron. Divalent bonds combine chalcogen elements to form chalcogenide materials, leading to the formation of chain and ring structures, and lone pairs of electrons provide an electron source to form conductive filaments. For example, aluminum (Al), gallium (Ga), indium (In), germanium (Ge), tin (Sn), silicon (Si), phosphorus (P), arsenic (As), and antimony (Sb). The valent and tetravalent modifiers determine the structural rigidity of the chalcogenide material by entering the chain and ring structures of the chalcogen element, and their ability to undergo crystallization or other structural rearrangements results in a phase change of the chalcogenide material with the switching material. classified as a substance.

In some embodiments, the selection device layer 143-1 may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), indium (In), or a combination of these elements. can For example, the selection element layer 143-1 includes silicon (Si) at a concentration of about 14%, tellurium (Te) at a concentration of about 39%, arsenic (As) at a concentration of about 37%, and low concentration of about 9%. It may include munium (Ge), and indium (In) at a concentration of about 1%. Here, the percentage ratio is an atomic percentage ratio in which the atomic constituents are 100% in total, and the same applies below.

In some embodiments, the selection element layer 143-1 may be formed of silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), or these Can contain any combination of elements. For example, the selection element layer 143-1 includes silicon (Si) at a concentration of about 5%, tellurium (Te) at a concentration of about 34%, arsenic (As) at a concentration of about 28%, and low concentration of about 11%. It may include munium (Ge), sulfur (S) at a concentration of about 21%, and selenium (Se) at a concentration of about 1%.

In some embodiments, the selection element layer 143-1 is made of tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), antimony (Sb), or these Can contain any combination of elements. For example, the selection element 134 includes tellerium (Te) at a concentration of about 21%, arsenic (As) at a concentration of about 10%, germanium (Ge) at a concentration of about 15%, and sulfur (S) at a concentration of about 2%. ), selenium (Se) at a concentration of about 50%, and antimony (Sb) at a concentration of about 2%.

Meanwhile, in the memory device 100 of this embodiment, the selection device layer 143-1 is not limited to the OTS material layer. For example, the selection device layer 143-1 is not limited to the OTS material layer, and may include various material layers capable of selecting a device. For example, the selection element layer 143-1 may include a diode, a tunnel junction, a PNP diode, a BJT, or a mixed ionic-electronic conduction (MIEC).

The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 are layers functioning as current passages and may be formed of a conductive material. there is. For example, each of the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may be a metal, a conductive metal nitride, a conductive metal oxide, or It may consist of a combination of these. For example, each of the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may include a TiN film, but is not limited thereto. no. In some embodiments, the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 are each made of a metal or conductive metal nitride. It may include a conductive layer and at least one conductive barrier layer covering at least a portion of the conductive layer. The conductive barrier layer may be made of metal oxide, metal nitride, or a combination thereof, but is not limited thereto.

In example embodiments, the third electrode layer 147-1 or the fourth electrode layer 148-1 in contact with the variable resistance layer 149-1 causes the variable resistance layer 149-1 to undergo a phase change. It may contain a conductive material capable of generating sufficient heat. For example, the third electrode layer 147-1 or the fourth electrode layer 148-1 may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof, or a nitride thereof, or a carbon-based conductive material. there is. However, the material of the third electrode layer 147-1 or the fourth electrode layer 148-1 is not limited to these materials.

In example embodiments, a heating electrode layer is provided between the variable resistance layer 149-1 and the fourth electrode layer 148-1 or between the variable resistance layer 149-1 and the third electrode layer 147-1. (not shown) may be further interposed. The heating electrode layer may include a conductive material capable of generating enough heat to change the phase of the variable resistance layer 149-1. For example, the heating electrode layer may include TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, It may be made of a high melting point metal such as TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof, or a nitride thereof, or a carbon-based conductive material. However, the material of the heating electrode layer is not limited to these materials.

2 and 3, the variable resistance layer 149-1 is disposed on the selection element layer 143-1 with the second electrode layer 145-1 and the third electrode layer 147-1 interposed therebetween. Although illustrated as an example, the technical spirit of the present invention is not limited thereto. Unlike those shown in FIGS. 2 and 3 , the selection element layer 143-1 is formed on the variable resistance layer 149-1 with the second electrode layer 145-1 and the third electrode layer 147-1 interposed therebetween. may be placed in The variable resistance layer 149-1 may be disposed between the first electrode layer 141-1 and the second electrode layer 145-1. In this case, the first electrode layer 141-1 and the second electrode layer 145-1 in contact with the variable resistance layer 149-1 generate enough heat to change the phase of the variable resistance layer 149-1. It may contain a conductive material that can be made. In addition, the heating electrode layer may be further interposed between the variable resistance layer 149-1 and the first electrode layer 141-1 or between the variable resistance layer 149-1 and the second electrode layer 145-1. there is.

The first electrode layer 141-1 and the fourth electrode layer 148-1 may be selectively formed. In other words, the first electrode layer 141-1 and the fourth electrode layer 148-1 may be omitted. However, in order to prevent contamination or contact failure that may occur as the selection element layer 143-1 and/or the variable resistance layer 149-1 directly contact the conductive lines, the first electrode layer 141-1 ) and the fourth electrode layer 148-1 may be disposed between the conductive lines and the selection element layer 143-1 or the variable resistance layer 149-1.

At least one of the second electrode layer 145-1 and the third electrode layer 147-1 must be provided between the selection element layer 143-1 and the variable resistance layer 149-1. In general, when the selection device layer 143-1 is based on OTS characteristics, the selection device layer 143-1 may include an amorphous chalcogenide material. However, the thickness of the variable resistance layer 149-1, the selection device layer 143-1, the second electrode layer 145-1, and the third electrode layer 147-1 according to the downscaling tendency of the memory device 100, The width and the distance between them may be reduced. Therefore, in the driving process of the memory device 100, when the heating electrode layer (or the third electrode layer 147-1 when the heating electrode layer is not formed) generates heat to change the phase of the variable resistance layer 149-1 The heat generation may also affect the selection element layer 143-1 disposed adjacent thereto. For example, deterioration and damage of the selection element layer 143-1 such as partial crystallization of the selection element layer 143-1 by heat from the adjacent heating electrode layer may occur. Therefore, at least one of the second electrode layer 145-1 and the third electrode layer 147-1 is essentially provided between the selection element layer 143-1 and the variable resistance layer 149-1, and the selection element layer ( 143-1) can be prevented from deterioration and damage.

In addition, according to the material of the first to fourth electrode layers 141-1, 145-1, 147-1, and 148-1 and/or the arrangement of the heating electrode layers, the first to fourth electrode layers 141-1, 145-1 1, 147-1, 148-1) Each thickness may be variously changed. For example, when the heating electrode layer is arranged between the third electrode layer 147-1 and the variable resistance layer 149-1, heat from the heating electrode layer is not transferred to the selection element layer 143-1. The third electrode layer 147-1 and the second electrode layer 145-1 may be formed thickly. If the heating electrode layer is not formed and the third electrode layer 147-1 is formed to include a conductive material capable of generating enough heat to phase change the variable resistance layer 149-1, the third The second electrode layer 145-1 may be formed thick so that heat from the electrode layer 147-1 is not transmitted to the selection element layer 143-1. For example, the second electrode layer 145-1 and the third electrode layer 147-1 may have a thickness of about 10 to 100 nm. However, the thicknesses of the second electrode layer 145-1 and the third electrode layer 147-1 are not limited to the above values. In addition, the second electrode layer 145-1 or the third electrode layer 147-1 may include at least one thermal barrier layer for a heat blocking function. When the second electrode layer 145-1 or the third electrode layer 147-1 includes two or more thermal barrier layers, the second electrode layer 145-1 or the third electrode layer 147-1 is a thermal barrier It may have a structure in which layers and electrode material layers are alternately stacked.

A first insulating layer 162 - 1 may be disposed between the plurality of first conductive lines 110 . A first insulating layer 162 - 1 and a third insulating layer 163 may be disposed between the first memory cells 140 - 1 of the first memory cell layer MCL1 . Specifically, the first insulating layer 162-1 is disposed between the first memory cells 140-1 disposed along the second direction (Y direction in FIG. 2), and the first insulating layer 162-1 is disposed in the first direction (X direction in FIG. 2). A third insulating layer 163 may be disposed between the first memory cells 140 - 1 disposed along ). Also, the third insulating layer 163 may be disposed between the second conductive lines 120 . A second insulating layer 162-2 is formed between the second memory cells 140-2 disposed in the second direction of the second memory cell layer MCL2 and between the third conductive lines 130 disposed in the second direction. can be placed. The first to third insulating layers 162-1, 162-2, and 163 may be formed of an insulating layer of the same material or at least one of them may be formed of an insulating layer of a different material. The first to third insulating layers 162-1, 162-2, and 163 are formed of, for example, oxide or nitride dielectric materials, and may function to electrically separate elements of each layer from each other. Meanwhile, air spaces (not shown) may be formed in place of at least one of the first to third insulating layers 162-1, 162-2, and 163. When air spaces are formed, an insulating liner having a predetermined thickness between the air spaces and the first memory cells 140-1 and/or between the air spaces and the second memory cells 140-2 ( not shown) may be formed.

As exemplarily shown in FIG. 3 , the first selection element layer 143-1 of the first memory cell 140-1 has a first height (or thickness) along the third direction (Z direction in FIG. 2). )(H1), and the second selection device layer 143-2 of the second memory cell 140-2 has a second height (or thickness) smaller than the first height H1 along the third direction. ) (H2). In example embodiments, the first height H1 of the first selection device layer 143-1 may be 10 to 500 nm, and the second height H2 of the second selection device layer 143-2 ) may be 5 to 450 nm. However, the technical spirit of the present invention is not limited thereto.

In example embodiments, the second height H2 of the second selection element layer 143-2 is about 50% to 90% of the first height H1 of the first selection element layer 143-1. can be However, the technical spirit of the present invention is not limited thereto.

The first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 are The level of the threshold voltage (V _T1 ) and the level of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 may be adjusted to have substantially the same value.

In example embodiments, the first height H1 of the first selection device layer 143-1 and the second height H2 of the second selection device layer 143-2 are the first selection device layer ( The difference between the level of the first threshold voltage (V _T1 ) of 143-1 and the level of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 may be adjusted to be 0.5 V or less. For example, the level of the second threshold voltage (V _T2 ) of the second selection element layer 143-2 is 0.5V greater than the level of the first threshold voltage (V _T1 ) of the first selection element layer 143-1. can be smaller Unlike this, the level of the second threshold voltage (V _T2 ) of the second selection element layer 143-2 is 0.5V higher than the level of the first threshold voltage (V _T1 ) of the first selection element layer 143-1. may be large

In example embodiments, the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 are the second selection element layer ( 143-2) is adjusted so that the magnitude of the second threshold voltage (V _T2 ) is in the range of about 80% to about 120% of the magnitude of the first threshold voltage (V _T1 ) of the first selection device layer 143-1. can For example, the magnitude of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 is about 90% of the magnitude of the first threshold voltage (V _T1 ) of the first selection device layer 143-1. % to about 110%.

The magnitude of the second threshold voltage (V _T2 ) of the second selection element layer 143-2 is about 80% to about 120% of the magnitude of the first threshold voltage (V _T1 ) of the first selection element layer 143-1. In the case of % range, the difference in electrical characteristics between the first memory cell MC1 and the second memory cell MC2 is reduced, so that a sensing margin for a read/write operation of the memory device 100 may be improved.

Hereinafter, the relationship between the threshold voltage and electrical characteristics of the selection device layers 143-1 and 143-2 having ovonic threshold switching (OTS) characteristics will be described in detail with reference to FIGS. 4 to 6.

4 is a graph schematically illustrating a voltage-current curve 40 of an OTS device exhibiting ovonic threshold switching (OTS) characteristics. 4 schematically shows a current flowing through the OTS device according to a voltage applied across both ends of the OTS device having ovonic threshold switching (OTS) characteristics.

Referring to FIG. 4 , a first curve 41 represents a voltage-current relationship in a state in which current does not flow through the OTS device. Here, the OTS element acts as a switching element having a threshold voltage (V _T ) of the first voltage level 43 . When the voltage gradually increases from a state where the voltage and current are zero, almost no current flows through the OTS device until the voltage reaches the threshold voltage V _T (ie, the first voltage level 43). However, as soon as the voltage exceeds the threshold voltage (V _T ), the current flowing through the OTS device may increase rapidly, and the voltage applied to the OTS device may reach the second voltage level 44 (or the saturation voltage (V _S )). is reduced

A second curve 42 represents a voltage-current relationship in a state where current flows through the OTS device. As the current flowing through the OTS device is greater than the first current level 46 , the voltage applied to the OTS device may be slightly higher than the second voltage level 44 . For example, the voltage applied to the OTS device may slightly increase from the second voltage level 44 while the current flowing through the OTS device significantly increases from the first current level 46 to the second current level 47. there is. That is, once the current flows through the OTS device, the voltage applied to the OTS device can be substantially maintained at the saturation voltage V _S (ie, the second voltage level 44). If the current decreases below the holding current level (ie, the first current level 46), the OTS element will switch back to the resistive state, effectively blocking the current until the voltage increases to the threshold voltage (V _T ). can

5A and 5B are schematic diagrams illustrating an operating method of a memory device having a cross-point stacked structure.

5A and 5B , each of the first and second lower memory cells MC11 and MC12 and the first and second upper memory cells MC21 and MC22 is connected to a common bit line BL and the first and second upper memory cells MC21 and MC22 therebelow. Read or A write operation method is shown.

Referring to FIG. 5A , the first lower memory cell MC11 disposed between the first lower word line WL11 and the common bit line BL is selected. To select the first lower memory cell MC11, a low voltage Vlow (eg, a bit line selection voltage or an inhibit voltage) is applied to the common bit line BL, and the first lower word line A word line select voltage (V _WL(Sel) ) may be applied to WL11.

For example, performing a write operation to store data in the first lower memory cell MC11 (for example, by a reset operation and a set operation) or reading data stored in the first lower memory cell MC11. A read operation may be performed for this purpose. A word line selection voltage V _WL(Sel) having a relatively high value is applied to the selected first lower word line WL11, and a low voltage Vlow having a relatively low value is applied to the common bit line BL. Accordingly, a first switching voltage having a value of (V _{WL ( Sel )} - Vlow) may be applied to the first lower memory cell MC11 . The level of the first switching voltage may be greater than the level of the threshold voltage of the selection element SW having the OTS characteristic, and accordingly, the selection element SW is turned on and the variable resistance of the first lower memory cell MC11 is turned on. A first current I _MC11 may flow through the layer R.

At this time, the word line unselect voltage V _{WL ( Unsel} ) is applied to the unselected second lower word line WL12 , first upper word line WL21 , and second upper word line _WL22 . An off voltage having a value of (V _{WL ( Unsel )} - Vlow) may be applied to the unselected memory cells MC12 , MC21 , and MC22 . The level of the off voltage may be smaller than the level of the threshold voltage of the selection element SW having the OTS characteristic, and accordingly, the selection element SW is not turned on, so that the memory cells MC12, MC21, and MC22 that are not selected Current does not flow through the variable resistance layer R of

Referring to FIG. 5B , the first upper memory cell MC21 disposed between the first upper word line WL21 and the common bit line BL is selected. To select the first upper memory cell MC21, a low voltage Vlow is applied to the common bit line BL and a word line selection voltage V _{WL ( Sel )} is applied to the first upper word line WL21. It can be. Accordingly, the second switching voltage having a value of (V _{WL ( Sel )} - Vlow) may be applied to the first upper memory cell MC21 . The level of the second switching voltage may be greater than the level of the threshold voltage of the selection element SW having the OTS characteristic, and accordingly, the selection element SW is turned on and the variable resistance of the first upper memory cell MC21 is turned on. A second current I _MC21 may flow through the layer R.

Comparing (A) and (B) of FIG. 5 , the magnitude of the first switching voltage applied to the selected first lower memory cell MC11 and the second switching voltage applied to the selected upper memory cell MC21 The magnitude of the voltage is the same. However, the direction of the first current I MC11 flowing through the selected first lower memory cell _MC11 is different from the direction of the second current I MC21 flowing through the first upper memory cell _MC21 . Accordingly, the amount of the first current I MC11 flowing through the selected first lower memory cell _MC11 may be different from the amount of the second current I _MC21 flowing through the first upper memory cell MC21 .

For example, while a relatively high voltage is applied to the first lower word line WL11 from the selection element SW of the first lower memory cell MC11, the selection element SW of the first upper memory cell MC21 ), a relatively high voltage is applied to the first upper word line WL21. Accordingly, electric fields in different directions may act on the selection element SW of the first lower memory cell MC11 and the selection element SW of the first upper memory cell MC21. The influence of the direction of the electric field acting on the selection element SW having the OTS characteristic will be described with reference to FIG. 6 .

6 is a voltage-current graph 60 when positive and negative voltages are respectively applied to the OTS device.

The first electrode layer 141-1 and the fourth electrode layer 148-1 may be selectively formed. In other words, the first electrode layer 141-1 and the fourth electrode layer 148-1 may be omitted. However, in order to prevent contamination or contact failure that may occur as the selection element layer 143-1 and/or the variable resistance layer 149-1 directly contact the conductive lines, the first electrode layer 141-1 ) and the fourth electrode layer 148-1 may be disposed between the conductive lines and the selection element layer 143-1 or the variable resistance layer 149-1.

At least one of the second electrode layer 145-1 and the third electrode layer 147-1 must be provided between the selection element layer 143-1 and the variable resistance layer 149-1. In general, when the selection device layer 143-1 is based on OTS characteristics, the selection device layer 143-1 may include an amorphous chalcogenide material. However, the thickness of the variable resistance layer 149-1, the selection device layer 143-1, the second electrode layer 145-1, and the third electrode layer 147-1 according to the downscaling tendency of the memory device 100, The width and the distance between them may be reduced. Therefore, in the driving process of the memory device 100, when the heating electrode layer (or the third electrode layer 147-1 when the heating electrode layer is not formed) generates heat to change the phase of the variable resistance layer 149-1 The heat generation may also affect the selection element layer 143-1 disposed adjacent thereto. For example, deterioration and damage of the selection element layer 143-1 such as partial crystallization of the selection element layer 143-1 by heat from the adjacent heating electrode layer may occur. Therefore, at least one of the second electrode layer 145-1 and the third electrode layer 147-1 is essentially provided between the selection element layer 143-1 and the variable resistance layer 149-1, and the selection element layer ( 143-1) can be prevented from deterioration and damage.

In addition, according to the material of the first to fourth electrode layers 141-1, 145-1, 147-1, and 148-1 and/or the arrangement of the heating electrode layers, the first to fourth electrode layers 141-1, 145-1 1, 147-1, 148-1) Each thickness may be variously changed. For example, when the heating electrode layer is arranged between the third electrode layer 147-1 and the variable resistance layer 149-1, heat from the heating electrode layer is not transferred to the selection element layer 143-1. The third electrode layer 147-1 and the second electrode layer 145-1 may be formed thickly. If the heating electrode layer is not formed and the third electrode layer 147-1 is formed to include a conductive material capable of generating enough heat to phase change the variable resistance layer 149-1, the third The second electrode layer 145-1 may be formed thick so that heat from the electrode layer 147-1 is not transmitted to the selection element layer 143-1. For example, the second electrode layer 145-1 and the third electrode layer 147-1 may have a thickness of about 10 to 100 nm. However, the thicknesses of the second electrode layer 145-1 and the third electrode layer 147-1 are not limited to the above values. In addition, the second electrode layer 145-1 or the third electrode layer 147-1 may include at least one thermal barrier layer for a heat blocking function. When the second electrode layer 145-1 or the third electrode layer 147-1 includes two or more thermal barrier layers, the second electrode layer 145-1 or the third electrode layer 147-1 is a thermal barrier It may have a structure in which layers and electrode material layers are alternately stacked.

A first insulating layer 162 - 1 may be disposed between the plurality of first conductive lines 110 . A first insulating layer 162 - 1 and a third insulating layer 163 may be disposed between the first memory cells 140 - 1 of the first memory cell layer MCL1 . Specifically, the first insulating layer 162-1 is disposed between the first memory cells 140-1 disposed along the second direction (Y direction in FIG. 2), and the first insulating layer 162-1 is disposed in the first direction (X direction in FIG. 2). A third insulating layer 163 may be disposed between the first memory cells 140 - 1 disposed along ). Also, the third insulating layer 163 may be disposed between the second conductive lines 120 . A second insulating layer 162-2 is formed between the second memory cells 140-2 disposed in the second direction of the second memory cell layer MCL2 and between the third conductive lines 130 disposed in the second direction. can be placed. The first to third insulating layers 162-1, 162-2, and 163 may be formed of an insulating layer of the same material or at least one of them may be formed of an insulating layer of a different material. The first to third insulating layers 162-1, 162-2, and 163 are formed of, for example, oxide or nitride dielectric materials, and may function to electrically separate elements of each layer from each other. Meanwhile, air spaces (not shown) may be formed in place of at least one of the first to third insulating layers 162-1, 162-2, and 163. When air spaces are formed, an insulating liner having a predetermined thickness between the air spaces and the first memory cells 140-1 and/or between the air spaces and the second memory cells 140-2 ( not shown) may be formed.

As exemplarily shown in FIG. 3 , the first selection element layer 143-1 of the first memory cell 140-1 has a first height (or thickness) along the third direction (Z direction in FIG. 2). )(H1), and the second selection device layer 143-2 of the second memory cell 140-2 has a second height (or thickness) smaller than the first height H1 along the third direction. ) (H2). In example embodiments, the first height H1 of the first selection device layer 143-1 may be 10 to 500 nm, and the second height H2 of the second selection device layer 143-2 ) may be 5 to 450 nm. However, the technical spirit of the present invention is not limited thereto.

In example embodiments, the second height H2 of the second selection element layer 143-2 is about 50% to 90% of the first height H1 of the first selection element layer 143-1. can be However, the technical spirit of the present invention is not limited thereto.

The first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 are The level of the threshold voltage (V _T1 ) and the level of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 may be adjusted to have substantially the same value.

In example embodiments, the first height H1 of the first selection device layer 143-1 and the second height H2 of the second selection device layer 143-2 are the first selection device layer ( The difference between the level of the first threshold voltage (V _T1 ) of 143-1 and the level of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 may be adjusted to be 0.5 V or less. For example, the level of the second threshold voltage (V _T2 ) of the second selection element layer 143-2 is 0.5V greater than the level of the first threshold voltage (V _T1 ) of the first selection element layer 143-1. can be smaller Unlike this, the level of the second threshold voltage (V _T2 ) of the second selection element layer 143-2 is 0.5V higher than the level of the first threshold voltage (V _T1 ) of the first selection element layer 143-1. may be large

In example embodiments, the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 are the second selection element layer ( 143-2) is adjusted so that the magnitude of the second threshold voltage (V _T2 ) is in the range of about 80% to about 120% of the magnitude of the first threshold voltage (V _T1 ) of the first selection device layer 143-1. can For example, the magnitude of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 is about 90% of the magnitude of the first threshold voltage (V _T1 ) of the first selection device layer 143-1. % to about 110%.

The magnitude of the second threshold voltage (V _T2 ) of the second selection element layer 143-2 is about 80% to about 120% of the magnitude of the first threshold voltage (V _T1 ) of the first selection element layer 143-1. In the case of % range, the difference in electrical characteristics between the first memory cell MC1 and the second memory cell MC2 is reduced, so that a sensing margin for a read/write operation of the memory device 100 may be improved.

Hereinafter, the relationship between the threshold voltage and electrical characteristics of the selection device layers 143-1 and 143-2 having ovonic threshold switching (OTS) characteristics will be described in detail with reference to FIGS. 4 to 6.

4 is a graph schematically illustrating a voltage-current curve 40 of an OTS device exhibiting ovonic threshold switching (OTS) characteristics. 4 schematically shows a current flowing through the OTS device according to a voltage applied across both ends of the OTS device having ovonic threshold switching (OTS) characteristics.

Referring to FIG. 4 , a first curve 41 represents a voltage-current relationship in a state in which current does not flow through the OTS device. Here, the OTS element acts as a switching element having a threshold voltage (V _T ) of the first voltage level 43 . When the voltage gradually increases from a state where the voltage and current are zero, almost no current flows through the OTS device until the voltage reaches the threshold voltage V _T (ie, the first voltage level 43). However, as soon as the voltage exceeds the threshold voltage (V _T ), the current flowing through the OTS device may increase rapidly, and the voltage applied to the OTS device may reach the second voltage level 44 (or the saturation voltage (V _S )). is reduced

A second curve 42 represents a voltage-current relationship in a state where current flows through the OTS device. As the current flowing through the OTS device is greater than the first current level 46 , the voltage applied to the OTS device may be slightly higher than the second voltage level 44 . For example, the voltage applied to the OTS device may slightly increase from the second voltage level 44 while the current flowing through the OTS device significantly increases from the first current level 46 to the second current level 47. there is. That is, once the current flows through the OTS device, the voltage applied to the OTS device can be substantially maintained at the saturation voltage V _S (ie, the second voltage level 44). If the current decreases below the holding current level (ie, the first current level 46), the OTS element will switch back to the resistive state, effectively blocking the current until the voltage increases to the threshold voltage (V _T ). can

5A and 5B are schematic diagrams illustrating an operating method of a memory device having a cross-point stacked structure.

5A and 5B , each of the first and second lower memory cells MC11 and MC12 and the first and second upper memory cells MC21 and MC22 is connected to a common bit line BL and the first and second upper memory cells MC21 and MC22 therebelow. Read or A write operation method is shown.

Referring to FIG. 5A , the first lower memory cell MC11 disposed between the first lower word line WL11 and the common bit line BL is selected. To select the first lower memory cell MC11, a low voltage Vlow (eg, a bit line selection voltage or an inhibit voltage) is applied to the common bit line BL, and the first lower word line A word line select voltage (V _WL(Sel) ) may be applied to WL11.

For example, performing a write operation to store data in the first lower memory cell MC11 (for example, by a reset operation and a set operation) or reading data stored in the first lower memory cell MC11. A read operation may be performed for this purpose. A word line selection voltage V _WL(Sel) having a relatively high value is applied to the selected first lower word line WL11, and a low voltage Vlow having a relatively low value is applied to the common bit line BL. Accordingly, a first switching voltage having a value of (V _{WL ( Sel )} - Vlow) may be applied to the first lower memory cell MC11 . The level of the first switching voltage may be greater than the level of the threshold voltage of the selection element SW having the OTS characteristic, and accordingly, the selection element SW is turned on and the variable resistance of the first lower memory cell MC11 is turned on. A first current I _MC11 may flow through the layer R.

At this time, the word line unselect voltage V _{WL ( Unsel} ) is applied to the unselected second lower word line WL12 , first upper word line WL21 , and second upper word line _WL22 . An off voltage having a value of (V _{WL ( Unsel )} - Vlow) may be applied to the unselected memory cells MC12 , MC21 , and MC22 . The level of the off voltage may be smaller than the level of the threshold voltage of the selection element SW having the OTS characteristic, and accordingly, the selection element SW is not turned on, so that the memory cells MC12, MC21, and MC22 that are not selected Current does not flow through the variable resistance layer R of

Referring to FIG. 5B , the first upper memory cell MC21 disposed between the first upper word line WL21 and the common bit line BL is selected. To select the first upper memory cell MC21, a low voltage Vlow is applied to the common bit line BL and a word line selection voltage V _{WL ( Sel )} is applied to the first upper word line WL21. It can be. Accordingly, the second switching voltage having a value of (V _{WL ( Sel )} - Vlow) may be applied to the first upper memory cell MC21 . The level of the second switching voltage may be greater than the level of the threshold voltage of the selection element SW having the OTS characteristic, and accordingly, the selection element SW is turned on and the variable resistance of the first upper memory cell MC21 is turned on. A second current I _MC21 may flow through the layer R.

Comparing (A) and (B) of FIG. 5 , the magnitude of the first switching voltage applied to the selected first lower memory cell MC11 and the second switching voltage applied to the selected upper memory cell MC21 The magnitude of the voltage is the same. However, the direction of the first current I MC11 flowing through the selected first lower memory cell _MC11 is different from the direction of the second current I MC21 flowing through the first upper memory cell _MC21 . Accordingly, the amount of the first current I MC11 flowing through the selected first lower memory cell _MC11 may be different from the amount of the second current I _MC21 flowing through the first upper memory cell MC21 .

For example, while a relatively high voltage is applied to the first lower word line WL11 from the selection element SW of the first lower memory cell MC11, the selection element SW of the first upper memory cell MC21 ), a relatively high voltage is applied to the first upper word line WL21. Accordingly, electric fields in different directions may act on the selection element SW of the first lower memory cell MC11 and the selection element SW of the first upper memory cell MC21. The influence of the direction of the electric field acting on the selection element SW having the OTS characteristic will be described with reference to FIG. 6 .

6 is a voltage-current graph 60 when positive and negative voltages are respectively applied to the OTS device.

Referring to FIG. 6 , in the first OTS device of the first experimental example 62 and the OTS device of the second experimental example 64 having different device dimensions, when a positive voltage is applied and a negative voltage is applied, It can be seen that different voltage-current profiles are obtained when Specifically, the OTS device of the first experimental example 62 has a first threshold voltage 56(V ₁ ) in a positive voltage range and a second threshold voltage 58(V ₂ ) in a negative voltage range. have It can be clearly seen that the magnitude of the first threshold voltage 56 (V ₁ ) is greater than that of the second threshold voltage 58 (V ₂ ).

In other words, the current and threshold voltage flowing through the selection element SW may vary according to the direction of the electric field acting on the selection element SW. 5A and 5B , even when the selection voltage V _{WL ( Sel )} of the same magnitude is applied to the lower word line WL11 and the upper word line W21 , the lower memory cell MC11 connected to the lower word line WL11 and the upper memory cell MC21 connected to the upper word line W21 may have different current profiles and different threshold voltages.

It can be understood that this phenomenon is caused by an asymmetric defect density and composition distribution in the selection element SW. For example, the selection element SW having ovonic threshold switching characteristics may include a chalcogenide material. In the switching mechanism of chalcogenide materials, when a high electric field is applied, electron trap sites are non-uniformly distributed in the chalcogenide material, and electrons move at a relatively high speed along the electron trap sites. It is known to do

In addition, when more defects are formed in the selection element SW, the density of the electron trap sites may increase, and in this case, since electrons can move along the electron trap sites even with a small electric field, the selection element The threshold voltage of (SW) may be reduced.

Referring back to FIGS. 2 and 3 , the first height H1 of the first selection device layer 143-1 in the first memory cell 140-1 is equal to the second height H1 in the second memory cell 140-2. It is greater than the second height H2 of the selection element layer 143-2. This is because the threshold voltage of the first selection device layer 143-1 is equal to the threshold voltage of the second selection device layer 143-2 in consideration of the defect density of the selection device layers 143-1 and 143-2. It may be a result of adjusting the first height H1 and the second height H2 to be substantially equal to .

In general, the defect density of the first selection device layer 143-1 located on the first level of the substrate 101 is not the same as that of the second selection device layer 143-2 located on the second level. may not be Here, the second level means a location farther from the upper surface of the substrate 101 than the first level, and the first selection element layer 143-1 is the second selection element layer 143-2. ) close to the top surface.

In general, the first selection device layer 143-1 located on the first level is exposed to process atmospheres such as deposition processes or etching processes of subsequent layers for a longer period of time. In addition, heat is supplied from the bottom surface of the substrate 101 by a chuck or a heater disposed on the bottom surface of the substrate 101 to maintain a process temperature generally ranging from several tens to hundreds of degrees Celsius. Therefore, the first selection element layer 143-1 located on the first level of the substrate 101 is an etching atmosphere and a high temperature atmosphere compared to the second selection element layer 143-2 located on the second level. It may be exposed to the atmosphere of the deposition process for a longer period of time. Accordingly, the first selection device layer 143-1 located on the first level of the substrate 101 may contain defects of a higher density than the second selection device layer 143-2 located on the second level. there is.

As described above, according to the switching mechanism of the selection element layers 143-1 and 143-2 having ovonic threshold switching characteristics, the first selection element layer 143-1 located on the first level of the substrate 101 ) includes defects of higher density than the second selection device layer 143-2 located at the second level, the threshold voltage of the first selection device layer 143-1 is increased by the second selection device layer 143 -2) may be lower than the threshold voltage. As the difference in magnitude between the threshold voltage of the first selection device layer 143-1 and the threshold voltage of the second selection device layer 143-2 increases, the sensing margin in the write operation and/or the read operation decreases, so that the memory device ( 100) write and/or read failures may occur.

However, according to the above-described exemplary embodiments, the first memory cell 140-1 is configured so that the threshold voltages of the first selection device layer 143-1 and the second selection device layer 143-2 are substantially the same. The first height H1 of the first selection device layer 143-1 in the second memory cell 140-2 and the second height H2 of the second selection device layer 143-2 in the second memory cell 140-2 may be adjusted. there is.

For example, the first height H1 of the first selection element layer 143-1 in the first memory cell 140-1 is equal to the second selection element layer 143-1 in the second memory cell 140-2. Since it is greater than the second height H2 of 2), even if the same switching voltage is applied to the first selection device layer 143-1 and the second selection device layer 143-2, the first selection device layer 143-1 ) may be smaller than the magnitude of the electric field acting on the second selection device layer 143-2. Therefore, even when the first selection device layer 143-1 includes a higher density of defects, a decrease in threshold voltage due to the defects can be prevented, and the first selection device layer 143-1 and A deviation of threshold voltages of the second selection device layer 143-2 may decrease.

In addition, the difference between the first height H1 of the first selection device layer 143-1 and the second height H2 of the second selection device layer 143-2 according to exemplary embodiments of the present invention is , Considering the direction of the electric field applied to the selection device layers 143-1 and 143-2, the size of the threshold voltage of the first selection device layer 143-1 is the size of the second selection device layer 143-2. It may be a result of adjusting the first height H1 and the second height H2 to be substantially equal to .

As described with reference to FIGS. 5A, 5B, and 6, when a negative voltage is applied to the selection device layers 143-1 and 143-2, a positive voltage is applied to the selection device layers 143-1 and 143-2. It can be seen that the selection element layers 143-1 and 143-2 have lower threshold voltages compared to the case where voltage is applied. Therefore, in a general memory device in which the first selection device layer 143-1 and the second selection device layer 143-2 have the same height, a negative voltage is applied to the first selection device layer 143-1 and When a positive voltage is applied to the second selection element layer 143-2, the magnitude of the threshold voltage (eg, 58(V ₂ ) of the first selection element layer 143-1) of the second selection element layer 143-2 is It may be smaller than the threshold voltage (eg, 56 (V ₁ ) of FIG. 6 ) of (143-2). For example, when a relatively low voltage is applied to the second conductive line 120 and a relatively high voltage is applied to the third conductive line 130 and the first conductive line 110 (ie, the second conductive line (120) and a word line selection voltage greater than the cut-off voltage is applied to the first and third conductive lines 110 and 130), the first selection element layer 143-1 The level of the threshold voltage (eg, 58 (V ₂ ) in FIG. 6 ) may be smaller than the level of the threshold voltage (eg, 56 (V ₁ ) in FIG. 6 ) of the second selection device layer 143 - 2 .

However, according to the above exemplary embodiments, the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2. , An electric field acting on the first selection device layer 143-1 when a negative voltage is applied to the first selection device layer 143-1 and a positive voltage is applied to the second selection device layer 143-2. The size of may be smaller than the size of the electric field acting on the second selection device layer 143-2. That is, a difference in threshold voltage between the first selection device layer 143-1 and the second selection device layer 143-2 may be reduced, and the first memory cell 140-1 and the second memory cell ( 140-2) electrical characteristic deviation can be reduced

Consequently, since the difference between the threshold voltages of the first selection device layer 143-1 and the second selection device layer 143-2 is reduced, the sensing margin in the read/write operation of the memory device 100 is improved. and read/write failure due to a small sensing margin can be prevented. The memory device 100 may have excellent reliability.

7 to 13 are cross-sectional views illustrating memory devices 100A, 100B, 100C, 100D, 100E, 100F, and 100G according to example embodiments, and are cross-sectional views along lines A-A' and B-B' of FIG. 2 . Indicates the cross sections corresponding to . 7 to 13, the same reference numerals as in FIGS. 1 to 6 denote the same components.

Referring to FIG. 7 , in the memory device 100A according to example embodiments, the first height H1A of the first selection device layer 143-1 of the first memory cell 140-1 is the second height H1A. It may be smaller than the second height H2A of the second selection device layer 143-2 of the memory cell 140-2.

The first height H1A of the first selection element layer 143-1 and the second height H2A of the second selection element layer 143-2 are The level of the threshold voltage (V _T1 ) and the level of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 may be adjusted to have substantially the same value. For example, the magnitude of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 is about 80% of the magnitude of the first threshold voltage (V _T1 ) of the first selection device layer 143-1. % to about 120%, or from about 90% to about 110%.

In example embodiments, the first height H1A of the first selection device layer 143-1 and the second height H2A of the second selection device layer 143-2 are the first selection device layer ( The difference between the level of the first threshold voltage (V _T1 ) of 143-1 and the level of the second threshold voltage (V _T2 ) of the second selection device layer 143-2 may be adjusted to be 0.5 V or less.

In example embodiments, the first height H1A of the first selection device layer 143-1 may be 5 to 450 nm, and the second height H2A of the second selection device layer 143-2 ) may be 10 to 500 nm. However, the technical spirit of the present invention is not limited thereto. For example, the first height H1A of the first selection device layer 143-1 may be about 50% to 90% of the second height H2A of the second selection device layer 143-2. However, the technical spirit of the present invention is not limited thereto.

As described with reference to FIGS. 5A, 5B, and 6, when a negative voltage is applied to the selection device layers 143-1 and 143-2, a positive voltage is applied to the selection device layers 143-1 and 143-2. It can be seen that the selection element layers 143-1 and 143-2 have lower threshold voltages compared to the case where voltage is applied. Therefore, in a general memory device in which the first selection device layer 143-1 and the second selection device layer 143-2 have the same height, a positive voltage is applied to the first selection device layer 143-1 and When a negative voltage is applied to the second selection element layer 143-2, the magnitude of the threshold voltage (eg, 58 (V ₂ ) in FIG. 6) of the second selection element layer 143-2 is the first selection element layer It may be smaller than the threshold voltage of (143-1) (e.g. 56 (V ₁ ) in FIG. 6). For example, when a relatively high voltage is applied to the second conductive line 120 and a relatively low voltage is applied to the third conductive line 130 and the first conductive line 110 (ie, the second conductive line When a cut-off voltage is applied to (120) and a word line selection voltage smaller than the cut-off voltage is applied to the first and third conductive lines 110 and 130), of the second selection element layer 143-2 The magnitude of the threshold voltage may be smaller than that of the first selection device layer 143-1.

However, according to example embodiments, the second height H2A of the second selection element layer 143-2 of the second memory cell 140-2 is equal to the first height H2A of the first memory cell 140-1. Since it is greater than the first height H1A of the selection element layer 143-1, a positive voltage is applied to the first selection element layer 143-1 and a negative voltage is applied to the second selection element layer 143-2. When this is applied, the electric field acting on the second selection device layer 143-2 may be smaller than the electric field acting on the first selection device layer 143-1. That is, a difference in threshold voltage between the first selection device layer 143-1 and the second selection device layer 143-2 may be reduced, and the first memory cell 140-1 and the second memory cell ( 140-2) may reduce electrical characteristic deviation.

Consequently, since the difference between the threshold voltages of the first selection device layer 143-1 and the second selection device layer 143-2 is reduced, the sensing margin in the read/write operation of the memory device 100 is improved. and read/write failure due to a small sensing margin can be prevented. The memory device 100A may have excellent reliability.

Referring to FIG. 8 , in a memory device 100B according to example embodiments, a first internal spacer 152-1 is formed on a sidewall of a first memory cell 140-1, and a second memory cell ( A second inner spacer 152-2 may be formed on the sidewall of the 140-2. The first inner spacer 152-1 covers sidewalls of the first electrode layer 141-1 and the first selection device layer 143-1 of the first memory cell 140-1, and the second inner spacer 152 -2) may cover sidewalls of the fifth electrode layer 141-2 and the second selection device layer 143-2 of the second memory cell 140-2. The first inner spacer 152-1 and the second inner spacer 152-2 surround the side surfaces of the memory cells 140-1 and 140-2, so that the memory cells 140-1 and 140-2, In particular, it can function to protect the selection element layers 143-1 and 143-2.

8 shows that the first selection element layer 143-1 is formed to have a first height H1 greater than the second height H2 of the second selection element layer 143-2, but this The technical idea of the invention is not limited thereto. Unlike the drawing, the first height H1 of the first selection device layer 143-1 may be smaller than the second height H2 of the second selection device layer 143-2.

Although FIG. 8 exemplarily shows that the first electrode layer 141-1 and the fifth electrode layer 141-2 are formed to have the same thickness, the technical spirit of the present invention is not limited thereto. Unlike the drawing, the first electrode layer 141-1 may be formed to have a greater thickness than the fifth electrode layer 141-2, and the first electrode layer 141-1 may be formed to have a thickness greater than that of the fifth electrode layer 141-2. It may be formed to have a small thickness.

In example embodiments, the first electrode layer 141-1, the fifth electrode layer 141-2, and the first and second selection element layers 143-1 and 143-2 are formed by a damascene process. and the second to fourth electrode layers 145-1, 147-1, and 148-1, the sixth to eighth electrode layers 145-2, 147-2, and 148-2, and the first to second electrode layers. The variable resistance layers 149-1 and 149-2 may be formed through an etching process. Accordingly, the first electrode layer 141-1, the fifth electrode layer 141-2, and the first and second selection element layers 143-1 and 143-2 have a structure in which the width decreases toward the bottom. can

In example embodiments, when the first electrode layer 141-1 and the first selection device layer 143-1 are formed by a damascene process, the first internal spacer 152 is formed on a sidewall of a trench (not shown). -1) is formed, and then the first electrode layer 141-1 and the first selection device layer 143-1 are sequentially formed in the trench having the first inner spacer 152-1 to fill the trench. there is. Then, the second to fourth electrode layers 145-1, 147-1, and 148-1 and the first variable resistance layer 149-1 may be formed. The second electrode layer 141-2 and the second selection element layer 143-2 may be formed in a method similar to the method of forming the first electrode layer 141-1 and the first selection element layer 143-1. .

Referring to FIG. 9 , in a memory device 100C according to example embodiments, a first upper spacer 155-1 is formed on a sidewall of a first memory cell 140-1, and a second memory cell ( A second upper spacer 155-2 may be formed on the sidewall of the 140-2. The first upper spacer 155-1 covers the sidewall of the first variable resistance layer 149-1 of the first memory cell 140-1, and the first upper spacer 155-1 covers the second memory cell ( It may cover the sidewall of the second variable resistance layer 149-2 of 140-2. The first upper spacer 155-1 and the second upper spacer 155-2 surround the side surfaces of the memory cells 140-1 and 140-2, so that the memory cells 140-1 and 140-2, In particular, it can function to protect the variable resistance layers 149-1 and 149-2.

9 shows that the first selection element layer 143-1 is formed to have a first height H1 greater than the second height H2 of the second selection element layer 143-2, but this The technical idea of the invention is not limited thereto. Unlike the drawing, the first height H1 of the first selection device layer 143-1 may be smaller than the second height H2 of the second selection device layer 143-2.

In example embodiments, the first and second variable resistance layers 149-1 and 149-2 are formed by a damascene process, and the first to fourth electrode layers 141-1, 145-1, 147-1, 148-1), first and second selection element layers 143-1 and 143-2, and fifth to eighth electrode layers 141-2, 145-2, 147-2, 148- 2) may be formed through an etching process. Accordingly, the first and second variable resistance layers 149-1 and 149-2 may have a structure in which a width becomes narrower toward the bottom.

In example embodiments, when the first variable resistance layer 149-1 is formed by a damascene process, a first upper spacer 155-1 is formed on a sidewall of a trench (not shown), and then a second upper spacer 155-1 is formed. A first variable resistance layer 149 - 1 filling the trench may be formed in the trench having one upper spacer 155 - 1 . The second variable resistance layer 149-1 may be formed in a method similar to that of the first variable resistance layer 149-1.

Referring to FIG. 10 , in the memory device 100D according to example embodiments, the variable resistance layers 149-1 and 149-2 may be formed in an “L” cross-section structure. Specifically, the first to fourth electrode layers 141-1, 145-1, 147-1, and 148-1, the first and second selection element layers 143-1 and 143-2, and the fifth to fourth electrode layers 143-1 and 143-2. The eighth electrode layers 141-2, 145-2, 147-2, and 148-2 may be formed through an etching process, and the first and second variable resistance layers 149-1 and 149-2 may be formed through an etching process. It can be formed in a damascene process.

Upper spacers 155-1 and 155-2 may be formed on side surfaces of the first and second variable resistance layers 149-1 and 149-2. However, as the first and second variable resistance layers 149-1 and 149-2 are formed in an “L” cross-sectional structure, the upper spacers 155-1 and 155-2 are formed in an asymmetric structure. can

In an exemplary process for forming the variable resistance layers 149-1 and 149-2, an insulating layer is formed on each of the third electrode layer 147-1 and the seventh electrode layer 147-2, and the insulating layer form a trench in The trench is formed between the adjacent first selection device layers 143-1 and the adjacent second selection device layers 143-2. Widely formed to overlap each other. Next, a first material layer to form a variable resistance layer is thinly formed inside the trench and on the insulating layer, and then a second material layer to form an upper spacer is formed on the first material layer. Thereafter, planarization is performed through CMP (Chemical Mechanical Polishing) or the like so that the upper surface of the insulating layer is exposed. After planarization, the first material layer and the second material layer are etched using a mask pattern aligned with the memory cells 140-1 and 140-2 to form an “L” cross-section of the variable resistance layer 149-1. , 149-2) and sidewalls of the variable resistance layers 149-1 and 149-2, upper spacers 155-1 and 155-2 may be formed, respectively.

Referring to FIG. 11 , in the memory device 100E according to example embodiments, variable resistance layers 149-1 and 149-2 may be formed to have an “I”-shaped cross-sectional structure.

The variable resistance layers 149-1 and 149-2 having an “I” cross-sectional structure may be formed in a similar manner to the method of forming the “L” cross-sectional structure. For example, after forming a thin first material layer to form a variable resistance layer on the inside of the trench and on the insulating layer, only the sidewall of the trench is left through anisotropic etching. Thereafter, a second material layer is formed to cover the remaining first material layer. Thereafter, planarization is performed through CMP or the like so that the upper surface of the insulating layer is exposed. After planarization, a mask pattern aligned with the memory cells 140-1 and 140-2 is formed, and the second material layer is etched using the mask pattern, thereby forming the variable resistance layer 149 having an “I” cross-sectional structure. -1 and 149-2) and upper spacers 155-1 and 155-2 may be formed.

Referring to FIG. 12 , in the memory device 100F according to example embodiments, a first heating electrode layer 146-1 is disposed between the first variable resistance layer 149-1 and the third electrode layer 147-1. may be further formed, and a second heating electrode layer 146-2 may be further formed between the second variable resistance layer 149-2 and the eighth electrode layer 148-2.

12, the first variable resistance layer 149-1 and the first heating electrode layer 146-1 along the direction from the second conductive line 120 toward the first conductive line 110. ) are arranged in order, and the second variable resistance layer 149-2 and the second heating electrode layer 146-2 are sequentially formed along the direction from the second conductive line 120 to the third conductive line 130. can be arranged

The arrangement of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory cell 140-1 is centered on the second conductive line 120, and the second memory cell 140 -2) has a structure symmetrical with the arrangement of the second variable resistance layer 149-2 and the second heating electrode layer 146-2, so that the first variable resistance layer 149-1 and the second variable resistance A resistance difference between the layers 149-2 may be reduced. For example, when the first variable resistance layer 149-1 and the second variable resistance layer 149-2 include a GeSbTe material, the first variable resistance layer 149-1 and the second variable resistance layer ( 149-2), the diffusion rates of cations (eg Sb ⁺ ) and anions (eg Te ⁻ ) may be different. When a negative voltage and a positive voltage are applied to the first variable resistance layer 149-1 and the second variable resistance layer 149-2, respectively, the first variable resistance layer 149-1 and the second variable resistance layer 149-1 A local concentration change may be induced by a difference in diffusion rate of cations and anions in the resistive layer 149-2, and accordingly, the first variable resistive layer 149-1 and the second variable resistive layer 149- The resistance value of 2) may be different from each other.

However, according to exemplary embodiments, the stack structure of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory cell 140-1 is the second conductive line ( 120) may have a stacked structure of the second variable resistance layer 149-2 and the second heating electrode layer 146-2 in the second memory cell 140-2, and a symmetrical structure. Since the resistance difference between the variable resistance layer 149-1 and the second variable resistance layer 149-2 is reduced, the first memory cell 140-1 and the second memory cell 140-2 operate uniformly. may have characteristics.

Referring to FIG. 13 , in the memory device 100G according to example embodiments, a first heating electrode layer 146-1 is disposed between the first variable resistance layer 149-1 and the fourth electrode layer 148-1. may be further formed, and a second heating electrode layer 146-2 may be further formed between the second variable resistance layer 149-2 and the seventh electrode layer 147-2.

13, the arrangement of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory cell 140-1 is the second conductive line ( 120 as the center, the arrangement of the second variable resistance layer 149-2 and the second heating electrode layer 146-2 in the second memory cell 140-2 may be symmetrical. As described above, the difference in resistance value between the first variable resistance layer 149-1 and the second variable resistance layer 149-2 is reduced so that the first memory cell 140-1 and the second memory cell 140 -2) may have uniform operating characteristics.

10 to 13, the first selection device layer 143-1 is formed to have a first height H1 greater than the second height H2 of the second selection device layer 143-2 by way of example. Although illustrated, the technical spirit of the present invention is not limited thereto, and the first selection element layer 143-1 has a first height H1 smaller than the second height H2 of the second selection element layer 143-2. It may be formed to have.

In the embodiments described with reference to FIGS. 1 to 13 , the first and second memory cells 140 - 1 and 140 - 2 are vertically arranged between the first to third conductive lines 110 , 120 and 130 . structure has been described. However, the technical spirit of the present invention is not limited thereto. An insulating layer (not shown) is formed on the third conductive line 130, and at least one of the stacked structures having a cross point array described with reference to FIGS. 1 to 13 is further disposed on the insulating layer. It could be.

14 is a perspective view illustrating a memory device 200 according to example embodiments. 15 is a cross-sectional view taken along line 2A-2A' of FIG. 14;

14 and 15 , the memory device 200 includes a driving circuit area 210 formed on a first level on a substrate 102 and a memory cell array area MCA formed on a second level on the substrate 102. can include

Here, the term “level” means a height from the substrate 102 along the vertical direction (Z direction in FIGS. 14 and 15). On the substrate 102 the first level is closer to the substrate 102 than the second level.

The driving circuit area 210 may be an area where peripheral circuits or driving circuits for driving the memory cells of the memory cell array area MCA are disposed. For example, peripheral circuits disposed in the driving circuit area 210 may be circuits that can process data input/output to the memory cell array area MCA at high speed. For example, the peripheral circuits include a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, and a data in/out circuit. /out circuit) or row decoder, etc.

An active region AC for a peripheral circuit (or a driving circuit) may be defined on the substrate 102 by the device isolation layer 104 . A plurality of transistors TR constituting a peripheral circuit of the driving circuit region 210 may be formed on the active region AC of the substrate 102 . Each of the plurality of transistors TR may include a gate G, a gate insulating layer GD, and a source/drain region SD. Both sidewalls of the gate G may be covered with an insulating spacer 106 , and an etch stop layer 108 may be formed on the gate G and the insulating spacer 106 . The etch stop layer 108 may include an insulating material such as silicon nitride or silicon oxynitride.

A plurality of interlayer insulating layers 212A, 212B, and 212C may be sequentially stacked on the etch stop layer 108 . The plurality of interlayer insulating layers 212A, 212B, and 212C may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

The driving circuit region 210 includes a multilayer wiring structure 214 electrically connected to the plurality of transistors TR. The multilayer wiring structure 214 may be covered by a plurality of interlayer insulating films 212A, 212B, and 212C.

The multilayer wiring structure 214 includes a first contact 216A, a first wiring layer 218A, a second contact 216B, and a second wiring layer 218B sequentially stacked on the substrate 102 and electrically connected to each other. ) may be included. In example embodiments, the first wiring layer 218A and the second wiring layer 218B may be made of metal, conductive metal nitride, metal silicide, or a combination thereof. For example, the first wiring layer 218A and the second wiring layer 218B include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide. can do.

In FIG. 15, the multilayer wiring structure 214 is illustrated as having a two-layer wiring structure including a first wiring layer 218A and a second wiring layer 218B, but the technical concept of the present invention is illustrated in FIG. 15 It is not limited. For example, the multi-layer wiring structure 214 may have three or more layers depending on the layout of the driving circuit region 210 and the type and arrangement of the gates G.

An upper interlayer insulating layer 220 may be formed on the plurality of interlayer insulating layers 212A, 212B, and 212C. The memory cell array area MCA may be disposed on the upper interlayer insulating layer 220 . The memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, and 100G described with reference to FIGS. 1 to 13 or a combination thereof may be disposed in the memory cell array area MCA.

Although not shown, a wiring structure (not shown) connected between the memory cells of the memory cell array area MCA and the peripheral circuits of the driving circuit area 210 may be disposed through the upper interlayer insulating film 220. can

According to the memory device 200 according to example embodiments, as the memory cell array area MCA is disposed above the driving circuit area 210 , the degree of integration of the memory device 200 may be further increased.

16A to 16I are cross-sectional views illustrating a manufacturing method of the memory device 100 according to exemplary embodiments according to a process sequence.

A method of manufacturing the memory device 100 illustrated in FIGS. 2 and 3 will be described with reference to FIGS. 16A to 16I. 16A to 16I respectively show a cross-sectional configuration of a portion corresponding to the line A-A' in FIG. 2 and a cross-sectional configuration of a portion corresponding to the line B-B' in FIG. 2 according to the process order. In Figs. 16A to 16I, the same reference numerals as in Figs. 1 to 15 denote the same members, and therefore detailed descriptions thereof are omitted here.

Referring to FIG. 16A , an interlayer insulating layer 105 may be formed on a substrate 101 . In example embodiments, an interlayer insulating layer 105 may be formed on the substrate 101 using at least one of silicon oxide, silicon oxynitride, and silicon nitride.

A first conductive layer 110P is formed on the interlayer insulating film 105, and a preliminary first electrode layer 141-1P, a preliminary first selection element layer 143-1P, and a preliminary first electrode layer 143-1P are formed on the first conductive layer 110P. A second electrode layer 145-1P, a preliminary third electrode layer 147-1P, a preliminary first variable resistance layer 149-1P, and a preliminary fourth electrode layer 148-1P are sequentially stacked to form a cross point array. 1 laminated structure (CPS1) is formed.

A first conductive layer 110P, a preliminary first electrode layer 141-1P, a preliminary first selection element layer 143-1P, a preliminary second electrode layer 145-1P, a preliminary third electrode layer 147-1P, Materials of the preliminary first variable resistance layer 149-1P and the preliminary fourth electrode layer 148-1P are the first conductive line 110, the first electrode layer 141-1, and the first electrode layer 141-1 described in FIGS. 2 and 3, respectively. The first selection element layer 143-1, the second electrode layer 145-1, the third electrode layer 147-1, the first variable resistance layer 149-1, and the fourth electrode layer 148-1 have been described. same as

Thereafter, a first mask pattern 410 is formed on the first stacked structure CPS1.

The first mask pattern 410 may include a plurality of line patterns extending along a first direction (X direction) (see FIG. 2 ) and spaced apart from each other in a second direction (Y direction) (see FIG. 2 ). The first mask pattern 410 may be formed of a single layer or a multi-layer structure in which a plurality of layers are stacked. For example, the first mask pattern 410 may be formed of a photoresist pattern, a silicon oxide pattern, a silicon nitride pattern, a silicon oxynitride pattern, a polysilicon pattern, or a combination thereof, but is limited to the materials exemplified above. However, the first mask pattern 410 may be formed using various materials.

Referring to FIG. 16B , the first mask pattern is such that the first stacked structure CPS1 is separated into a plurality of first stacked lines CPL1 and the first conductive layer 110P is separated into a plurality of first conductive lines 110 . The first stacked structure CPS1 and the first conductive layer 110P are sequentially anisotropically etched using 410 as an etch mask.

As a result, a plurality of first conductive lines 110 and a plurality of first stacked lines CPL1 extending in the first direction (X direction) (see FIG. 2 ) may be formed. The plurality of first stacking lines CPL1 include a first electrode layer line 141-1L, a first selection element layer line 143-1L, a second electrode layer line 145-1L, and a third electrode layer line 147-1L, respectively. 1L), the first variable resistance layer line 149-1L, and the fourth electrode layer line 148-1L, and may be separated from each other in the second direction (Y direction) (see FIG. 2). The plurality of conductive lines 110 extend in a first direction and are separated from each other in a second direction to form a first conductive line layer 110L.

In addition, by the anisotropic etching process, each of the plurality of first conductive lines 110 and the plurality of first stacked lines CPL1 extends in the first direction (X direction) and is separated from each other in the second direction (Y direction). A plurality of first gaps GX1 may be formed. As the plurality of first gaps GX1 are formed, a portion of the upper surface of the substrate 101 may be exposed again within the plurality of first gaps GX1.

Referring to FIG. 16C , after removing the first mask pattern 410 (see FIG. 16B ), exposing the upper surface of the fourth electrode layer line 148-1L, and then filling the plurality of first gaps GX1, respectively, 1 insulating layer 162-1 is formed.

In example embodiments, a plurality of first gaps GX1 are filled using an insulating material on the substrate 101, and an upper portion of the insulating material is covered until an upper surface of the plurality of first stacked lines CPL1 is exposed. The first insulating layer 162-1 may be formed by planarization.

The first insulating layer 162-1 may be formed of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The first insulating layer 160P may include one kind of insulating layer or a plurality of insulating layers. However, the technical spirit of the present invention is not limited thereto.

Referring to FIG. 16D , a second conductive layer 120P is formed on the exposed upper surface of the fourth electrode layer line 148-1L and the exposed upper surface of the first insulating layer 162-1.

Subsequently, a preliminary fifth electrode layer 141-2P, a preliminary second selection element layer 143-2P, a preliminary sixth electrode layer 145-2P, and a preliminary seventh electrode layer 147-2P are formed on the second conductive layer 120P. ), the preliminary second variable resistance layer 149 - 2P and the preliminary eighth electrode layer 148 - 2P are sequentially stacked to form a second stacked structure CPS2 .

A second conductive layer 120P, a preliminary fifth electrode layer 141-2P, a preliminary second selection element layer 143-2P, a preliminary sixth electrode layer 145-2P, a preliminary seventh electrode layer 147-2P, Materials of the preliminary second variable resistance layer 149-2P and the preliminary eighth electrode layer 148-2P are the second conductive line 120, the fifth electrode layer 141-2, and the second conductive line 120 described in FIGS. 2 and 3, respectively. 2 The selection element layer 143-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, the variable resistance layer 149-2, and the eighth electrode layer 148-2 are the same as those described above. do.

Thereafter, a second mask pattern 420 is formed on the second stacked structure CPS2. The second mask pattern 420 may include a plurality of line patterns that extend along the second direction (Y direction) (see FIG. 2 ) and are spaced apart from each other in the first direction (X direction) (see FIG. 2 ).

Referring to FIG. 16E , the second stacked structure CPS2 is divided into a plurality of second stacked lines CPL2, the second conductive layer 120P is divided into a plurality of second conductive lines 120, and the plurality of second stacked lines CPL2 is separated. The second stacking structure CPS2, the second conductive layer 120P, and the plurality of first stacking lines CPL1 are separated by using the second mask pattern 420 as an etching mask so that each stacking line CPL1 is separated into a plurality of first stacking patterns CPP1. The first stacked lines CPL1 of are sequentially anisotropically etched.

As a result, a plurality of second stacked lines CPL2 extending in the second direction (Y direction) (see FIG. 2 ) and spaced apart in the first direction (X direction) (see FIG. 2 ), extending in the second direction and A plurality of second conductive lines 120 spaced apart in one direction are formed. Also, a plurality of first stacked patterns CPP1 spaced apart from each other in the second direction may be formed. The plurality of second conductive lines 120 form the second conductive line layer 120L. can do. The plurality of second stacking lines CPL2 include a fifth electrode layer line 141-2L, a second selection device layer line 143-2L, a sixth electrode layer line 145-2L, and a seventh electrode layer line 147-2L, respectively. 2L), the second variable resistance layer line 149-2L, and the eighth electrode layer line 148-2L. The plurality of first stacked patterns CPP1 include a first electrode layer 141-1, a first selection device layer 143-1, a second electrode layer 145-1, a third electrode layer 147-1, and a second electrode layer 147-1. One variable resistance layer 149-1 and a fourth electrode layer 148-1 may be included.

In addition, the anisotropic etching process extends in the second direction between the plurality of second stacked lines CPL2 and the plurality of second conductive lines 120 and between the plurality of first stacked patterns CPP1 and extends in the first direction. A plurality of second gaps GY1 separated from each other may be formed.

In example embodiments, the anisotropic etching process may be performed until upper surfaces of the plurality of first conductive lines 110 are exposed. Although not shown, recesses (not shown) having a predetermined depth may be formed on the upper side of the plurality of first conductive lines 110 by the anisotropic etching process.

In other embodiments, the anisotropic etching process is performed until the upper surface of the first electrode layer line 141 - 1L (see FIG. 16G ) is exposed, and then the plurality of first conductive lines 110 are exposed. A portion of the first electrode layer line 141-1L exposed in the plurality of second gaps GY1 is removed by performing an etching process in which the first electrode layer line 141-1L has an etching selectivity, thereby forming a plurality of first conductive lines The upper surface of 110 may be exposed.

Referring to FIG. 16F, after the second mask pattern 420 (see FIG. 16E) is removed to expose the upper surface of the second stacking line CPL2, a second insulating layer (which fills the plurality of second gaps GY1) 163) form.

In example embodiments, a plurality of second gaps ( The second insulating layer 163 may be formed by filling GY1 ) and planarizing an upper portion of the insulating material until upper surfaces of the plurality of second stacked lines CPL2 are exposed.

Referring to FIG. 16G , a third conductive layer 130P is formed on the plurality of second stacked lines CPL2 and the second insulating layer 163 .

Thereafter, a third mask pattern 430 is formed on the third conductive layer 130P. The third mask pattern 430 may include a plurality of line patterns extending along a first direction (X direction) (see FIG. 2 ) and spaced apart in a second direction (Y direction) (see FIG. 2 ).

Referring to FIG. 16H , the third conductive layer 130P is separated into a plurality of third conductive lines 130 and each of the plurality of second stacked lines CPL2 is separated into a plurality of second stacked patterns CPP2. 3 Using the mask pattern 430 as an etching mask, the third conductive layer 130P and the plurality of second stacking lines CPL2 are sequentially anisotropically etched.

As a result, a plurality of third conductive lines 130 extending in the first direction (X direction) (see FIG. 2) and spaced apart in the second direction, and a plurality of third conductive lines 130 spaced apart in the first and second directions. A two-layered pattern CPP2 is formed. The plurality of third conductive lines 130 may form a third conductive line layer 130L. The plurality of second stacked patterns CPP2 include a fifth electrode layer 141-2, a second selection device layer 143-2, a sixth electrode layer 145-2, a seventh electrode layer 147-2, and a second electrode layer 147-2. 2 variable resistance layers 149-2 and an eighth electrode layer 148-2 may be included.

In addition, a plurality of third gaps extending in the first direction and spaced apart in the second direction between each of the plurality of third conductive lines 130 and between each of the plurality of second stacked patterns CPP2 by an anisotropic etching process (GX2) can be formed.

In example embodiments, the anisotropic etching process may be performed until upper surfaces of the plurality of second conductive lines 120 are exposed. Although not shown, recesses (not shown) having a predetermined depth may be formed on the upper side of the plurality of second conductive lines 120 by the anisotropic etching process.

In other embodiments, the anisotropic etching process is performed until the upper surface of the fifth electrode layer line 141 - 2L is exposed, and then the fifth electrode layer line 141 is applied to the plurality of second conductive lines 120 . Parts of the fifth electrode layer line 141 - 2L exposed in the plurality of third gaps GX2 may be removed by performing an etching process having an etching selectivity of -2L, and accordingly, the plurality of second conductive lines ( 120) may be exposed.

Referring to FIG. 16I , upper surfaces of the plurality of second stacked patterns CPP2 (see FIG. 16H ) may be exposed by removing the third mask pattern 430 (see FIG. 16H ).

Thereafter, a third insulating layer 162 - 2 may be formed to fill the plurality of third gaps GX2 .

In example embodiments, the plurality of third gaps GX2 are filled by using an insulating material on the plurality of third conductive lines 130 and the plurality of second stacked patterns CPP2, and the plurality of third conductive The third insulating layer 162 - 2 may be formed by planarizing an upper portion of the insulating material until the upper surface of the line 130 is exposed.

By performing the above process, the memory device 100 may be completed.

The plurality of first stacking patterns CPP1 may become the plurality of first memory cells 140 - 1 , and the plurality of second stacking patterns CPP2 may become the plurality of second memory cells 140 - 2 . . Also, the plurality of first memory cells 140 - 1 may form the first memory cell layer MCL1 , and the plurality of first memory cells 140 - 1 may form the first memory cell layer MCL2 .

According to the method of manufacturing the memory device 100, a first patterning process using a first mask pattern 410 extending in a first direction and a second patterning process using a second mask pattern 420 extending in a second direction The process and the third patterning process using the third mask pattern 430 extending in the first direction may be sequentially performed. As a result, the plurality of first conductive lines 110 extending in the first direction, the plurality of second conductive lines 120 extending in the second direction, and the plurality of third conductive lines 130 extending in the first direction , a plurality of first memory cells 140-1, and a plurality of second conductive lines 120 respectively disposed at intersections between the plurality of first conductive lines 110 and the plurality of second conductive lines 120 A plurality of second memory cells 140 - 2 may be formed at intersections between the and the plurality of third conductive lines 130 .

According to the manufacturing method, since the plurality of memory cells 140-1 and 140-2 can be formed using only three patterning processes, the variable resistance layers 149-1 and 149-2 and / or the variable resistance layers 149-1 and 149-2 and/or the selection device layers 143-1 and 143-2 that may occur when the selection device layers 143-1 and 143-2 are exposed to an etching atmosphere ) can be prevented from deterioration or damage. In addition, the manufacturing cost of the memory device 100 can be reduced.

Fig. 17 is a block configuration diagram of a memory device according to an exemplary embodiment.

Referring to FIG. 17 , a memory device 800 may include a memory cell array 810, a decoder 820, a read/write circuit 830, an input/output buffer 840, and a controller 850. The memory cell array 810 may include at least one of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 200 illustrated in FIGS. 1 to 15 .

A plurality of memory cells in the memory cell array 810 may be connected to the decoder 820 through the word line WL and connected to the read/write circuit 830 through the bit line BL. The decoder 820 receives the external address ADD and can decode row addresses and column addresses to be accessed within the memory cell array 810 under the control of the controller 850 operating according to the control signal CTRL. there is.

The read/write circuit 830 receives data DATA from the input/output buffer 840 and the data line DL, and writes the data to a selected memory cell of the memory cell array 810 under the control of the controller 850. Alternatively, data read from a selected memory cell of the memory cell array 810 may be provided to the input/output buffer 840 under the control of the controller 850 .

18 is a block diagram of an electronic system according to example embodiments.

Referring to FIG. 18 , an electronic system 1100 may include a memory system 1110, a processor 1120, a RAM 1130, an input/output device 1140, and a power supply 1150. Also, the memory system 1110 may include a memory device 1112 and a memory controller 1114 . Meanwhile, although not shown in FIG. 18 , the electronic system 1100 may further include ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other electronic devices. . The electronic system 1100 may be implemented as a personal computer or as a portable electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), and a camera.

Processor 1120 may perform certain calculations or tasks. Depending on the embodiment, the processor 1120 may be a micro-processor or a central processing unit (CPU). The processor 1120 communicates with the RAM 1130, the input/output device 1140, and the memory system 1110 through a bus 1160 such as an address bus, a control bus, and a data bus. communication can be performed. Here, the memory system 1110 may include at least one of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 200 illustrated in FIGS. 1 to 15 .

In some embodiments, processor 1120 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The RAM 1130 may store data necessary for the operation of the electronic system 1100 . The RAM 1130 may include DRAM, mobile DRAM, SRAM, ReRAM, FRAM, MRAM, or PRAM.

The input/output device 1140 may include input means such as a keyboard, keypad, and mouse, and output means such as a printer and a display. The power supply 1150 may supply an operating voltage necessary for the operation of the electronic system 1100 .

In the above, the present invention has been described in detail with preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes are made by those skilled in the art within the technical spirit and scope of the present invention. this is possible

101, 102: substrate 110: first conductive line
120: second conductive line 130: third conductive line
140-1, 140-2: memory cell 143-1, 143-2: selection element layer
146-1, 146-2: heating electrode layer 149-1, 149-2: variable resistance layer

Claims (20)

a plurality of first conductive lines extending on a substrate in a first direction parallel to an upper surface of the substrate and separated from each other in a second direction crossing the first direction;
a plurality of second conductive lines extending in the second direction on the plurality of first conductive lines and separated from each other in the first direction;
a plurality of third conductive lines extending in the first direction on the plurality of second conductive lines and separated from each other in the second direction;
a plurality of first memory cells disposed at intersections of the plurality of first conductive lines and the plurality of second conductive lines, each including a first selection element layer and a first variable resistance layer; and
a plurality of second memory cells disposed at intersections of the plurality of third conductive lines and the plurality of second conductive lines, each including a second selection element layer and a second variable resistance layer;
Each of the first selection element layer and the second selection element layer includes a material layer having a different resistance based on a voltage applied to both terminals,
A first height of the first selection element layer along a third direction perpendicular to the first and second directions is different from a second height of the second selection element layer along the third direction. According to claim 1,
A difference between the threshold voltage of the first selection element layer and the threshold voltage of the second selection element layer is less than 10% of the threshold voltage of the first selection element layer. According to claim 1,
A difference between a threshold voltage of the first selection element layer and a threshold voltage of the second selection element layer is less than 0.5 V. According to claim 1,
The magnitude of the threshold voltage of the first selection element layer is 90% to 110% of the magnitude of the threshold voltage of the second selection element layer. According to claim 1,
The first height of the first selection element layer is greater than the second height of the second selection element layer. According to claim 5,
A word line select voltage is applied to the plurality of first conductive lines or the plurality of third conductive lines, and a cut-off voltage lower than the word line select voltage is applied to the plurality of second conductive lines. According to claim 5,
The second height of the second selection element layer is 50% to 90% of the first height of the first selection element layer. According to claim 1,
The first height of the first selection element layer is smaller than the second height of the second selection element layer. According to claim 8,
The first height of the first selection element layer is 50% to 90% of the second height of the second selection element layer. According to claim 8,
A memory device configured such that a word line select voltage is applied to the plurality of first conductive lines or the plurality of third conductive lines, and a cut-off voltage greater than the word line select voltage is applied to the plurality of second conductive lines. According to claim 1,
The first selection element layer and the second selection element layer have ovonic threshold switching characteristics. According to claim 1,
Each of the plurality of first memory cells further includes a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of first conductive lines;
Each of the plurality of second memory cells further includes a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of third conductive lines. According to claim 1,
Each of the plurality of first memory cells further includes a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of second conductive lines;
Each of the plurality of second memory cells further includes a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of second conductive lines. a plurality of first conductive lines extending on a substrate in a first direction parallel to an upper surface of the substrate and spaced apart from each other in a second direction crossing the first direction;
a plurality of second conductive lines extending in the second direction on the plurality of first conductive lines and spaced apart from each other in the first direction;
a plurality of third conductive lines extending in the first direction on the plurality of second conductive lines and spaced apart from each other in the second direction;
A first selection element layer disposed at an intersection of the plurality of first conductive lines and the plurality of second conductive lines and sequentially stacked in a third direction perpendicular to the first and second directions; a plurality of first memory cells including a variable resistance layer; and
a plurality of second selection element layers and a second variable resistance layer disposed at intersections of the plurality of third conductive lines and the plurality of second conductive lines and sequentially stacked in the third direction; contains a memory cell;
Each of the first selection element layer and the second selection element layer includes a material layer having a different resistance based on a voltage applied to both terminals,
The first selection element layer and the second selection element layer have ovonic threshold switching characteristics,
A thickness of the first selection element layer in the third direction is greater than a thickness of the second selection element layer in the third direction. According to claim 14,
The selection element layer and the variable resistance layer include at least one chalcogen element. According to claim 14,
The thickness of the second selection element layer is 50 to 90% of the thickness of the first selection element layer. According to claim 14,
A difference between a threshold voltage of the first selection element layer and a threshold voltage of the second selection element layer is less than 0.5 V. According to claim 14,
The thickness of the first selection element layer is 10 to 500 nm, and the thickness of the second selection element layer is 5 to 450 nm. According to claim 14,
Each of the plurality of first memory cells further includes a first heating electrode layer disposed between the first selection element layer and the first variable resistance layer;
Each of the plurality of second memory cells further includes a second heating electrode layer disposed between the second variable resistance layer and each of the plurality of third conductive lines. According to claim 14,
Each of the plurality of first memory cells further includes a first heating electrode layer disposed between the first variable resistance layer and each of the plurality of second conductive lines;
Each of the plurality of second memory cells further includes a second heating electrode layer disposed between the second selection element layer and the second variable resistance layer.

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