TW201730880A - Memory device including ovonic threshold switch adjusting threshold voltage thereof - Google Patents

Abstract

A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

Description

Memory device including bidirectional critical switch for adjusting threshold voltage

Embodiments of the present disclosure are directed to a memory device. More specifically, embodiments of the present disclosure are directed to a memory device having a cross-point structure.

As the size of electronic devices has shrunk, the accumulation of semiconductor memory devices has increased. Therefore, a three-dimensional cross-point memory device including a plurality of memory cells disposed at intersection points of two electrodes crossing each other has been studied to be scaled down. However, in the scaling down process, since the thickness of the layer used to form the three-dimensional cross-point array memory device is also reduced, the layer exposed to the high-temperature process can be easily damaged and degraded. Therefore, the electrical characteristics of the three-dimensional cross-point memory device may degrade the quality.

According to an example embodiment, a memory device may include: a substrate; a plurality of first conductive lines on which the plurality of first conductive lines are parallel to a top surface of the substrate Extending in the direction and spaced apart from each other in a second direction crossing the first direction; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines being in the second direction Extending and spaced apart from each other in a first direction; a plurality of third conductive lines above the plurality of second conductive lines, the plurality of third conductive lines extending in a first direction and in a second direction Separating; a plurality of first memory cells, each of the plurality of first memory cells at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines a first selection element layer and a first variable resistance layer; and a plurality of second memory cells at the plurality of second conductive lines and the plurality of third conductive lines At the respective intersections of the lines, the plurality of second Each memory unit contains a second selection element layer and the second variable resistance layer. The first height of the first selection element layer in a third direction perpendicular to the first direction and the second direction may be different from the second height of the second selection element layer in the third direction. The first variable resistance layer and the second variable resistance layer may be made of the same material, and the first selection element layer and the second selection element layer may be made of the same material.

According to an example embodiment, a memory device may include: a substrate; a plurality of first conductive lines, wherein the plurality of first conductive lines extend in a first direction parallel to a top surface of the substrate and Separating from each other in a second direction in which one direction intersects; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and in the first direction Separating from each other; a plurality of third conductive lines above the plurality of second conductive lines, the plurality of third conductive lines extending in a first direction and spaced apart from each other in a second direction; a plurality of first a memory unit, each of the plurality of first memory cells being included in a direction perpendicular to the first direction at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines And a first selection element layer and a first variable resistance layer sequentially stacked by the third direction in the second direction; and a plurality of second memory units in the plurality of second conductive lines and the plurality of At respective intersections of the three conductive lines, in the plurality of second memory cells Selecting one element contained in the second layer and the second variable resistance layer are sequentially stacked in the third direction. The thickness of the first selection element layer in the third direction may be greater than the thickness of the second selection element layer in the third direction. The first variable resistance layer and the second variable resistance layer may be made of the same material, and the first selection element layer and the second selection element layer may be made of the same material.

According to an example embodiment, a memory device may include: a substrate; a first word line layer disposed on the substrate; a common bit line layer disposed on the first word line a second word line layer disposed on the common bit line such that the common bit line layer is vertically located between the first word line layer and the second word line layer; the first memory unit layer (memory) The cell layer includes a first variable resistance layer vertically stacked and a first ovonic threshold switching layer, and the first memory cell layer is disposed in the vertical direction on the first word line layer and the common level And a second memory cell layer comprising a second variable resistance layer and a second bidirectional critical switching layer vertically stacked, wherein the second memory cell layer is disposed in the vertical direction on the second word line Between the layer and the common bit line layer. The first variable resistance layer and the second variable resistance layer may be made of the same material, and the first bidirectional critical switching layer and the second bidirectional critical switching layer may be made of the same material. The first thickness of the first bidirectional critical switching layer in the vertical direction may be different from the second thickness of the second bidirectional critical switching layer in the vertical direction.

The disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which FIG. However, the inventive concept may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein.

FIG. 1 is an equivalent circuit diagram illustrating a memory device according to an example embodiment.

As used herein, a semiconductor device may refer to any of the various devices such as those illustrated in Figures 1-3 and 7-15, and may also refer to, for example, a semiconductor chip (such as a semiconductor chip). For example, a memory chip and/or a logic chip formed on a die, a stack of semiconductor wafers, a semiconductor including one or more semiconductor wafers stacked on a package substrate A semiconductor package or a device comprising a plurality of packaged package-on-package devices. These devices may be formed using ball grid arrays, wire bonding, through substrate vias or other electrical connection elements, and may include, for example, volatility A memory device or a memory device of a non-volatile memory device.

As used herein, electronic devices may refer to such semiconductor devices, but may additionally include products having such devices, such as a memory module, a memory card, a hard disk drive containing additional components. (hard drive), or mobile phone, laptop, tablet, desktop, camera, or other consumer electronic device and many more.

Referring to FIG. 1, the memory device 100 can include lower word lines WL11 and WL12, upper word lines WL21 and WL22, common bit lines BL1, BL2, BL3, and BL4, first. The memory cell MC1 and the second memory cell MC2. The lower word lines WL11 and WL12 may extend in the X direction (eg, referred to as the first direction) and may be spaced apart from each other in the Y direction (eg, referred to as the second direction) that intersects the first direction. The upper word lines WL21 and WL22 may be separated from the lower word lines WL11 and WL12 in a Z direction perpendicular to the first direction and the second direction (for example, referred to as a third direction or a vertical direction), which may be first The directions extend and are spaced apart from each other in the second direction. The common bit lines BL1, BL2, BL3, and BL4 may be disposed between the lower word lines WL11 and WL12 and the upper word lines WL21 and WL22 to be in the third direction from the lower word lines WL11 and WL12 and the upper word lines. WL21 and WL22 are separated. The common bit lines BL1, BL2, BL3, and BL4 may extend in the second direction and may be spaced apart from each other in the first direction.

The first memory cell MC1 and the second memory cell MC2 may be respectively disposed between the common bit lines BL1, BL2, BL3, and BL4 and the lower word lines WL11 and WL12 and the common bit lines BL1, BL2, BL3, and BL4, respectively. Between the upper word lines WL21 and WL22. More specifically, the first memory cell MC1 may be disposed at respective intersections (or intersections) of the common bit lines BL1, BL2, BL3, and BL4 and the lower word lines WL11 and WL12, and may each be included The variable resistance layer ME for storing information and the selection element SW for selecting a memory unit. The first memory cell MC1 may be configured in two dimensions in the first direction and the second direction to form a first memory cell layer. The second memory cell MC2 may be disposed at respective intersections (or intersections) of the common bit lines BL1, BL2, BL3, and BL4 and the upper word lines WL21 and WL22, and may each include an information for storing information. A variable resistance layer ME and a selection element SW for selecting a memory unit. The second memory cell MC2 may be configured in two dimensions in the first direction and the second direction to form a second memory cell layer. The selection element SW may be referred to as a switching element or an access element.

The first memory cell MC1 and the second memory cell MC2 may be disposed to have the same structure in the third direction. As shown in FIG. 1 , in a situation where the first memory cell MC1 is located between the lower word line WL11 and the common bit line BL1, the variable resistance layer ME may be electrically connected to the common bit line BL1, and the selection element SW may be Electrically connected to the lower word line WL11, and the variable resistance layer ME can be connected in series with the selection element SW. Further, in a state where the second memory cell MC2 is located between the upper word line WL21 and the common bit line BL1, the variable resistance layer ME may be electrically connected to the upper word line WL21, and the selection element SW may be electrically connected to the common The bit line BL1 and the variable resistance layer ME may be connected in series with the selection element SW. However, aspects of the inventive concept are not limited to this case. In some embodiments, in each of the first memory cell MC1 and the second memory cell MC2, the configuration of the variable resistance layer ME and the selection element SW may be flipped differently than that shown in FIG. For example, the first memory cell MC1 and the second memory cell MC2 may be symmetrically arranged in the third direction with respect to the common bit lines BL1, BL2, BL3, and BL4. For example, in the first memory cell MC1, the variable resistance layer ME may be connected to the lower word lines WL11 and WL12, and the selection element SW may be connected to the common bit lines BL1, BL2, BL3, and BL4, and In the second memory cell MC2, the variable resistance layer ME may be connected to the upper word lines WL21 and WL22, and the selection element SW may be connected to the common bit lines BL1, BL2, BL3, and BL4 such that the first memory cell MC1 Each of the second memory cells MC2 and each of the second memory cells MC2 may be symmetrically arranged with respect to a corresponding one of the common bit lines BL1, BL2, BL3, and BL4.

Hereinafter, a method of operating the memory device 100 will be described.

For example, a voltage may be applied to any of the first memory cells MC1 via the lower word lines WL11 and WL12 and the upper word lines W21 and W22 and the common bit lines BL1, BL2, BL3, and BL4. The variable resistance layer ME of any one of the variable resistance layer ME or the second memory unit MC2 to allow current to flow in the variable resistance layer ME. For example, the variable resistance layer ME may include a phase change material that can be reversibly changed between the first state and the second state different from the first state, but is not limited thereto. In some embodiments, the variable resistance layer ME may comprise any kind of variable resistance material whose resistance value varies depending on the applied voltage. For example, according to the voltage applied to the variable resistance layer ME of the selected one of the first memory cell MC1 and the second memory cell MC2, the resistance value of the variable resistance layer ME may be in the first state and the second state. Reversible change between.

According to the resistance change of the variable resistance layer ME, digital data such as "0" or "1" may be stored in the first memory unit MC1 and the second memory unit MC2 and may be from the first memory unit MC1 and the second The memory cell MC2 is erased. For example, in the first memory cell MC1 and the second memory cell MC2, the high resistance state can be written as data "0" and the low resistance state can be written as data "1". Here, the resistance change operation from the high resistance state ("0" data state) to the low resistance state ("1" data state) can be referred to as a "set" operation, and the self-low resistance state ("1" Data state) The resistance change operation to the high resistance state ("0" data state) can be referred to as a "reset" operation. However, the example embodiments are not limited to digital data of a high resistance state ("0" data state) and a low resistance state ("1" data state). For example, memory cells MC1 and MC2 can store various resistance states.

One of the first memory cell MC1 and the second memory cell MC2 can be addressed by selecting one of the word lines WL11, WL12, WL21, and WL22 and one of the common bit lines BL1, BL2, BL3, and BL4. Any memory unit. The first memory cell MC1 can be programmed by applying a certain signal between the corresponding one of the word lines WL11, WL12, WL21, and WL22 and the corresponding one of the common bit lines BL1, BL2, BL3, and BL4. Corresponding to the second memory cell MC2, and by measuring the current value through the corresponding one of the common bit lines BL1, BL2, BL3, and BL4, can be read depending on the first memory cell MC1 and the second Information on the resistance value of the variable resistance layer ME of the corresponding one of the memory cells MC2.

In an example embodiment, the threshold voltage of the selection element SW of the first memory cell MC1 may be substantially the same as the threshold voltage of the selection element SW of the second memory cell MC2. For example, the magnitude difference between the threshold voltage of the selection element SW of the first memory cell MC1 and the threshold voltage of the selection element SW of the second memory cell MC2 may be smaller than that of the selection element SW of the first memory cell MC1. 10% of the threshold voltage. For example, the magnitude difference between the threshold voltage of the selection element SW of the first memory cell MC1 and the threshold voltage of the selection element SW of the second memory cell MC2 may be less than 0.5 V. Since the magnitude difference between the threshold voltage of the selection element SW of the first memory cell MC1 and the threshold voltage of the selection element SW of the second memory cell MC2 may be much smaller, the read/write operation may be improved or increased. Sensing margin, thereby reducing or preventing read/write failures. As a result, the memory device 100 can have improved reliability.

2 is a perspective cross-sectional view illustrating a memory device according to an example embodiment, and FIG. 3 is a cross-sectional view taken along lines AA' and BB' of FIG. 2, according to an example embodiment. Sectional view.

Referring to FIG. 2 and FIG. 3, the memory device 100 can include a first conductive line layer 110L, a second conductive line layer 120L, a third conductive line layer 130L, a first memory cell layer MCL1, and a second memory on the substrate 101. Unit layer MCL2.

The memory device 100 may further include an interlayer insulating layer 105 disposed on the substrate. The interlayer insulating layer 105 may include an oxide such as hafnium oxide and a nitride such as tantalum nitride, and the first conductive line layer 110L may be electrically separated from the substrate 101.

The first conductive line layer 110L may include a plurality of first conductive lines 110 extending in the first direction (X direction) and spaced apart from each other in the second direction (Y direction). The second conductive line layer 120L may be disposed on the first conductive line layer 110L, and may include a plurality of second conductive lines 120 extending in the second direction and spaced apart from each other in the first direction. The third conductive line layer 130L may be disposed on the second conductive line layer 120L, and may include a plurality of third conductive lines 130 extending in the first direction and spaced apart from each other in the second direction. The plurality of third conductive lines 130 and the plurality of first conductive lines 110 may be positioned at different levels in a third direction (Z direction), but may have substantially the same configuration.

In terms of operation of the memory device, the plurality of first conductive lines 110 and the plurality of third conductive lines 130 may correspond to word lines (eg, word lines WL11, Wl2, W21, and WL22 of FIG. 1) And the plurality of second conductive lines 120 may correspond to bit lines (eg, common bit lines BL1, BL2, BL3, and BL4 of FIG. 1). In some embodiments, the plurality of first conductive lines 110 and the plurality of third conductive lines 130 may correspond to bit lines (eg, common bit lines BL1, BL2, BL3, and BL4 of FIG. 1). And the plurality of second conductive lines 120 may correspond to word lines (eg, word lines WL11, Wl2, W21, and WL22 of FIG. 1). In a state where the plurality of first conductive lines 110 and the plurality of third conductive lines 130 correspond to word lines, the plurality of first conductive lines 110 may correspond to lower word lines (eg, FIG. 1 Lower word lines W11 and W12), and the plurality of third conductive lines 130 may correspond to upper word lines (eg, upper word lines W21 and W22 of FIG. 1). Because the plurality of second conductive lines 120 can be commonly used by the plurality of first conductive lines 110 (ie, lower word lines) and the plurality of third conductive lines 130 (ie, upper word lines) Shared, so the plurality of second conductive lines 120 may correspond to a common bit line.

Each of the plurality of first conductive lines 110, the plurality of second conductive lines 120, and the plurality of third conductive lines 130 may comprise a metal, a conductive metal nitride, a conductive metal oxide, or combination. In an example embodiment, each of the plurality of first conductive lines 110, the plurality of second conductive lines 120, and the plurality of third conductive lines 130 may include W, WN, Au, and Ag. , Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, alloys thereof or combinations thereof. In one embodiment, each of the plurality of first conductive lines 110, the plurality of second conductive lines 120, and the plurality of third conductive lines 130 may include a metal layer and A conductive barrier layer for covering at least a portion of the metal layer. The conductive barrier layer can comprise, for example, Ti, TiN, Ta, TaN, or a combination thereof.

The first memory cell layer MCL1 may include a plurality of first memory cells 140-1 spaced apart from each other in the first direction and the second direction and arranged in two dimensions (for example, the first memory cell of FIG. 1) MC1). The second memory cell layer MCL2 may include a plurality of second memory cells 140-2 spaced apart from each other in the first direction and the second direction and arranged in two dimensions (eg, the second memory cell of FIG. 1) MC2).

As shown in FIG. 2, the plurality of second conductive lines 120 may intersect the plurality of first conductive lines 110, and the plurality of third conductive lines 130 may cross the plurality of second conductive lines 120 . The first memory unit 140-1 may be disposed between the first conductive line layer 110L and the second conductive line layer 120L and intersect the plurality of first conductive lines 110 and the plurality of second conductive lines 120 Point. The second memory unit 140-2 may be disposed between the second conductive line layer 120L and the third conductive line layer 130L and the plurality of second conductive lines 120 and the plurality of third conductive lines 130 respectively intersect Point.

The first memory unit 140-1 and the second memory unit 140-2 may each have a pillar-like structure such as a square pillar, but are not limited thereto. For example, the first memory unit 140-1 and the second memory unit 140-2 may each have various pillar shapes such as a cylindrical pillar, an elliptical pillar, or a polygonal pillar. According to the forming method of the first memory unit 140-1 and the second memory unit 140-2, the lower portion of each of the first memory unit 140-1 and the second memory unit 140-2 may be larger than The upper portion (eg, the width of the lower portion is greater than the width of the upper portion), or the upper portion of each of the first memory unit 140-1 and the second memory unit 140-2 may be larger than the lower portion thereof (eg, The width of the upper portion is greater than the width of the lower portion). In some embodiments, the first memory unit 140-1 and the second memory unit 140-2 may each have substantially vertical sidewalls, and thus there is almost no difference in width between the lower portion and the upper portion. Although the first memory unit 140-1 and the second memory unit 140-2 are shown in other figures as having substantially vertical sidewalls in addition to FIGS. 2 and 3, the first memory unit 140 The lower portion of each of -1 and second memory unit 140-2 may be larger or smaller than its upper portion.

The first memory cells 140-1 may each include a first electrode layer 141-1, a first selection element layer 143-1, and a second electrode layer 145 which are sequentially disposed (or stacked) on the substrate 101. -1, a third electrode layer 147-1, a first variable resistance layer 149-1, and a fourth electrode layer 148-1. The second memory cells 140-2 may each include a fifth electrode layer 141-2, which is sequentially disposed (or stacked) on the first memory cell layer MCL1 (or the plurality of second conductive lines 120) The second element layer 143-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, the second variable resistance layer 149-2, and the eighth electrode layer 148-2 are selected. The first memory unit 1401-1 and the second memory unit 140-2 may have substantially the same structure and substantially the same material. Therefore, for the sake of brevity, the first memory unit 140-1 will be mainly described below.

The first variable resistance layer 149-1 (eg, the variable resistance layer ME of FIG. 1) may include a phase change material that is reversibly changeable between a first state and a second state depending on a heating time. For example, the variable resistance layer 149-1 may comprise a material whose phase is attributable to joule heat generated by the voltage applied to the two terminals of the variable resistance layer 149-1. It changes reversibly, and the electrical resistance of this material can change due to phase change. More specifically, the phase change material can exhibit a high resistance state in an amorphous phase and can exhibit a low resistance state in a crystalline phase. The high resistance state can be defined as a "0" state and the low resistance state can be defined as a "1" state, and the data can be stored in the first variable resistance layer 149-1.

In some embodiments, the first variable resistance layer 149-1 may comprise one or more elements from Group VI of the periodic table (eg, one or more chalcogen elements), and optionally from the third group, One or more chemical modifiers of Group IV and/or Group V. The first variable resistance layer 149-1 may include Ge-Sb-Te. The chemical composition notation represented by the hyphen (-) used herein means an element contained in a specific mixture or compound, and is used to indicate all chemical structures containing the indicated elements. For example, the Ge-Sb-Te material may comprise Ge ₂ Sb ₂ Te ₅ , Ge ₂ Sb ₂ Te ₇ , Ge ₁ Sb ₂ Te ₄ or Ge ₁ Sb ₄ Te ₇ .

The first variable resistance layer 149-1 may contain a plurality of phase change materials in addition to the Ge-Sb-Te material. For example, the first variable resistance layer 149-1 may include at least one of: Ge-Te, Sb-Te, In-Se, Ga-Sb, In-Sb, As-Te, Al- Te, Bi-Sb-Te (BST), In-Sb-Te (IST), Ge-Sb-Te, Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te, Sn- Sb-Bi, Ge-Te-O, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge- Te-Sn-Ni, Ge-Te-Sn-Pd, Ge-Te-Sn-Pt, In-Sn-Sb-Te, As-Ge-Sb-Te, and combinations thereof.

The elements constituting the first variable resistance layer 149-1 may have various stoichiometric ratios. The crystallization temperature, the melting temperature, the phase change rate depending on the crystallization energy, and the data retention characteristics can be controlled according to the stoichiometric ratio of the elements. (data retention characteristic).

The first variable resistance layer 149-1 may further contain at least one impurity element. The impurity element may include, for example, at least one of carbon (C), nitrogen (N), cerium (Si), bismuth (Bi), and tin (Sn). The operating current of the memory device 100 can be changed by an impurity element. Furthermore, the first variable resistance layer 149-1 may further comprise a metal. For example, the first variable resistance layer 149-1 may include at least one of aluminum (Al), gallium (Ga), zinc (Zn), titanium (Ti), chromium (Cr), manganese. (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pa), ruthenium (Hf), ruthenium (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), lead (Pb), and bismuth (Po). The metal can increase the electrical conductivity and thermal conductivity of the first variable resistance layer 149-1 to increase its crystallization rate, thereby increasing the setting stylization speed. Further, the metal can improve the data retention characteristics of the first variable resistance layer 149-1.

The first variable resistance layer 149-1 may comprise a multi-layered structure in which two or more layers having different physical properties are stacked. The number or thickness of the plurality of layers constituting the multilayer structure may not be limited. The barrier layer may be further interposed between the plurality of layers constituting the multilayer structure. A barrier layer can be used to prevent diffusion of material between the plurality of layers. When forming a subsequent layer of the plurality of layers, the barrier layer can reduce the diffusion of material contained in the previous layers of the plurality of layers.

The first variable resistance layer 149-1 may include a superlattice structure constructed of a plurality of layers including different materials and alternately stacked on each other. For example, the first variable resistance layer 149-1 may include a stacked structure in which a first layer formed of Ge-Te and a second layer formed of Sb-Te are alternately stacked in the stacked structure. However, the first layer and the second layer are not limited to this case, and may include various materials as described above.

The phase change material as the first variable resistance layer 149-1 can be described above, but the aspect of the inventive concept is not limited to this case. The first variable resistance layer 149-1 of the memory device 100 may include various materials having resistance change properties.

In some embodiments, in a state where the first variable resistance layer 149-1 includes a transition metal oxide, the memory device 100 may be a resistive random access memory (ReRAM) device. In the first variable resistance layer 149-1 containing the transition metal oxide, at least one electrical path can be established or eliminated by a stylization operation. The first variable resistance layer 149-1 may have a low resistance value when the electrical path is established and may have a high resistance value when the electrical path disappears. The memory device 100 can store data by using a difference in resistance values.

In the case where the first variable resistance layer 149-1 contains a transition metal oxide, the transition metal oxide may include Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr. At least one of them. For example, the first variable resistance layer 149-1 comprising a transition metal oxide may comprise a single layer or a plurality of layers formed by at least one of: Ta ₂ O _5-x , ZrO _2-x TiO _2-x , HfO _2-x , MnO _2-x , Y ₂ O _3-x , NiO _1-y , Nb ₂ O _5-x , CuO _1-y and Fe ₂ O _3-x . In the above materials, the value x and the value y may be selected within the range of 0 ≤ x ≤ 1.5 and 0 ≤ y ≤ 0.5, respectively, but are not limited thereto.

In other embodiments, the first variable resistance layer 149-1 includes a magnetic tunnel junction (MTJ) having two electrodes formed of a magnetic material and a dielectric layer interposed between the two electrodes. In the case of the structure, the memory device 100 may be a magnetic random access memory (MRAM) device.

One of the two electrodes may be a magnetization pinned layer, and the other of the two electrodes may be a magnetization free layer. The dielectric layer can be a tunnel barrier layer. The magnetized pinned layer may have a pinning magnetization direction, and the magnetization free layer may have a variable magnetization direction parallel or anti-parallel to the pinning magnetization direction of the magnetized pinned layer. The magnetization direction of the magnetized pinned layer and the magnetization free layer may be parallel to the surface of the tunnel barrier layer, but is not limited thereto. The magnetization pinning layer and the magnetization free layer may have a magnetization direction perpendicular to a surface of the tunnel barrier layer.

The first variable resistance layer 149-1 may have a first resistance value in a state where the magnetization direction of the magnetization free layer is parallel to the magnetization direction of the magnetization pinning layer. Alternatively, the first variable resistance layer 149-1 may have a second resistance value in a state where the magnetization direction of the magnetization free layer is antiparallel to the magnetization direction of the magnetization pinning layer. The memory device 100 can store data by using a difference between the first resistance value and the second resistance value. The magnetization direction of the magnetization free layer can be varied by the spin torque of the electrons in the stylized current.

The magnetized pinned layer and the magnetized free layer may comprise a magnetic material. The magnetized pinned layer may further comprise an antiferromagnetic material that fixes the magnetization direction of the ferromagnetic material in the magnetized pinned layer. The tunnel barrier layer may include an oxide having at least one of Mg, Ti, Al, MgZn, and MgB, but is not limited thereto.

The first selection element layer 143-1 (eg, the selection element SW of FIG. 1) can serve as a current control layer for controlling current flow. The first selection element layer 143-1 may comprise a layer of material whose resistance may vary depending on the voltage applied to its two terminals. For example, the first selection element layer 143-1 can include a layer of material having bidirectional critical switching (OTS) properties. In a state where the first selection element layer 143-1 includes a material layer having a bidirectional critical switching property, the first selection element layer 143-1 can maintain a high resistance state, wherein the threshold voltage is less than the threshold voltage of the first selection element layer 143-1 When a voltage is applied to the first selection element layer 143-1, the current hardly flows. When a voltage greater than the threshold voltage of the first selection element layer 143-1 is applied to the first selection element layer 143-1, the first selection element layer 143-1 may be in a low resistance state such that current begins to flow. When the current flowing through the first selection element layer 143-1 is less than the holding current, the first selection element layer 143-1 can be switched to the high resistance state. The bidirectional critical switching property of the first selection element layer 143-1 will be described in detail later with reference to FIG.

The first selection element layer 143-1 may comprise a chalcogenide material as a bidirectional critical switching material layer. The first selection element layer 143-1 may comprise one or more elements from Group VI of the periodic table (eg, chalcogen elements), and optionally one from Group III, Group IV, and/or Group V. Or a variety of chemical modifiers. The chalcogen element contained in the first selection element layer 143-1 may include sulfur (S), selenium (Se), and/or tellurium (Te). The chalcogenide can be characterized by the presence of divalent bonding and the absence of a pair of electrons. The divalent linkage can result in the formation of a chain and ring structure upon combining the chalcogenide to form the chalcogenide material, and the unshared electron pair can provide an electron source for forming a conducting filament. Trivalent modification of such as aluminum (Al), gallium (Ga), indium (In), germanium (Ge), tin (Sn), germanium (Si), phosphorus (P), arsenic (As), and antimony (Sb) The agent and the tetravalent modifier can enter the chain and ring structure of the chalcogen element and can affect the structural rigidity of the chalcogenide material. The structural stiffness of the chalcogenide material can result in the classification of the chalcogenide material into one of a critical switching material and a phase change material, depending on the ability to undergo crystallization or other structural reconfiguration.

In some embodiments, the first selection element layer 143-1 may comprise germanium (Si), tellurium (Te), arsenic (As), germanium (Ge), indium (In), or a combination thereof. For example, the first selection element layer 143-1 can comprise a germanium (Si) concentration of about 14%, a cerium (Te) concentration of about 39%, an arsenic (As) concentration of about 37%, and about 9% bismuth ( Ge) concentration, about 1% indium (In) concentration. Here, the percentage is an atomic percentage which amounts to 100% of the atoms constituting the element.

In some embodiments, the first selection element layer 143-1 may comprise germanium (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), or a combination thereof. For example, the first selection element layer 143-1 may comprise about 5% cerium (Si) concentration, about 34% cerium (Te) concentration, about 28% arsenic (As) concentration, about 11% bismuth ( Ge) concentration, sulfur (S) concentration of about 21%, and selenium (Se) concentration of about 1%.

In some embodiments, the first selection element layer 143-1 may comprise tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), antimony (Sb), or a combination thereof. For example, the first selection element layer 143-1 may comprise about 21% cerium (Te) concentration, about 10% arsenic (As) concentration, about 15% cerium (Ge) concentration, about 2% sulfur ( S) concentration, about 50% selenium (Se) concentration, and about 2% strontium (Sb) concentration.

In the memory device 100 according to example embodiments, the first selection element layer 143-1 is not limited to the bidirectional critical switching material, but includes various materials that can be used to select the device. For example, the first selection element layer 143-1 may include a diode, a tunnel junction, a bipolar junction transistor, or a mixed ionic-electronic conduction switch (MIEC).

The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may serve as an electrical path and may be formed of a conductive material. The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, each of the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may include a TiN layer, but is not limited thereto. situation. In some embodiments, each of the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may comprise a metal or a conductive metal nitrogen. And a conductive layer formed by the compound and at least one conductive barrier layer covering at least a portion of the conductive layer. The conductive barrier layer may include a metal oxide, a metal nitride, or a combination thereof, but is not limited thereto.

In some embodiments, the third electrode layer 147-1 and/or the fourth electrode layer 148-1 contacting the first variable resistance layer 149-1 may comprise a level sufficient to change the first variable resistance layer 149-1. The phase of the hot conductive material. For example, the third electrode layer 147-1 or the fourth electrode layer 148-1 may comprise a refractory metal, a refractory metal nitride, and/or a carbon-based conductive material. The third electrode layer 147-1 or the fourth electrode layer 148-1 may include, for example, TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN or a combination thereof. However, the third electrode layer 147-1 or the fourth electrode layer 148-1 is not limited to this case.

In some embodiments, a heating electrode layer may be further interposed between the first variable resistance layer 149-1 and the third electrode layer 147-1 or the first variable resistance layer 149-1 and the fourth Between the electrode layers 148-1. The heating electrode layer may comprise a conductive material capable of generating heat sufficient to change the phase of the variable resistance layer 149-1. For example, the heating electrode layer may comprise a refractory metal, a refractory metal nitride or a carbon-based conductive material. The heating electrode layer may include, for example, TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN or a combination thereof, but is not limited to this case.

Although the first variable resistance layer 149-1 is shown as being disposed on the first selection element layer 143-1 in FIGS. 2 and 3, the second electrode layer 145-1 and the third electrode layer 147-1 are inserted in The first variable resistance layer 149-1 is interposed between the first selection element layer 143-1, but the aspect of the inventive concept is not limited to this case. Unlike the case shown in FIGS. 2 and 3, the first selection element layer 143-1 is disposed on the first variable resistance layer 149-1, wherein the second electrode layer 145-1 and the third electrode layer 147-1 are inserted. Between the first selection element layer 143-1 and the first variable resistance layer 149-1, and the first variable resistance layer 149-1 is insertable into the first electrode layer 141-1 and the second electrode layer 145-1 between. For example, the first electrode layer 141-1 and/or the second electrode layer 145-1 contacting the first variable resistance layer 149-1 may include a phase capable of generating a phase sufficient to change the first variable resistance layer 149-1. Hot conductive material. Furthermore, the heating electrode layer may be further interposed between the first variable resistance layer 149-1 and the first electrode layer 141-1 and between the first variable resistance layer 149-1 and the second electrode layer 145-1.

The first electrode layer 141-1 and the fourth electrode layer 148-1 may be formed as appropriate. For example, the first electrode layer 141-1 and the fourth electrode layer 148-1 may be omitted. However, at least one of the first electrode layer 141-1 and the fourth electrode layer 148-1 may be respectively disposed on one of the first conductive line 110 and the second conductive line 120 and the first selection element layer 143-1 Between and/or between one of the first conductive line 110 and the second conductive line 120 and the first variable resistance layer 149-1, so as to prevent being attributed to the first conductive line 110 and the second conductive line 120 Between one of the first selection element layers 143-1 and/or one of the first conductive line 110 and the second conductive line 120 and the first variable resistance layer 149-1 Pollution or contact failure.

At least one of the second electrode layer 145-1 and the third electrode layer 147-1 may be necessarily disposed between the first selection element layer 143-1 and the first variable resistance layer 149-1. When the first selection element layer 143-1 is based on a bidirectional critical switching property, the first selection element layer 143-1 may comprise a chalcogenide material in an amorphous state. According to the trend of scaling down the memory device 100, the thickness of the variable resistance layer 149-1, the selection element layer 143-1, the second electrode layer 145-1, and the third electrode layer 147-1 can be reduced, and Width and the distance between them. Therefore, at the time of operation of the memory device 100, the heating electrode layer (or the third electrode layer 147-1 when the additional heating electrode layer is not formed) may be heated to cause the phase of the first variable resistance layer 149-1 The change causes the adjacent first selection element layer 143-1 to be thermally affected. For example, the first selection element layer 143-1 may be partially crystallized by heat from the adjacent first variable resistance layer 149-1, thereby causing degradation in quality in the first selection element layer 143-1 or damage. Therefore, at least one of the second electrode layer 145-1 and the third electrode layer 147-1 may be necessarily disposed between the first selection element layer 143-1 and the first variable resistance layer 149-1 to prevent Or reducing the degradation quality or damage in the first selection element layer 143-1.

The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may be formed of various materials. The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may each have a varying thickness depending on the configuration of the heating electrode layer. For example, in a state where the heating electrode layer is interposed between the third electrode layer 147-1 and the variable resistance layer 149-1, the third electrode layer 147-1 and the second electrode layer 145-1 may be formed as Thick enough to prevent heat transfer from the heating electrode layer to the first selection element layer 143-1. When the heating electrode is not formed and the third electrode layer 147-1 is formed of a conductive material capable of generating heat sufficient to change the phase of the first variable resistance layer 149-1, the second electrode layer 145-1 may be formed as Thick enough to prevent heat transfer from the third electrode layer 147-1 to the first selection element layer 143-1. For example, the second electrode layer 145-1 and the third electrode layer 147-1 may have a thickness of 10 nm to 100 nm, but are not limited thereto. Further, each of the second electrode layer 145-1 and the third electrode layer 147-1 may have at least one thermal barrier layer for blocking heat. In a state where each of the second electrode layer 145-1 and the third electrode layer 147-1 has two or more than two thermal barrier layers, the second electrode layer 145-1 and the third electrode layer 147- Each of 1 may have a stacked structure in which a thermal barrier layer and an electrode material layer are alternately stacked.

The first insulating layer 162-1 may be disposed between the plurality of first conductive lines 110. The first insulating layer 162-1 and the third insulating layer 163 may be disposed between the first memory cells 140-1 of the first memory cell layer MCL1. For example, the first insulating layer 162-1 may be disposed between the first memory cells 140-1 disposed in the second direction (Y direction), and the third insulating layer 163 may be disposed in the first direction ( Between the first memory cells 140-1 disposed on the X direction). The third insulating layer 163 may be disposed between the second conductive lines 120 disposed in the first direction. The second insulating layer 162-2 may be disposed between the second memory cells 140-2 of the second memory cell layer MCL2 disposed in the second direction, and may be disposed in the third conductive region disposed in the second direction Between lines 130. The first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may be formed of the same insulating material, or the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163. At least one of the materials may be formed of a material different from the other of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163. Each of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may be formed of an oxide or a nitride, and a memory cell (or component) of each memory cell layer may be ) Electrically separated from each other. In some embodiments, at least one of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may be replaced by an air space. For example, at least one of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may not be formed, thereby being between the first memory unit 140-1 and in the second A gap is formed between the memory cells 140-2. In the case of forming a void, an insulating liner having a certain thickness may be disposed between the void and at least one of the first memory unit 140-1 and the second memory unit 140-2.

As illustrated in FIG. 3, the first selection element layer 143-1 of the first memory unit 140-1 may have a first height (or thickness) H1 in the third direction (the Z direction of FIG. 2), and the second memory The second selection element layer 143-2 of the body unit 140-2 may have a second height (or thickness) H2 that is smaller than the first height H1 in the third direction. In some embodiments, the first height H1 of the first selection element layer 143-1 of the first memory unit 140-1 may range from 10 nm to 500 nm, and the second of the second memory unit 140-2 The second height H2 of the selection element layer 143-2 may range from 5 nm to 450 nm, but is not limited thereto.

In some embodiments, the second height H2 of the second selection element layer 143-2 may range from, for example, 50% to 90% of the first height H1 of the first selection element layer 143-1, but is not limited thereto. This situation.

The first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 may be controlled such that the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 is The magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 is substantially the same.

In some embodiments, the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 may be controlled such that the first threshold voltage of the first selection element layer 143-1 The magnitude difference between V _T1 and the second threshold voltage V _{T2 of the} second selection element layer 143-2 is less than 0.5 V. For example, the magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 may be less than or less than 0.5 V greater than the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1.

In some embodiments, the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 may be controlled such that the second threshold voltage of the second selection element layer 143-2 The magnitude of V _T2 ranges from, for example, 80% to 120% of the magnitude of the first threshold voltage V _T1 of the first selection element 143-1. The magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 may range from, for example, 90% to 110% of the magnitude of the first threshold voltage V _T1 of the first selection element 143-1.

The magnitude of the magnitude of the second threshold voltage V _T2 at the second selection element layer 143-2 is, for example, 80% to 120% of the magnitude of the first threshold voltage V _T1 of the first selection element 143-1. Next, the difference between the electrical properties of the first memory cell MC1 and the electrical properties of the second memory cell MC2 can be reduced, thereby increasing the sensing margin of the read/write operation of the memory device 100.

Hereinafter, the relationship between the threshold voltage and the electrical properties of the selection element layers 143-1 and 143-2 having the bidirectional critical switching (OTS) attribute will be described in detail with reference to FIGS. 4 to 6.

4 is a schematic diagram illustrating a voltage-current curve 40 of a bidirectional critical switching element representing bidirectional critical switching (OTS) properties. Figure 4 schematically illustrates the current flowing through the bidirectional critical switching element in response to the voltage applied to the two terminals of the bidirectional critical switching element.

Referring to FIG. 4, the first curve 41 may represent a voltage-current relationship in a state where current does not flow through the bidirectional critical switching element. Here, the bidirectional critical switching element can be used as a switching element having a threshold voltage V _T at a first voltage level 43. When the voltage gradually increases from the state where the current and the voltage are at zero, the current can hardly flow through the bidirectional critical switching element until the voltage reaches the threshold voltage V _T (ie, the first voltage level 43). However, once the voltage exceeds the threshold voltage V _T , the current flowing through the bidirectional critical switching element can be sharply increased, and the voltage applied across the bidirectional critical switching element can be reduced to the second voltage level 44 (or the saturation voltage Vs). ).

The second curve 42 may represent a voltage-current relationship in a state where current flows through the bidirectional critical switching element. As the current flowing through the bidirectional critical switching element increases more than the first current level 46, the voltage applied across the bidirectional critical switching element may increase slightly above the second voltage level 44. For example, although the current flowing through the bidirectional critical switching element increases significantly from the first current level 46 to the second current level 47, the voltage applied across the bidirectional critical switching element can be from the second voltage level. 44 increased slightly. For example, once current flows through the bidirectional critical switching element, the voltage applied across the bidirectional critical switching element can be maintained at approximately the saturation voltage Vs (ie, the second voltage level 44). When the current is reduced to less than the sustain current level (ie, less than the first current level 46), the bidirectional critical switching element can be switched back to the resistive state, thereby effectively blocking the current until the voltage is increased to the threshold voltage V. _T so far.

5A and 5B are schematic diagrams illustrating an operation method of a memory device having a stacked cross-point structure, according to an example embodiment.

5A and 5B illustrate a read operation or a write operation of a memory device having a stacked cross-point structure in which a first lower memory cell MC11 and a second lower memory cell MC12 and The first upper memory cell MC21 and the second upper memory cell MC22 are respectively disposed between the common bit line BL and the first lower word line WL11 and the second lower word line WL12 below the common bit line BL. And between the common bit line BL and the first upper word line WL21 and the second upper word line WL22 above the common bit line BL.

Referring to FIG. 5A, the first lower memory cell MC11 at the intersection of the first lower word line WL11 and the common bit line BL may be selected. In order to select the first lower word line WL11, a lower voltage Vlow (eg, a bit line selection voltage or a disable voltage) may be applied to the common bit line BL and the word line selection voltage V _{WL (Sel) may be} applied. To the first lower word line WL11.

For example, a write operation may be performed to store data in the first lower memory unit MC11 (for example, a write operation may be performed by a reset operation and a set operation), and a read operation may be performed to read The data stored in the first lower memory cell MC11 is taken. A word line select voltage V _WL(Sel) having a relatively higher value may be applied to the selected first lower word line WL11, and a lower voltage Vlow having a relatively lower value may be applied to the common bit line BL, therefore, a first switching voltage having a difference (V _WL(Sel) - Vlow) can be applied across the first lower memory cell MC11. The magnitude of the first switching voltage may be greater than the magnitude of the threshold voltage of the selection element SW having the bidirectional critical switching property. Therefore, the selection element SW of the first lower memory cell MC11 can be turned on, so that the first current I _MC11 flows through the variable resistance layer R of the first lower memory cell MC11. In one embodiment, the magnitude of the first current I _MC11 may vary based on the resistance state (eg, set or reset) of the variable resistance layer R of the first lower memory cell MC11.

Meanwhile, the word line unselected voltage V _{WL (Unsel) may be} applied to the unselected second lower word line WL12 and the first upper word line WL21 and the second upper word line WL22. Therefore, an off voltage having a difference (V _{WL (Unsel)} - Vlow) can be applied across the unselected memory cells MC12, MC21, and MC22. The magnitude of the turn-off voltage may be less than the magnitude of the threshold voltage of the select element SW having the bidirectional critical switching property, so the select element SW may not be turned on. As a result, current may not flow through the variable resistance layer R of the unselected memory cells MC12, MC21, and MC22.

Referring to FIG. 5B, the first upper memory cell MC21 at the intersection of the first upper word line WL21 and the common bit line BL may be selected. In order to select the first upper memory cell MC21, a lower voltage Vlow may be applied to the common bit line BL and a word line selection voltage V _{WL (Sel) may be} applied to the first upper word line WL21. Therefore, a second switching voltage having a difference voltage (V _WL(Sel) - Vlow) can be applied across the first upper memory cell MC21. The magnitude of the second switching voltage may be greater than the threshold voltage of the selection element SW having the bidirectional critical switching property. Therefore, the selection element SW of the first upper memory cell MC21 can be turned on, so that the second current I _MC21 flows through the variable resistor R of the first upper memory cell MC21.

5A and 5B, the magnitude of the first switching voltage applied across the selected first lower memory cell MC11 may be equal to the second switching applied across the selected first upper memory cell MC21. The magnitude of the voltage. However, the direction of the first current I _MC11 flowing through the first lower memory cell MC11 may be different from the direction of the second current I _MC21 flowing through the first upper memory cell MC21. Therefore, the amount of the first current I _MC11 flowing through the first lower memory cell MC11 may be different from the amount of the second current I _MC21 flowing through the first upper memory cell MC21.

For example, a relatively high voltage may be applied to the first lower word line WL11 relative to the select element SW of the first lower memory cell MC11, and may be relative to the select element SW of the first upper memory cell MC21 A relatively high voltage is applied to the first upper word line WL21. Therefore, the selection element SW of the first lower memory cell MC11 and the selection element SW of the first upper memory cell MC21 can respectively be subjected to an electric field in different directions. The influence or effect caused by the electric field in different directions will be described with reference to FIG.

Figure 6 illustrates a voltage-current graph 60 for applying a positive voltage and a negative voltage to a bidirectional critical switching element, respectively.

Referring to Fig. 6, in the bidirectional critical switching element of the first experimental example 62 having different sizes and the bidirectional critical switching element of the second experimental example 64, it has been found that different voltage-current distributions are obtained when a positive voltage and a negative voltage are applied. (voltage-current profile). More specifically, the bidirectional critical switching element of the first experimental example 62 has a first threshold voltage 56 (V ₁ ) in a period of a positive voltage and a second threshold voltage 58 (V ₂ ) in a period of a negative voltage. It has been clearly found that the magnitude of the first threshold voltage 56 (V ₁ ) is greater than the magnitude of the second threshold voltage 58 (V ₂ ).

For example, the current flowing through the selection element SW and the threshold voltage of the selection element SW may vary depending on the direction of the electric field acting on the selection element SW. In FIGS. 5A and 5B, even if the selection voltage V _{WL (Sel)} having the same magnitude is applied to the first lower word line WL11 and the first upper word line WL21, the first lower word line is connected. The first lower memory cell MC11 of the WL11 and the first upper memory cell MC21 connected to the first upper word line WL21 may also have different current distributions and different threshold voltages from each other.

This phenomenon can be understood as caused by the asymmetric defect density and composition distribution in the selection element SW. For example, the selection element SW having a bidirectional critical switching property may comprise a chalcogenide material. In a switching mechanism of a chalcogenide material, when a high electric field is applied to the chalcogenide material, it is known that the electron trap sites in the chalcogenide material are unevenly distributed. , causing electrons to move at relatively high speeds along the electron trap site.

Furthermore, in the case where a large number of defects are generated in the selection element SW, the density of the electron trap sites can be increased. Therefore, in even a small electric field, electrons can still move along the electron trap sites, so that the threshold voltage of the selection element SW becomes reduced.

Referring again to FIGS. 2 and 3, the first height H1 of the first selection element layer 143-1 of the first memory unit 140-1 may be greater than the second selection element layer 143-2 of the second memory unit 140-2. The second height H2. Such a structure can be formed as follows: the first height H1 and the second height H2 are controlled in consideration of the defect density in the first selection element layer 143-1 and the second selection element layer 143-2, so that the first selection element The magnitude of the threshold voltage of layer 143-1 is substantially equal to the magnitude of the threshold voltage of second select element layer 143-2.

The defect density of the first selection element layer 143-1 located at the first level above the substrate 101 may be different from the defect density of the second selection element layer 143-2 positioned at the second level above the substrate 101. Here, the second level means a position farther from the substrate 101 in the third direction (Z direction) than the first level. For example, it means that the first selection element layer 143-1 is closer to the top surface of the substrate 101 than the second selection element layer 143-2.

The first selection element layer 143-1 at the first level may be exposed to the process environment for a long time, such as a deposition process and/or etching to form a subsequent layer, compared to the second selection element layer 143-2 at the second level. Process. In such a process environment, heat may be supplied from a chuck below the substrate 101 or from a heater to maintain a processing temperature ranging from tens of degrees Celsius to hundreds of degrees Celsius. Therefore, the first selection element layer 143-1 at the first level may be exposed to the deposition environment and/or the etching environment for a long time under a high temperature atmosphere compared to the second selection element layer 143-2 at the second level. As a result, the first selection element layer 143-1 can be easily damaged due to prolonged exposure to the deposition environment and/or the etching environment compared to the second selection element layer 143-2, such that the first level at the first level The defect density of the selection element layer 143-1 may be greater than the defect density of the second selection element layer 143-2 at the second level.

As described above, according to the switching mechanism of the selection element layers 143-1 and 143-2, in the case where the defect density of the first selection element layer 143-1 is larger than the defect density of the second first selection element layer 143-2, The threshold voltage of the first selection element layer 143-1 at the first level may be smaller in magnitude than the threshold voltage of the second selection element layer 143-2 at the second level. The magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 may cause less sensing margin in the write operation and/or the read operation, This induces a failure in the write operation and/or the read operation of the memory device 100.

According to the example embodiment as described above, the first height H1 of the first selection element layer 143-1 of the first memory unit 140-1 and the second selection element layer 143 of the second memory unit 140-2 may be controlled. The second height H2 of -2 is such that the magnitude of the threshold voltage of the first selection element layer 143-1 is substantially the same as the magnitude of the threshold voltage of the second selection element layer 143-2.

For example, because the first height H1 of the first selection element layer 143-1 of the first memory unit 140-1 is greater than the second height H2 of the second selection element layer 143-2 of the second memory unit 140-2. , so even if the switching voltage applied to the first selection element layer 143-1 is the same as the switching voltage applied to the second selection element layer 143-2, the magnitude of the electric field acting on the first selection element layer 143-1 is less than the effect The magnitude of the electric field of the second selection element layer 143-2. Therefore, in the case where the first selection element layer 143-1 contains a large defect density, the threshold voltage of the first selection element layer 143-1 can be prevented from being attributed to the reduction of the defect, and the first selection element layer 143 can be reduced. The difference between the threshold voltage of 1 and the threshold voltage of the second selection element layer 143-2.

Furthermore, the presence of the difference between the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 may be a result of the application to the first selection element layer 143- The first height H1 and the second height H2 are controlled by the direction of the electric field of the first and second selection element layers 143-2 such that the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 Essentially the same.

As described with reference to FIGS. 5A, 5B, and 6, when a positive voltage is applied to the first selection element layer 143-1 and the second selection element layer 143-2, when a negative voltage is applied to the first selection When the element layer 143-1 and the second selection element layer 143-2 are used, it has been found that the first selection element layer 143-1 and the second selection element layer 143-2 have a lower threshold voltage. Therefore, in the general case where the first selection element layer 143-1 and the second selection element layer 143-2 have the same height, when a negative voltage is applied to the first selection element layer 143-1 and a positive voltage is applied to the second When the element layer 143-2 is selected, the threshold voltage of the first selection element layer 143-1 (eg, 58 (V ₂ ) of FIG. 6) may be smaller in magnitude than the threshold voltage of the second selection element layer 143-2 (eg, , 56 (V ₁ ) of Fig. 6). For example, when a relatively lower voltage is applied to the second conductive line 120 (eg, the common bit line BL) and a relatively higher voltage is applied to the first conductive line 110 (eg, the first lower word line WL11) And the third conductive line 130 (eg, the first upper word line WL21) (ie, when a disable voltage is applied to the second conductive line 120 and a word line select voltage greater than the inhibit voltage is applied to the first conductive The line 110 and the third conductive line 130), the threshold voltage of the first selection element layer 143-1 (eg, 58 (V ₂ ) of FIG. 6) may be smaller than the threshold of the second selection element layer 143-2. Voltage (for example, 56 (V ₁ ) of Fig. 6).

According to the example embodiment as described above, since the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, when a negative voltage is applied to the first selection element When the layer 143-1 and a positive voltage are applied to the second selection element layer 143-2, the electric field acting on the first selection element layer 143-1 may be smaller in magnitude than the electric field acting on the second selection element layer 143-2. . Therefore, the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 can be reduced, and the electrical properties of the first memory unit 140-1 and the second memory can be reduced. The difference in electrical properties of body unit 140-2.

As a result, since the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 is reduced, the writing operation and/or the reading operation of the memory device 100 can be increased. The sensing margin in and can prevent or reduce the write operation and/or read operation of the memory device 100 due to the failure of the sensing margin reduction. Therefore, the reliability of the memory device 100 can be improved.

7 through 13 are cross-sectional views illustrating memory devices 100A, 100B, 100C, 100D, 100E, 100F, and 100G, respectively, and illustrating lines A-A' and B-B along FIG. 2, according to an example embodiment. 'The cross section taken. In the embodiments related to FIGS. 7 through 13, the same elements as those described in the embodiments of FIGS. 1 through 6 will be denoted by the same drawing element symbols or the same reference designating symbols.

Referring to FIG. 7, in the memory device 100A according to an example embodiment, the first height H1A of the first selection element layer 143-1 of the first memory unit 140-1 is smaller than the second level of the second memory unit 140-2. The second height H2A of the element layer 143-2 is selected. The first height H1A of the first selection element layer 143-1 and the second height H2A of the second selection element layer 143-2 may be controlled such that the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 is The magnitude of the second critical V _T2 of the second selection element layer 143-2 is substantially the same. For example, the magnitude of the second critical V _T2 of the second selection element layer 143-2 may be, for example, 80% of the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 to 120%, preferably 90% to 110%.

In some embodiments, the first height H1A of the first selection element layer 143-1 and the second height H2A of the second selection element layer 143-2 may be controlled such that the first threshold voltage of the first selection element layer 143-1 The magnitude difference between V _T1 and the second critical V _{T2 of the} second selection element layer 143-2 is in the range of less than 0.5 V.

In some embodiments, the first height H1A of the first selection element layer 143-1 may range from, for example, 5 nm to 450 nm, and the second height H2A of the second selection element layer 143-2 may be (eg, ) 10 nm to 500 nm, but is not limited to this case. For example, the first height H1A of the first selection element layer 143-1 may range from 50% to 90% of the second height H2A of the second selection element layer 143-2, but is not limited thereto.

As described with reference to FIGS. 5A, 5B, and 6, when a positive voltage is applied to the first selection element layer 143-1 and the second selection element layer 143-2, when a negative voltage is applied to the first selection When the element layer 143-1 and the second selection element layer 143-2 are used, it has been found that the first selection element layer 143-1 and the second selection element layer 143-2 have a lower threshold voltage. Therefore, in the general case where the first selection element layer 143-1 and the second selection element layer 143-2 have the same height, when a positive voltage is applied to the first selection element layer 143-1 and a negative voltage is applied to the second When the element layer 143-2 is selected, the threshold voltage of the second selection element layer 143-2 may be smaller in magnitude than the threshold voltage of the first selection element layer 143-1 in consideration of the direction of the electric field. For example, when a relatively higher voltage is applied to the second conductive line 120 (eg, the common bit line BL) and a relatively lower voltage is applied to the first conductive line 110 (eg, the first lower word line WL11) And the third conductive line 130 (eg, the first upper word line WL21) (ie, when a disable voltage is applied to the second conductive line 120 and a word line select voltage less than the inhibit voltage is applied to the first conductive When the line 110 and the third conductive line 130 are), the threshold voltage of the second selection element layer 143-2 may be smaller than the threshold voltage of the first selection element layer 143-1.

According to an example embodiment, since the second height H2A of the second selection element layer 143-2 is greater than the first height H1A of the first selection element layer 143-1, when a positive voltage is applied to the first selection element layer 143-1 and When a negative voltage is applied to the second selection element layer 143-2, the electric field acting on the second selection element layer 143-2 may be smaller in magnitude than the electric field acting on the first selection element layer 143-1. For example, the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 may be reduced, and the electrical properties of the first memory unit 140-1 may be reduced. The difference in electrical properties of the two memory cells 140-2.

As a result, since the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 is reduced, the writing operation and/or the reading operation of the memory device 100A can be increased. The sensing margin in and can prevent or reduce the write operation and/or read operation of the memory device 100A due to the failure of the sensing margin reduction. Therefore, the reliability of the memory device 100A can be improved.

Referring to FIG. 8, in a memory device 100B according to an example embodiment, a first inner spacer 152-1 may be formed on a sidewall of the first memory unit 140-1, and a second internal spacer 152. -2 may be formed on the sidewall of the second memory unit 140-2. The first inner spacer 152-1 may cover the first electrode layer 141-1 of the first memory unit 140-1 and the sidewall of the first selection element layer 143-1, and the second inner spacer 152-2 may cover the first The sidewalls of the fifth electrode layer 141-2 and the second selection element layer 143-2 of the two memory cells 140-2. The first inner spacer 152-1 and the second inner spacer 152-2 may enclose the sidewalls of the first memory unit 140-1 and the second memory unit 140-2 to respectively protect the first memory unit 140-1 And the second memory unit 140-2 preferably protects the first selection element layer 143-1 and the second selection element layer 143-2, respectively. For example, each of the first inner spacer 152-1 and the second inner spacer 152-2 may comprise an insulating material.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIG. 8, the aspect of the inventive concept is not limited to this case. For example, the first height H1 of the first selection element layer 143-1 is smaller than the second height H2 of the second selection element layer 143-2.

Although the first electrode layer 141-1 and the fifth electrode layer 141-2 have the same thickness as illustrated in FIG. 8, the aspect of the inventive concept is not limited to this case. For example, the thickness of the first electrode layer 141-1 is greater or smaller than the thickness of the fifth electrode layer 141-2.

In some embodiments, the first electrode layer 141-1, the fifth electrode layer 141-2, and the first selection element layer 143-1 and the second selection element layer 143-2 may be formed by a damascene process. The second electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, the sixth electrode layer 145-2, the seventh electrode layer 147-2, and the eighth layer can be formed by an etching process. The electrode layer 148-2 and the first variable resistance layer 149-1 and the second variable resistance layer 149-2. Therefore, the first electrode layer 141-1, the fifth electrode layer 141-2, and the first selection element layer 143-1 and the second selection element layer 143-2 may each have a width (eg, in the first direction or the second direction) Upper) a narrower structure down.

In some embodiments, when the first electrode layer 141-1 and the first selection element layer 143-1 are formed by a damascene process, the first inner spacer 152-1 may be formed in a trench (not shown). On the sidewalls, and then the first electrode layer 141-1 and the first selection element layer 143-1 may be sequentially formed in the trenches having the first internal spacers 152-1 to fill the trenches. The second electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, and the first variable resistance layer 149-1 may be formed on the first selection element layer 143-1. The fifth electrode layer 141-2 and the second selection element layer 143-2 may be formed by a process similar to the process of forming the first electrode layer 141-1 and the first selection element layer 143-1.

Referring to FIG. 9, in a memory device 100C according to an example embodiment, a first upper spacer 155-1 may be formed on a sidewall of the first memory unit 140-1, and a second upper spacer 155. -2 may be formed on the sidewall of the second memory unit 140-2. The upper spacer 155-1 may cover the sidewall of the first variable resistance layer 149-1 of the first memory unit 140-1, and the second upper spacer 155-2 may cover the second memory unit 140-2 The sidewall of the second variable resistance layer 149-2. The first upper spacer 155-1 and the second upper spacer 155-2 may enclose the sidewalls of the first memory unit 140-1 and the second memory unit 140-2 to respectively protect the first memory unit 140-1 And the second memory unit 140-2 preferably protects the first variable resistance layer 149-1 and the second variable resistance layer 149-2, respectively. For example, each of the first upper spacer 155-1 and the second upper spacer 155-2 may comprise an insulating material.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIG. 9, the aspect of the inventive concept is not limited to this case. For example, the first height H1 of the first selection element layer 143-1 is smaller than the second height H2 of the second selection element layer 143-2.

In some embodiments, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed by a damascene process, and the first electrode layer 141-1 and the second electrode may be formed by an etching process. Electrode layer 145-1, third electrode layer 147-1, fourth electrode layer 148-1, first selection element layer 143-1 and second selection element layer 143-2, and fifth electrode layer 141-2, sixth Electrode layer 145-2, seventh electrode layer 147-2, and eighth electrode layer 148-2. Therefore, the first variable resistance layer 149-1 and the variable resistance layer 149-2 may each have a structure in which the width (for example, in the first direction or the second direction) is narrower downward.

In some embodiments, when the first variable resistance layer 149-1 is formed by a damascene process, the first upper spacers 155-1 may be formed on sidewalls of the trenches (not shown), and then The first variable resistance layer 149-1 is formed in the trench having the first upper spacer 155-1 to fill the trench. The second variable resistance layer 149-2 can be formed by a process similar to the process of forming the first variable resistance layer 149-1.

In an example embodiment, the memory device (not shown) may include a plurality of first memory cells 140-1 and a plurality of second memory cells 140-2. Each of the first memory cells 140-1 may include a first internal spacer 152-1 formed on a sidewall of the first selection element layer 143-1 and a first variable resistance layer 149-1 formed on the first variable resistance layer 149-1 A first upper spacer 155-1 on the side wall. Each of the second memory cells 140-2 may include a second internal spacer 152-2 formed on a sidewall of the second selection element layer 143-2 and a second variable resistance layer 149-2 formed on the second variable resistance layer 149-2. A second upper spacer 155-2 on the side wall.

Referring to FIG. 10, in the memory device 100D according to example embodiments, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "L" sectional shape. Specifically, the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, and the first selection element layer 143 may be formed by an etching process. 1 and the second selection element layer 143-2 and the fifth electrode layer 141-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, and the eighth electrode layer 148-2, and can be fabricated by a damascene process The first variable resistance layer 149-1 and the second variable resistance layer 149-2 are formed.

The first upper spacers 155-1 and the second upper spacers 155-2 may be formed on sidewalls of the first variable resistance layer 149-1 and sidewalls of the second variable resistance layer 149-2, respectively. Since the first variable resistance layer 149-1 and the second variable resistance layer 149-2 have an "L" sectional shape, the first upper spacers 155-1 and the second upper spacers 155-2 may be formed as Asymmetric structure.

According to an exemplary process for forming the first variable resistance layer 149-1 and the second variable resistance layer 149-2, on each of the third electrode layer 147-1 and the seventh electrode layer 147-2 An insulating layer is formed, and a trench can be formed in the insulating layer. The trench may be formed to overlap with each of the adjacent first selection element layer 143-1 and the adjacent second selection element layer 143-2. A first material layer for forming a variable resistance layer may be thinly formed in the trench and on the insulating layer, and then a second material layer for forming the upper spacer may be formed. A planarization process such as a chemical mechanical polishing process may be performed on the first material layer and the second material layer until the top surface of the insulating layer is exposed. After the planarization process, the first material layer and the second material layer may be etched using a mask pattern to serve as an etch mask with the first memory unit 140-1 and the second memory. Unit 140-2 is aligned. Therefore, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "L" sectional shape, and the first upper spacer 155-1 and the second upper spacer 155-2 The sidewalls of the first variable resistance layer 149-1 and the sidewalls of the second variable resistance layer 149-2 are formed respectively.

Referring to FIG. 11, in the memory device 100E according to example embodiments, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "I" sectional shape. The first shape having the "I" cross-sectional shape can be formed by a process similar to the process of forming the first variable resistance layer 149-1 and the second variable resistance layer 149-2 having the "L" cross-sectional shape of FIG. Variable resistance layer 149-1 and second variable resistance layer 149-2. For example, after the first material layer for forming the variable resistance layer is thinly formed in the trench and on the insulating layer, an anisotropic etching process may be performed on the first material layer, such that an anisotropic etching process is performed. The first material layer remains only on the sidewalls of the trench. A second material layer comprising an insulating material may be formed to cover the first material layer. A planarization process (eg, a chemical mechanical polishing process) may be performed to expose the top surface of the insulating layer. After the planarization process, a mask pattern can be used to etch the second material layer to align with the first memory cell 140-1 and the second memory cell 140-2 as an etch mask. Therefore, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "I" sectional shape, and the first upper spacer 155-1 and the second upper spacer 155-2 The sidewalls of the first variable resistance layer 149-1 and the sidewalls of the second variable resistance layer 149-2 are formed respectively.

Referring to FIG. 12, in the memory device 100F according to an example embodiment, the first heating electrode layer 146-1 may be further formed between the first variable resistance layer 149-1 and the third electrode layer 147-1, and The second heating electrode layer 146-2 may be further formed between the second variable resistance layer 149-2 and the eighth electrode layer 148-2.

As illustrated in FIG. 12, the first variable resistance layer 149-1 and the first heating electrode layer 146-1 may be disposed in order from the second conductive line 120 toward the first conductive line 110, and may be in the first The second variable resistance layer 149-2 and the second heating electrode layer 146-2 are disposed in this order in the direction in which the two conductive lines 120 are directed toward the third conductive line 130. Therefore, the arrangement of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory unit 140-1 may be opposite to the second memory unit 140-2 with respect to the second conductive line 120. The arrangement of the second variable resistance layer 149-2 and the second heating electrode layer 146-2 is symmetrical. Therefore, the difference between the resistance value of the first variable resistance layer 149-1 and the resistance value of the second variable resistance layer 149-2 can be reduced. For example, when each of the first variable resistance layer 149-1 and the second variable resistance layer 149-2 includes GeSbTe, a diffusion rate and an anion of a positive ion (eg, Sb ⁺ ) The diffusivity of (e.g., Te ⁺ ) may be different from each other in the first variable resistance layer 149 - 1 and the second variable resistance layer 149 - 2 . When a negative voltage is applied to the first variable resistance layer 149-1 and a positive voltage is applied to the second variable resistance layer 149-2, the first variable resistance layer 149-1 and the second variable resistance layer 149 In -2, the difference between the diffusivity of the negative ions and the diffusivity of the positive ions induces a local concentration change. Therefore, the resistance value of the first variable resistance layer 149-1 and the resistance value of the second variable resistance layer 149-2 may be different from each other.

According to an example embodiment, the stacked structure of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory unit 140-1 and the second memory are opposite to the second conductive line 120 The stacked structure of the second heating electrode layer 146-2 and the second variable resistance layer 149-2 in the body unit 140-2 is symmetrical, so that the resistance value of the first variable resistance layer 149-1 can be reduced and the second The difference between the resistance values of the variable resistance layer 149-2 is such that each of the first memory unit 140-1 and the second memory unit 140-2 can have a uniform operational property. The resistance values of each of the first variable resistance layer 149-1 and the second variable resistance layer 149-2 are assumed to be in the same state (for example, a set state or a reset state).

Referring to FIG. 13, in the memory device 100G according to an example embodiment, the first heating electrode layer 146-1 may be further formed between the first variable resistance layer 149-1 and the fourth electrode layer 148-1, and The second heating electrode layer 146-2 may be further formed between the second variable resistance layer 149-2 and the seventh electrode layer 147-2.

As illustrated in FIG. 13 , the first variable resistance layer 149 - 1 and the first heating electrode layer 146-1 in the first memory unit 140 - 1 may be disposed opposite to the second conductive line 120 . The arrangement of the second variable resistance layer 149-2 and the second heating electrode layer 146-2 in the unit 140-2 is symmetrical. As described above, the difference between the resistance value of the first variable resistance layer 149-1 and the resistance value of the second variable resistance layer 149-2 can be reduced, so that the first memory unit 140-1 and the second memory Each of the body units 140-2 can have uniform operational attributes.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIGS. 10 to 13, the aspect of the inventive concept is not limited to this case. . For example, the first height H1 of the first selection element layer 143-1 may be formed to be smaller than the second height H2 of the second selection element layer 143-2.

In the example embodiment described with reference to FIGS. 1 to 13, the first memory unit 140-1 and the second memory unit 140-2 are vertically disposed on the first conductive line 110, the second conductive line 120, and the third. The structure between the conductive lines 130, but the aspect of the inventive concept is not limited to this case. In some embodiments, an insulating layer (not shown) may be formed on the third conductive line 130, and at least one stacked structure having an array of intersections as described with reference to FIGS. 1 through 13 may be disposed on the insulating layer.

FIG. 14 is a perspective view illustrating a memory device 200 according to an example embodiment, and FIG. 15 is a cross-sectional view taken along line 2A-2A' of FIG. 14 according to an example embodiment.

Referring to FIGS. 14 and 15, the memory device 200 can include a drive circuit region 210 disposed at a first level on the substrate 102, and a memory at a second level disposed on the drive circuit region 210. Memory cell array region MCA.

Here, the level means the height (or position) spaced apart from the substrate 102 in the vertical direction (that is, the Z direction of FIGS. 14 and 15). The first level is closer to the substrate 102 than the second level. The driving circuit region 210 may be a region in which peripheral circuits (or driving circuits) for driving the memory cells in the memory cell region MCA are disposed. For example, the peripheral circuits in the driver circuit region 210 may include circuitry for processing data input to the memory cells in the memory cell array region MCA or from the memory cells in the memory cell array region MCA. Peripheral circuits may include, for example, a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, Data in/out circuit or row decoder.

An active region AC for a peripheral circuit (or drive circuit) may be defined by a device isolation layer 104 in the substrate 102. A plurality of transistors TR constituting peripheral circuits in the driving circuit region 210 may be formed on the active region AC and in the active region AC. The plurality of transistors TR may each include a gate G, a gate insulating layer GD, and a source/drain region SD. Insulating spacers 106 may be formed on opposite sidewalls of the gate G, and an etch stop layer 108 may be formed on the gate G and the insulating spacers 106. The etch stop layer 108 may comprise an insulating material such as tantalum nitride or hafnium oxynitride.

A plurality of interlayer insulating layers 212A, 212B, and 212C may be sequentially stacked on the etch stop layer 108. Each of the plurality of interlayer insulating layers 212A, 212B, and 212C may include, for example, hafnium oxide, tantalum nitride, and/or hafnium oxynitride.

The driver circuit region 210 may include a multilevel interconnection structure 214 electrically connected to the plurality of transistors TR. The multi-level interconnect structure 214 may be covered by the plurality of interlayer insulating layers 212A, 212B, and 212C. The multi-level interconnect structure 214 can include a first contact 216A, a first interconnect layer 218A, a second contact 216b, and a second that are electrically connected to each other sequentially on the substrate 102. Interconnect layer 218B. The first interconnect layer 218A and the second interconnect layer 218B may comprise a metal, a conductive metal nitride, a metal telluride, or a combination thereof. The first interconnect layer 218A and the second interconnect layer 218B may comprise, for example, tungsten, molybdenum, titanium, cobalt, rhenium, nickel, tungsten telluride, titanium telluride, cobalt telluride, antimony telluride or nickel telluride.

Although the multi-level interconnect structure 214 includes a two-level interconnect structure having a first interconnect layer 218A and a second interconnect layer 218B, as illustrated in FIG. 15, the aspects of the inventive concept are not limited thereto. situation. For example, depending on the layout of the driver circuit region 210 and the configuration or type of gate G, the multi-level interconnect structure 214 may comprise a three-level or more than three-level interconnect structure.

The upper interlayer insulating layer 220 may be formed on the interlayer insulating layer 212C. The memory cell array region MCA may be disposed on the upper interlayer insulating layer 220. In the memory cell array region MCA, at least one or a combination of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, and 100G as described with reference to FIGS. 1 through 13 may be disposed.

An interconnect structure (not shown) penetrating the upper interlayer insulating layer 220 may be further disposed to electrically connect the memory cells in the memory cell array region MCA to peripheral circuits in the driving circuit region 210.

In the memory device 200 according to the example embodiment, since the memory cell array region MCA is disposed on the driving circuit region 210, the degree of accumulation of the memory device 200 can be increased.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIG. 15, the aspect of the inventive concept is not limited to this case. For example, the first height H1 of the first selection element layer 143-1 may be formed to be smaller than the second height H2 of the second selection element layer 143-2.

16A-16I are cross-sectional views illustrating stages of a method of fabricating a memory device 100, in accordance with an example embodiment.

A method of manufacturing the memory device 100 as illustrated in FIGS. 2 and 3 will be described with reference to FIGS. 16A through 16I. 16A through 16I illustrate cross-sectional structures corresponding to cross sections taken along lines AA' and BB' of Fig. 2 in accordance with the process stages. The same drawing element symbols are used to denote the same elements as those in FIGS. 1 to 15, and repeated description thereof is omitted for the sake of brevity.

Referring to FIG. 16A, an interlayer insulating layer 105 may be formed on the substrate 101. The interlayer insulating layer 105 may be formed of at least one of cerium oxide, cerium nitride, and cerium oxynitride.

The first conductive layer 110P may be formed on the interlayer insulating layer 105, and may form the first stacked structure CPS1, wherein the preliminary first electrode layer 141-1P, the preliminary first selection element layer 143-1P, and the preliminary second electrode layer 145- 1P, the preliminary third electrode layer 147-1P, the preliminary first variable resistance layer 149-1P, and the preliminary fourth electrode layer 148-1P are sequentially formed on the first conductive layer 110P. The first stack structure CPS1 can be used to form an array of cross points.

First conductive layer 110P, preliminary first electrode layer 141-1P, preliminary first selection element layer 143-1P, preliminary second electrode layer 145-1P, preliminary third electrode layer 147-1P, preliminary first variable resistance layer The 149-1P and the preliminary fourth electrode layer 148-1P may be the first conductive line 110, the first electrode layer 141-1, the first selection element layer 143-1, and the second electrode as described with reference to FIGS. 2 and 3. The material of the layer 145-1, the third electrode layer 147-1, the first variable resistance layer 149-1, and the fourth electrode layer 148-1 is formed of the same material.

The first mask pattern 410 may be formed on the preliminary fourth electrode layer 148-1P.

The first mask pattern 410 may include a plurality of line patterns extending in the first direction (X direction of FIG. 2) and spaced apart from each other in the second direction (Y direction of FIG. 2). The first mask pattern 410 may comprise a single layer or a multi-layer stack. The first mask pattern 410 may include, for example, a photoresist pattern, a silicon oxide pattern, a silicon nitride pattern, a silicon oxynitride pattern, and a polysilicon pattern. (poly-silicon pattern) or a combination thereof, but is not limited to this case. The first mask pattern 410 may be formed of various materials.

Referring to FIG. 16B, the first stacked pattern CPS1 and the first conductive layer 110P may be sequentially anisotropically etched using the first mask pattern 410 as an etch mask to separate the first stacked structure CPS1 into a plurality of first The line CPL1 is stacked and the first conductive layer 110P is separated into a plurality of first conductive lines 110.

As a result, the plurality of first conductive lines 110 and the plurality of first stack lines CPL1 may be formed to extend in the first direction. The plurality of first conductive lines 110 may be spaced apart from each other in the second direction, and the plurality of first stack lines CPL1 may be spaced apart from each other in the second direction. The plurality of first conductive lines 110 may form a first conductive line layer 110L. The plurality of first stacking lines CPL1 may each include a first electrode layer line 141-1L, a first selection element layer line 143-1L, a second electrode layer line 145-1L, and a third electrode layer line 147-1L, A variable resistance layer line 149-1L and a fourth electrode layer line 148-1L.

Furthermore, a plurality of first gaps GX1 may be formed between the plurality of conductive lines 110 and between the plurality of first stack lines CPL1 by an anisotropic etching process. The plurality of first gaps GX1 may extend in the first direction and may be spaced apart from each other in the second direction. A portion of the top surface of the substrate 101 may be exposed by the plurality of first gaps GX1.

Referring to FIG. 16C, the mask pattern 410 may be removed to expose the top surface of the fourth electrode line 148-1L, and then the first insulating layer 162-1 may be formed to fill the plurality of first gaps GX1.

In some embodiments, the forming of the first insulating layer 162-1 may include forming an insulating material on the substrate 101 to fill the plurality of first gaps GX1 and an upper portion of the planarizing insulating material until the plurality of the first portions are exposed One stacks the top surface of the line CPL1. The first insulating layer 162-1 may include, for example, a hafnium oxide layer, a tantalum nitride layer, and/or a hafnium oxynitride layer. The first insulating layer 162-1 may be made of one type of insulating layer or a plurality of insulating layers, but is not limited thereto.

Referring to FIG. 16D, a second conductive layer 120P may be formed on the exposed top surface of the fourth electrode line 148-1L and the exposed top surface of the first insulating layer 162-1.

The second stack structure CPS2 may be formed on the second conductive layer 120P. The second stacked structure CPS2 may include a preliminary fifth electrode layer 141-2P sequentially formed on the second conductive layer 120P, a preliminary second selection element layer 143-2P, a preliminary sixth electrode layer 145-2P, and a preliminary seventh The electrode layer 147-2P, the preliminary second variable resistance layer 149-2P, and the preliminary eighth electrode layer 148-2P.

Second conductive layer 120P, preliminary fifth electrode layer 141-2P, preliminary second selection element layer 143-2P, preliminary sixth electrode layer 145-2P, preliminary seventh electrode layer 147-2P, preliminary second variable resistance layer The 149-2P and the preliminary eighth electrode layer 148-2P may be the second conductive line 120, the fifth electrode layer 141-2, the second selection element layer 143-2, and the sixth electrode as described with reference to FIGS. 2 and 3. The material of the layer 145-2, the seventh electrode layer 147-2, the second variable resistance layer 149-2, and the eighth electrode layer 148-2 is formed of the same material.

The mask pattern 420 may be formed on the preliminary eighth electrode layer 148-2P. The mask pattern 420 may include a plurality of line patterns extending in the second direction and spaced apart from each other in the first direction.

Referring to FIG. 16E, the second mask pattern 420 may be used as an etch mask pattern to sequentially etch the second stack structure CPS2, the second conductive layer 120P, and the plurality of first stack lines CPL1 in an unequal manner to The second stack structure CPS2 is separated into a plurality of second stack lines CPL2, the second conductive layer 120P is separated into a plurality of second conductive lines 120, and the plurality of first stack lines CPL1 are separated into a plurality of first stacked patterns CPP1.

As a result, the plurality of second stacking lines CPL2 may extend in the second direction and may be spaced apart from each other in the first direction, and the plurality of second conductive lines 120 may extend in the second direction and may be in the They are separated from each other in one direction. Furthermore, the plurality of first stacked patterns CPP1 may be spaced apart from each other in the first direction and the second direction. The plurality of second conductive lines 120 may form a second conductive line layer 120L. The plurality of second stacking lines CPL2 may each include a fifth electrode layer line 141-2L, a second selection element layer line 143-2L, a sixth electrode layer line 145-2L, and a seventh electrode layer line 147-2L, Two variable resistance layer lines 149-2L and an eighth electrode layer line 148-2L. The plurality of first stacked patterns CPP1 may include a first electrode layer 141-1, a first selection element layer 143-1, a second electrode layer 145-1, a third electrode layer 147-1, and a first variable resistance layer. 149-1 and fourth electrode layer 148-1.

Furthermore, an anisotropic etching process may be formed between the plurality of second stacking lines CPL2, between the plurality of second lines 120, and between the plurality of first stacked patterns CPP1. A plurality of second gaps GY1. The plurality of second gaps GY1 may extend in the second direction and may be spaced apart from each other in the first direction.

In some embodiments, an anisotropic etch process can be performed until the top surface of the plurality of first conductive lines 110 is exposed. Although not shown, a groove having a certain depth may be formed in an upper portion of the plurality of first conductive lines 110 by an anisotropic etching process.

In some embodiments, an anisotropic etching process may be performed until the top surface of the first electrode layer line 141-1L is exposed, and then an etching process may be performed under a certain etching condition, under the etching condition, An electrode layer line 141-1L has an etching selectivity with respect to the plurality of first conductive lines 110 to remove the first electrode layer line 141-1L exposed by the plurality of second gaps GY1 A portion of each of the plurality of first conductive lines 110 is exposed to expose a top surface of the plurality of first conductive lines 110.

Referring to FIG. 16F, the second mask pattern 420 may be removed to expose top surfaces of the plurality of second stack lines CPL2. A second insulating layer 163 may be formed to fill the plurality of second gaps GY1.

In some embodiments, the forming of the second insulating layer 163 may be included on the plurality of first conductive lines 110, on sidewalls of the plurality of first stacked patterns CPP1, and on the plurality of second stacked lines An insulating material is formed on the sidewall of the CPL 2 to fill the plurality of second gaps GY1 and the upper portion of the planarization insulating material until the top surfaces of the plurality of second stacking lines CPL2 are exposed.

Referring to FIG. 16G, a third conductive layer 130P may be formed on the plurality of second stack lines CPL2 and the second insulating layer 163.

The third mask pattern 430 may be formed on the third conductive layer 130P. The third mask pattern 430 may include a plurality of line patterns extending in the first direction and spaced apart from each other in the second direction.

Referring to FIG. 16H, the third conductive layer 130P and the plurality of second stacked lines CPL2 may be sequentially anisotropically etched using the third mask pattern 430 as an etch mask to separate the third conductive line 130P into The plurality of third conductive lines 130 and the plurality of second stacked lines CPL2 are separated into a plurality of second stacked patterns CPP2.

As a result, the plurality of third conductive lines 130 may extend in the first direction and may be spaced apart from each other in the second direction, and the plurality of second stacked patterns CPP2 may be spaced apart from each other in the first direction and the second direction open. The plurality of third conductive lines 130 may form a third conductive line layer 130L. The plurality of second stacked patterns CPP2 may include a fifth electrode layer 141-2, a second selection element layer 143-2, a sixth electrode layer 145-2, a seventh electrode layer 147-2, and a second variable resistance layer. 149-2 and the eighth electrode layer 148-2.

Furthermore, a plurality of third gaps GX2 may be formed between the plurality of third conductive lines 130 and between the plurality of second stacked patterns CPP2 by an anisotropic etching process. The plurality of third gaps GX2 may extend in the first direction and may be spaced apart from each other in the second direction.

In some embodiments, an anisotropic etch process can be performed until the top surface of the plurality of second conductive lines 120 is exposed. Although not shown, a groove having a certain depth may be formed in an upper portion of the plurality of second conductive lines 120 by an anisotropic etching process.

In some embodiments, an anisotropic etching process may be performed until the top surface of the fifth electrode layer line 141-2L is exposed, and then an etching process may be performed under a certain etching condition, under the etching condition, The five-electrode layer line 141-2L has an etch selectivity with respect to the plurality of second conductive lines 120 to remove each of the fifth electrode layer lines 141-2L exposed by the plurality of third gaps GX2 A portion to expose a top surface of the plurality of second conductive lines 120.

Referring to FIG. 16I, the third mask pattern 430 may be removed to expose top surfaces of the plurality of second stacked patterns CPP2. A third insulating layer 162-2 may be formed to fill the plurality of third gaps GX2.

In some embodiments, the forming of the third insulating layer 162-2 may include forming an insulating material on the plurality of third conductive lines 130 and sidewalls of the plurality of second stacked patterns CPP2 to fill the plurality of The third gap GX2 and the upper portion of the planarization insulating material expose the top surface of the plurality of third conductive lines 130.

As a result, the memory device 100 can be implemented by performing the processes described above.

The plurality of first stacked patterns CPP1 may be a plurality of first memory cells 140-1, and the plurality of second stacked patterns CPP2 may be a plurality of second memory cells 140-2. In addition, the plurality of first memory cells 140-1 may form a first memory cell layer MCL1, and the plurality of second memory cells 140-2 may form a second memory cell layer MCL2.

According to the method of manufacturing the memory device 100, a first patterning process using the first mask pattern 410 extending in the first direction, and a second mask extending in the second direction may be sequentially performed A second patterning process of the cap pattern 420 and a third patterning process using the third mask pattern 430 extending in the first direction. As a result, the plurality of first conductive lines 110 extending in the first direction, the plurality of second conductive lines 120 extending in the second direction, and the plurality of first lines extending in the first direction may be formed a plurality of conductive lines 130, the plurality of first memory cells 140-1 at respective intersections of the plurality of first conductive lines 110 and the plurality of second conductive lines 120, and the plurality of The plurality of second memory cells 140-2 at the intersection of the second conductive line 120 and the plurality of third conductive lines 130.

Therefore, since the plurality of first memory cells 140-1 and the plurality of second memory cells 140-2 are formed using only three patterning processes, the first variable resistance layer 149-1 can be prevented. And the second variable resistance layer 149-2 and/or the first selection element layer 143-1 and the second selection element layer 143-2 are attributed to reduced quality or damage to the etching atmosphere during the patterning process. In addition, the manufacturing cost of the memory device 100 can be reduced.

17 is a block diagram illustrating a memory device in accordance with some embodiments.

Referring to FIG. 17, the memory device 800 can include a memory cell array 810, a decoder, a read/write circuit 830, an input/output buffer, and a controller 850. The memory cell array 810 can include at least one of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 200 described with reference to FIGS. 1 through 15.

A plurality of memory cells in the memory cell array 810 may be connected to the decoder 820 via a plurality of word lines WL and may be connected to the read/write circuit 830 via a plurality of bit lines BL. The decoder 820 can receive the address ADD from the outside of the memory device 800, and can decode the column address and the row address in the memory cell array 810 by the control of the controller 850 operating in response to the control signal CTRL. access.

The read/write circuit 830 can receive data from the input/output buffer and the plurality of data lines DL, and can write the received data to the selected memory of the memory cell array 810 by the control of the controller 850. In the unit. The read/write circuit 830 can read data from the selected memory cells of the memory cell array 810 by the control of the controller 850, and can transfer the read data to the input/output buffer.

18 is a block diagram illustrating an electronic system in accordance with some embodiments.

Referring to FIG. 18, the electronic system 1100 can include a memory system 1110, a processor 1120, a random access memory (RAM) 1130, and an input/output (I/O). A unit 1140, a power supply unit 1150. The memory system 1110 can include a memory device 1112 and a memory controller 1114. Although not shown, the electronic system 1100 can further include a device that communicates with a video card, a sound card, a memory card, a USB device, or other electronic device. The electronic system 1100 can be a personal computer or a mobile electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), or a video camera.

The processor 1120 can perform a particular calculation or task. The processor 1120 can be a microprocessor or a central processing unit (CPU). The processor 1120 can communicate with the random access memory 1130, the input/output unit 1140, and the memory system 1110 via a bus 1160, such as an address bus, a control bus, or a data bus. Here, the memory system 1110 or the random access memory 1130 may include at least one of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 200 described with reference to FIGS. 1 through 15. .

In some embodiments, processor 1120 can be coupled to an expansion bus, such as a peripheral component interconnection (PCI) bus.

The random access memory 1130 can store the data necessary to operate the electronic system 1100. The random access memory 1130 may comprise DRAM, mobile DRAM, SRAM, ReRAM, FRAM, MRAM or PRAM.

The input/output unit 1140 may include an input unit such as a keypad, a keyboard, or a mouse, and an output unit such as a display or a printer. The power supply unit 1150 can supply an operating voltage necessary for operating the electronic system 1100.

The above-disclosed subject matter is intended to be illustrative and not restrictive, and the scope of the appended claims are intended to be Therefore, to the extent permitted by law, the scope should be judged by the broadest permitted interpretation of the scope of the following claims and their equivalents, and should not be limited or limited by the foregoing detailed description.

2A-2A', A-A', B-B'‧‧‧ line
40‧‧‧Voltage-current curve
41‧‧‧First curve
42‧‧‧second curve
43‧‧‧First voltage level
44‧‧‧second voltage level
46‧‧‧First current level
47‧‧‧second current level
56(V ₁ )‧‧‧First threshold voltage
58(V ₂ )‧‧‧second threshold voltage
60‧‧‧Voltage-current graph
62‧‧‧First experimental example
64‧‧‧Second experimental example
100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 200, 800, 1112‧‧‧ memory devices
101, 102‧‧‧ substrate
104‧‧‧Device isolation
105, 212A, 212B, 212C‧‧‧ interlayer insulation
106‧‧‧Insulation spacers
108‧‧‧etch stop layer
110‧‧‧First conductive line
110L‧‧‧First conductive layer
110P‧‧‧first conductive layer
120‧‧‧Second conductive line
120L‧‧‧Second conductive layer
120P‧‧‧Second conductive layer
130‧‧‧ third conductive line
130L‧‧‧3rd conductive layer
130P‧‧‧3rd conductive layer
140-1, MC1‧‧‧ first memory unit
140-2, MC2‧‧‧ second memory unit
141-1‧‧‧First electrode layer
141-1L‧‧‧First electrode layer line
141-1P‧‧‧ Preliminary first electrode layer
141-2‧‧‧ fifth electrode layer
141-2L‧‧‧ fifth electrode layer line
141-2P‧‧‧ preliminary fifth electrode layer
143-1‧‧‧First selection component layer
143-1L‧‧‧First selection component layer line
143-1P‧‧‧ Preliminary first selection component layer
143-2‧‧‧Second selection component layer
143-2L‧‧‧Second selection component layer line
143-2P‧‧‧ preliminary second selection component layer
145-1‧‧‧Second electrode layer
145-1L‧‧‧Second electrode layer line
145-1P‧‧‧ Preliminary second electrode layer
145-2‧‧‧ sixth electrode layer
145-2L‧‧‧ sixth electrode layer line
145-2P‧‧‧ preliminary sixth electrode layer
147-1‧‧‧ third electrode layer
147-1L‧‧‧ third electrode layer line
147-1P‧‧‧ Preliminary third electrode layer
147-2‧‧‧ seventh electrode layer
147-2L‧‧‧ seventh electrode layer line
147-2P‧‧‧ preliminary seventh electrode layer
148-1‧‧‧fourth electrode layer
148-1L‧‧‧fourth electrode layer line
148-1P‧‧‧ preliminary fourth electrode layer
148-2‧‧‧8th electrode layer
148-2L‧‧‧8th electrode layer line
148-2P‧‧‧ preliminary eighth electrode layer
149-1‧‧‧First variable resistance layer
149-1L‧‧‧First variable resistance layer line
149-1P‧‧‧ Preliminary first variable resistance layer
149-2‧‧‧Second variable resistance layer
149-2L‧‧‧Second variable resistance layer line
149-2P‧‧‧ Preliminary second variable resistance layer
152-1‧‧‧First internal spacer
152-2‧‧‧Second internal spacer
155-1‧‧‧First upper spacer
155-2‧‧‧Second upper spacer
162-1‧‧‧First insulation layer
162-2‧‧‧Second insulation
163‧‧‧ Third insulation layer
210‧‧‧Drive circuit area
214‧‧‧Multi-level interconnect structure
216A‧‧‧First contact
216B‧‧‧second contact
218A‧‧‧First interconnect layer
218B‧‧‧Second inner layer
220‧‧‧ Upper interlayer insulation
410‧‧‧First mask pattern
420‧‧‧Second mask pattern
430‧‧‧ third mask pattern
810‧‧‧Memory cell array
820‧‧‧Decoder
830‧‧‧Read/Write Circuit
840‧‧‧Input/Output Buffer
850‧‧‧ Controller
1100‧‧‧Electronic system
1110‧‧‧Memory System
1114‧‧‧Memory Controller
1120‧‧‧ processor
1130‧‧‧ random access memory
1140‧‧‧Input/output unit
1150‧‧‧Power supply unit
1160‧‧ ‧ busbar
AC‧‧ Active Area
BL‧‧‧ bit line
BL1, BL2, BL3, BL4‧‧‧ common bit line
CPL1‧‧‧ first stacking line
CPL2‧‧‧Second stacking line
CPP1‧‧‧ first stacking pattern
CPP2‧‧‧ second stacking pattern
CPS1‧‧‧ first stack structure
CPS2‧‧‧Second stacking structure
DL‧‧‧ data line
G‧‧‧ gate
GD‧‧‧ gate insulation
GX1‧‧‧ first gap
GY1‧‧‧Second gap
GX2‧‧‧ third gap
H1, H1A‧‧‧ first height
H2, H2A‧‧‧ second height
I _MC11 ‧‧‧First current
I _MC21 ‧‧‧second current
MC11‧‧‧First lower memory unit
MC12‧‧‧Second lower memory unit
MC21‧‧‧First upper memory unit
MC22‧‧‧Second upper memory unit
MCA‧‧‧ memory cell array area
MCL1‧‧‧ first memory unit layer
MCL2‧‧‧Second memory unit layer
ME, R‧‧‧variable resistance layer
SD‧‧‧Source/Bungee Zone
SW‧‧‧Select components
TR‧‧‧O crystal
Vlow‧‧‧lower voltage
V _S ‧‧‧Saturation voltage
V _T ‧‧‧ threshold voltage
V _T1 ‧‧‧first threshold voltage
V _T2 ‧‧‧second threshold voltage
V _WL(Sel) ‧‧‧ character line selection voltage
V _{WL (Unsel)} ‧‧‧ character line not selected voltage
WL‧‧‧ character line
WL11, WL12‧‧‧ lower word line
WL21, WL22‧‧‧ upper word line
X, Y, Z‧‧ Direction

Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is an equivalent circuit diagram illustrating a memory device in accordance with an example embodiment. 2 is a perspective cross-sectional view illustrating a memory device according to an example embodiment, and FIG. 3 is a cross-sectional view taken along lines AA' and BB' of FIG. 2, according to an example embodiment. Sectional view. 4 is a schematic diagram illustrating a voltage-current curve of a bidirectional critical switching element representing an ovonic threshold switching (OTS) attribute. 5A and 5B are schematic diagrams illustrating an operation method of a memory device having a stacked cross-point structure, according to an example embodiment. Figure 6 illustrates a voltage-current graph for applying a positive voltage and a negative voltage to a bidirectional critical switching element, respectively. 7 through 13 are cross-sectional views illustrating a memory device, respectively, according to an example embodiment. FIG. 14 is a perspective view illustrating a memory device according to an example embodiment, and FIG. 15 is a cross-sectional view taken along line 2A-2A′ of FIG. 14 according to an example embodiment. 16A-16I are cross-sectional views illustrating stages of a method of fabricating a memory device, in accordance with an example embodiment. 17 is a block diagram illustrating a memory device in accordance with some embodiments. 18 is a block diagram illustrating an electronic system in accordance with some embodiments.

100‧‧‧ memory device

BL1, BL2, BL3, BL4‧‧‧ common bit line

MC1‧‧‧ first memory unit

MC2‧‧‧Second memory unit

ME‧‧‧variable resistance layer

SW‧‧‧Select components

WL11, WL12‧‧‧ lower word line

WL21, WL22‧‧‧ upper word line

X, Y, Z‧‧ Direction

Claims (20)

A memory device comprising: a substrate; a plurality of first conductive lines on the substrate, the plurality of first conductive lines extending in a first direction parallel to a top surface of the substrate and Separating from each other in a second direction in which the first directions intersect; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and Separating from each other in the first direction; a plurality of third conductive lines above the plurality of second conductive lines, the plurality of third conductive lines extending in the first direction and in the second direction Separating from each other; a plurality of first memory cells, each of the plurality of first memory cells at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines One includes a first selection element layer and a first variable resistance layer; and a plurality of second memory units at respective intersections of the plurality of second conductive lines and the plurality of third conductive lines, Each of the plurality of second memory units includes a second selection element layer and a second variable a resist layer, wherein a first height of the first selection element layer in a third direction perpendicular to the first direction and the second direction is different from a second selection element layer in the third direction a height, and wherein the first variable resistance layer and the second variable resistance layer are made of the same material, and the first selection element layer and the second selection element layer are made of the same material to make. The memory device of claim 1, wherein a difference in magnitude between a threshold voltage of the first selection element layer and a threshold voltage of the second selection element layer is smaller than the first selection element layer 10% of the threshold voltage. The memory device of claim 1, wherein the magnitude of the threshold voltage of the first selection element layer ranges from 90% to 110% of the magnitude of the threshold voltage of the second selection element layer. . The memory device of claim 1, wherein the first height of the first selection element layer is greater than the second height of the second selection element layer. The memory device of claim 4, wherein the memory device is configured to apply a word line selection voltage to one of the plurality of first conductive lines or to the plurality of One of the third conductive lines, and applying a inhibit voltage that is less than the word line select voltage to one of the plurality of second conductive lines. The memory device of claim 4, wherein the second height of the second selection element layer ranges from 50% to 90% of the first height of the first selection element layer . The memory device of claim 1, wherein the first height of the first selection element layer is less than the second height of the second selection element layer. The memory device of claim 7, wherein the first height of the first selection element layer ranges from 50% to 90% of the second height of the second selection element layer . The memory device of claim 7, wherein the memory device is configured to apply a word line selection voltage to one of the plurality of first conductive lines or to the plurality of One of the third conductive lines, and applying a inhibit voltage greater than the word line select voltage to one of the plurality of second conductive lines. The memory device of claim 1, wherein each of the first selection element layer and the second selection element layer has a bidirectional critical switching property. The memory device of claim 1, wherein each of the plurality of first memory cells is further included in the first variable resistance layer and the plurality of first conductive lines a first heating electrode layer between the counterparts, and each of the plurality of second memory cells further includes a correspondence between the second variable resistance layer and the plurality of third conductive lines A second heating electrode layer between the two. The memory device of claim 1, wherein each of the plurality of first memory cells is further included in the first variable resistance layer and the plurality of second conductive lines a first heating electrode layer between the counterparts, and each of the plurality of second memory cells further comprising a corresponding one of the second variable resistance layer and the plurality of second conductive lines A second heating electrode layer between the two. A memory device comprising: a substrate; a plurality of first conductive lines on the substrate, the plurality of first conductive lines extending in a first direction parallel to a top surface of the substrate and Separating from each other in a second direction in which the first directions intersect; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and Separating from each other in the first direction; a plurality of third conductive lines above the plurality of second conductive lines, the plurality of third conductive lines extending in the first direction and in the second direction Separating from each other; a plurality of first memory cells, each of the plurality of first memory cells at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines One includes a first selection element layer and a first variable resistance layer sequentially stacked in a third direction perpendicular to the first direction and the second direction; and a plurality of second memory units Where the plurality of second conductive lines and the plurality of third conductive lines intersect each other, Each of the plurality of second memory cells includes a second selection element layer and a second variable resistance layer sequentially stacked in the third direction, wherein the first selection element layer is at the third party The upward thickness is greater than the thickness of the second selection element layer in the third direction, and wherein the first variable resistance layer and the second variable resistance layer are made of the same material, and the A selection element layer and the second selection element layer are made of the same material. The memory device of claim 13, wherein each of the first selection element layer and the second selection element layer and the variable resistance layer has at least one of chalcogen elements By. The memory device of claim 13, wherein a thickness of the second selection element layer in the third direction is a thickness of the first second selection element layer in the third direction 50% to 90%. A memory device includes: a substrate; a first word line layer disposed on the substrate; a common bit line layer disposed on the first word line layer; and a second word line layer disposed on The common bit line is such that the common bit line layer is vertically located between the first word line layer and the second word line layer; the first memory unit layer comprises vertically stacked a first variable resistance layer and a first bidirectional critical switching layer, the first memory cell layer being disposed between the first word line layer and the common bit line layer in a vertical direction; and a second a memory cell layer comprising a second variable resistance layer and a second bidirectional critical switching layer vertically stacked, wherein the second memory cell layer is disposed in the vertical direction on the second word line layer and the common Between the bit line layers, wherein the first variable resistance layer and the second variable resistance layer are made of the same material, and the first bidirectional critical switching layer and the second bidirectional critical switching layer Is made of the same material, and wherein the first bidirectional critical switching A first thickness in a vertical direction is different from a second thickness of the second layer of a bidirectional switching threshold in a vertical direction. The memory device of claim 16, wherein the first thickness of the first bidirectional critical switching layer ranges from 50% of the second thickness of the second bidirectional critical switching layer to 90%, or wherein the second thickness of the second bidirectional critical switching layer ranges from 50% to 90% of the first thickness of the first bidirectional critical switching layer. The memory device of claim 16, wherein each of the first variable resistance layer and the second variable resistance layer and the bidirectional critical switching layer comprises a chalcogen element At least one. The memory device of claim 16, further comprising a sidewall covering the first bidirectional critical switching layer and the second bidirectional critical switching layer and/or the first variable resistance layer and the a spacer for the sidewall of the second variable resistance layer. The memory device of claim 19, wherein each of the first variable resistance layer and the second variable resistance layer has an L shape or an I shape.