TWI703578B - Memory device including ovonic threshold switch adjusing threshold voltage thereof - Google Patents

Abstract

A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

Description

Memory device including bidirectional threshold switch for adjusting threshold voltage [Cross reference of related applications]

This application claims the Korean Patent Application No. 10-2016-0020680 filed in the Korean Intellectual Property Office on February 22, 2016 and the Korean Patent Application No. 10-2016 filed in the Korean Intellectual Property Office on April 25, 2016 -0050113 priority, the entire disclosure of these Korean patent applications is incorporated herein by reference.

The embodiment of the disclosure relates to a memory device. More specifically, the embodiment of the present disclosure relates to a memory device having a cross-point structure.

As the size of electronic devices has been reduced, the integration of semiconductor memory devices has increased. Therefore, it has been studied to include a three-dimensional intersection of a plurality of memory cells arranged at the intersection point of two electrodes that cross each other. The cross point memory device is scaled down. However, in the scaling down process, because the thickness of the layer used to form the three-dimensional cross-point array memory device is also reduced, the layer exposed to the high temperature process can be easily damaged and degraded in quality. Therefore, the electrical characteristics of the three-dimensional cross-point memory device may degrade the quality.

According to example embodiments, a memory device may include: a substrate; a plurality of first conductive lines, on the substrate, the plurality of first conductive lines are arranged at first parallel to the top surface of the substrate. Extending in the direction and spaced apart from each other in a second direction crossing the first direction; a plurality of second conductive lines, above the plurality of first conductive lines, the plurality of second conductive lines in the second direction Extending and spaced apart from each other in the first direction; a plurality of third conductive lines above the plurality of second conductive lines, the plurality of third conductive lines extending in the first direction and mutually in the second direction Spaced apart; a plurality of first memory cells, at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines, each of the plurality of first memory cells Comprising a first selection element layer and a first variable resistance layer; and a plurality of second memory cells, between the plurality of second conductive lines and the plurality of third conductive lines At respective intersections of the lines, each of the plurality of second memory cells includes a second selection element layer and a second variable resistance layer. The first height of the first selection element layer in the third direction perpendicular to the first direction and the second direction may be different from the second height of the second selection element layer in the third direction. The first variable resistance layer and the second variable resistance layer can be made of the same material, and the first selection element layer and the second selection element layer can be made of the same material.

According to example embodiments, a memory device may include: a substrate; a plurality of first conductive lines, on the substrate, the plurality of first conductive lines extend in a first direction parallel to the top surface of the substrate and are aligned with the first One direction is separated from each other in a second direction crossing; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and in the first direction Spaced apart from each other; a plurality of third conductive lines, above the plurality of second conductive lines, the plurality of third conductive lines extend in the first direction and are spaced apart from each other in the second direction; a plurality of first A memory cell, where each of the plurality of first memory cells is included in a direction perpendicular to the first direction at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines And the first selection element layer and the first variable resistance layer sequentially stacked in the third direction in the second direction; and a plurality of second memory cells, between the plurality of second conductive lines and the plurality of first At respective intersections of the three conductive lines, each of the plurality of second memory cells includes a second selection element layer and a second variable resistance layer sequentially stacked in the third direction. The thickness of the first selection element layer in the third direction may be greater than the thickness of the second selection element layer in the third direction. The first variable resistance layer and the second variable resistance layer can be made of the same material, and the first selection element layer and the second selection element layer can be made of the same material.

According to example embodiments, a memory device may include: a substrate; a first word line layer (word line layer) disposed on the substrate; a common bit line layer (common bit line layer) disposed on the first word line The second word line layer is arranged on the common bit line layer, so that the common bit line layer is vertically located between the first word line layer and the second word line layer; the first memory cell layer (memory cell layer), including a first variable resistance layer and a first ovonic threshold switching layer stacked vertically, the first memory cell layer is arranged in the vertical direction Between the first word line layer and the common bit line layer; and the second memory cell layer, including a second variable resistance layer and a second bidirectional critical switching layer stacked vertically, the second memory cell layer It is vertically arranged between the second word line layer and the common bit line layer. The first variable resistance layer and the second variable resistance layer can be made of the same material, and the first bidirectional critical switching layer and the second bidirectional critical switching layer can be made of the same material. The first thickness of the first bidirectional critical switching layer in the vertical direction may be different from the second thickness of the second bidirectional critical switching layer in the vertical direction.

2A-2A', A-A', B-B': line

40: voltage-current curve

41: The first curve

42: second curve

43: first voltage level

44: second voltage level

46: First current level

47: second current level

56 (V ₁ ): the first critical voltage

58 (V ₂ ): the second critical voltage

60: voltage-current graph

62: The first experimental example

64: second experimental example

100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 200, 800, 1112: memory device

101, 102: substrate

104: Device isolation layer

105, 212A, 212B, 212C: interlayer insulation layer

106: insulating spacer

108: Etch stop layer

110: The first conductive thread

110L: the first conductive wire layer

110P: the first conductive layer

120: second conductive wire

120L: second conductive wire layer

120P: second conductive layer

130: third conductive thread

130L: third conductive wire layer

130P: third conductive layer

140-1, MC1: the first memory unit

140-2, MC2: second memory unit

141-1: First electrode layer

141-1L: first electrode layer line

141-1P: preliminary first electrode layer

141-2: Fifth electrode layer

141-2L: Fifth electrode layer line

141-2P: preliminary fifth electrode layer

143-1: first choice component layer

143-1L: first choice component layer line

143-1P: Initial first choice component layer

143-2: The second choice component layer

143-2L: Second choice component layer line

143-2P: Preliminary second choice component layer

145-1: second electrode layer

145-1L: second electrode layer line

145-1P: preliminary second electrode layer

145-2: The sixth electrode layer

145-2L: sixth electrode layer line

145-2P: preliminary sixth electrode layer

147-1: third electrode layer

147-1L: third electrode layer line

147-1P: preliminary third electrode layer

147-2: seventh electrode layer

147-2L: seventh electrode layer line

147-2P: Preliminary seventh electrode layer

148-1: Fourth electrode layer

148-1L: Fourth electrode layer line

148-1P: preliminary fourth electrode layer

148-2: Eighth electrode layer

148-2L: Eighth electrode layer line

148-2P: preliminary eighth electrode layer

149-1: The first variable resistance layer

149-1L: The first variable resistance layer line

149-1P: preliminary first variable resistance layer

149-2: Second variable resistance layer

149-2L: Second variable resistance layer line

149-2P: Preliminary second variable resistance layer

152-1: The first internal spacer

152-2: The second inner spacer

155-1: First upper spacer

155-2: The second upper spacer

162-1: The first insulating layer

162-2: second insulating layer

163: third insulating layer

210: Drive circuit area

214: Multi-level interconnect structure

216A: first contact

216B: second contact

218A: The first interconnection layer

218B: The second interconnection layer

220: upper interlayer insulation layer

410: The first mask pattern

420: The second mask pattern

430: The third mask pattern

810: Memory cell array

820: decoder

830: read/write circuit

840: input/output buffer

850: Controller

1100: Electronic System

1110: memory system

1114: Memory Controller

1120: processor

1130: random access memory

1140: input/output unit

1150: power supply unit

1160: bus

AC: Active area

BL: bit line

BL1, BL2, BL3, BL4: common bit line

CPL1: first stacking line

CPL2: second stacking line

CPP1: first stack pattern

CPP2: second stack pattern

CPS1: The first stack structure

CPS2: second stack structure

DL: Data line

G: Gate

GD: gate insulation layer

GX1: first gap

GY1: second gap

GX2: third gap

H1, H1A: first height

H2, H2A: second height

I _MC11 : first current

I _MC21 : second current

MC11: The first lower memory unit

MC12: The second lower memory unit

MC21: The first upper memory unit

MC22: The second upper memory unit

MCA: Memory cell array area

MCL1: The first memory cell layer

MCL2: The second memory cell layer

ME, R: Variable resistance layer

SD: source/drain region

SW: Select component

TR: Transistor

Vlow: lower voltage

V _S : saturation voltage

V _T : critical voltage

V _T1 : the first threshold voltage

V _T2 : second threshold voltage

V _WL(Sel) : character line selection voltage

V _WL(Unsel) : No voltage selected for word line

WL: Character line

WL11, WL12: lower character line

WL21, WL22: upper character line

X, Y, Z: direction

The following detailed description taken in conjunction with the accompanying drawings will give a clearer understanding of example embodiments of the present disclosure. In the drawings: FIG. 1 is an equivalent circuit diagram illustrating a memory device according to an example embodiment.

FIG. 2 is a perspective cross-sectional view illustrating a memory device according to an example embodiment, and FIG. 3 is a cross-sectional view illustrating a cross section taken along the lines A-A' and B-B' of FIG. 2 according to an example embodiment Sectional view.

FIG. 4 is a schematic diagram illustrating a voltage-current curve of a bidirectional threshold switching element representing the properties of ovonic threshold switching (OTS).

5A and 5B are schematic diagrams illustrating an operation method of a memory device having a stacked cross-point structure according to example embodiments.

FIG. 6 illustrates voltage-current graphs regarding the application of positive voltage and negative voltage to the bidirectional critical switching element, respectively.

7 to 13 are respectively cross-sectional views illustrating a memory device according to example embodiments.

FIG. 14 is a perspective view illustrating a memory device according to an example embodiment, and FIG. 15 is a cross-sectional view taken along line 2A-2A' of FIG. 14 according to an example embodiment.

16A to 16I are cross-sectional views illustrating stages of a method of manufacturing a memory device according to example embodiments.

Figure 17 is a block diagram illustrating a memory device according to certain embodiments.

Figure 18 is a block diagram illustrating an electronic system according to some embodiments.

The present disclosure will now be described more fully below with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. However, the concept of the present invention can be embodied in different forms and should not be regarded as limited to the embodiments set forth herein.

FIG. 1 is an equivalent circuit diagram illustrating a memory device according to an example embodiment.

As used herein, a semiconductor device may refer to any of various devices such as those shown in FIGS. 1 to 3 and FIGS. 7 to 15, and may also refer to, for example, a semiconductor chip (semiconductor chip) ( For example, a memory chip and/or logic chip (logic chip) formed on a die, a stack of semiconductor chips, a semiconductor including one or more semiconductor chips stacked on a package substrate Package (semiconductor package) or a package-on-package device containing multiple packages. These devices can be formed using ball grid arrays, wire bonding, through substrate vias, or other electrical connection elements, and can include, for example, volatile Memory device or non-volatile memory device.

As used herein, electronic devices may refer to these semiconductor devices, but may additionally include products with these devices, such as memory modules, memory cards, and hard drives containing additional components (hard drive), or mobile phone, laptop, tablet, desktop, camera or other consumer electronic device (consumer electronic device) and many more.

1, the memory device 100 may include lower word lines WL11 and WL12, upper word lines WL21 and WL22, common bit lines BL1, BL2, BL3 and BL4, and a first The memory cell MC1 and the second memory cell MC2. The lower word lines WL11 and WL12 may extend in the X direction (for example, referred to as the first direction) and may be spaced apart from each other in the Y direction (for example, referred to as the second direction) crossing the first direction. The upper character lines WL21 and WL22 can be separated from the lower character lines WL11 and WL12 in the Z direction (for example, referred to as the third direction or the vertical direction) perpendicular to the first direction and the second direction. Extend in the direction and may be spaced apart from each other in the second direction. The common bit lines BL1, BL2, BL3, and BL4 can be arranged between the lower word lines WL11 and WL12 and the upper word lines WL21 and WL22 to move from the lower word lines WL11 and WL12 and the upper word lines in the third direction WL21 and WL22 are separated. The common bit lines BL1, BL2, BL3, and BL4 may extend in the second direction and may be spaced apart from each other in the first direction.

The first memory cell MC1 and the second memory cell MC2 can be arranged between the common bit lines BL1, BL2, BL3, and BL4 and the lower word lines WL11 and WL12, and the common bit lines BL1, BL2, BL3, and BL4, respectively Between the upper character lines WL21 and WL22. More specifically, the first memory cell MC1 can be placed on the common bit lines BL1, BL2, BL3, and BL4 and the lower word lines WL11 and WL12 The respective intersection points (or intersection points) of, and each may include a variable resistance layer ME for storing information and a selection element SW for selecting a memory cell. The first memory cell MC1 can be arranged in two dimensions in the first direction and the second direction to form the first memory cell layer. The second memory cell MC2 can be placed at the respective intersections (or intersections) of the common bit lines BL1, BL2, BL3, and BL4 and the upper word lines WL21 and WL22, and can each include a memory cell for storing information. The variable resistance layer ME and the selection element SW for selecting the memory cell. The second memory cell MC2 can be arranged in two dimensions in the first direction and the second direction to form a second memory cell layer. The selection element SW can be called a switching element or an access element.

The first memory cell MC1 and the second memory cell MC2 can be arranged to have the same structure in the third direction. As shown in FIG. 1, under the condition that the first memory cell MC1 is located between the lower word line WL11 and the common bit line BL1, the variable resistance layer ME can be electrically connected to the common bit line BL1, and the selection element SW can be It is electrically connected to the lower word line WL11, and the variable resistance layer ME may be connected in series with the selection element SW. In addition, under the condition that the second memory cell MC2 is located between the upper word line WL21 and the common bit line BL1, the variable resistance layer ME can be electrically connected to the upper word line WL21, and the selection element SW can be electrically connected to the common bit line. The bit line BL1 and the variable resistance layer ME may be connected in series with the selection element SW. However, the aspect of the concept of the present invention is not limited to this case. In some embodiments, in each of the first memory cell MC1 and the second memory cell MC2, the configuration of the variable resistance layer ME and the selection element SW may be reversed differently from that shown in FIG. 1. For example, the first memory cell MC1 and the second memory cell MC2 may be symmetrically arranged in the third direction with respect to the common bit lines BL1, BL2, BL3, and BL4. For example, in the first note In the memory cell MC1, the variable resistance layer ME can be connected to the lower word lines WL11 and WL12, and the selection element SW can be connected to the common bit lines BL1, BL2, BL3, and BL4, and in the second memory cell MC2 , The variable resistance layer ME can be connected to the upper word lines WL21 and WL22, and the selection element SW can be connected to the common bit lines BL1, BL2, BL3, and BL4, so that each of the first memory cells MC1 is Each of the two memory cells MC2 can be symmetrically arranged with respect to the corresponding ones of the common bit lines BL1, BL2, BL3, and BL4.

Hereinafter, the operation method of the memory device 100 will be described.

For example, a voltage can be applied to any one of the first memory cell MC1 through the lower word lines WL11 and WL12, the upper word lines WL21 and WL22, and the common bit lines BL1, BL2, BL3, and BL4. The variable resistance layer ME or the variable resistance layer ME of any one of the second memory cell MC2 is changed to allow current to flow in the variable resistance layer ME. For example, the variable resistance layer ME may include a phase change material that can be reversibly changed between a first state and a second state different from the first state, but is not limited to this case. In some embodiments, the variable resistance layer ME may include any kind of variable resistance material whose resistance value changes depending on the applied voltage. For example, according to the voltage applied to the variable resistance layer ME of the selected one of the first memory cell MC1 and the second memory cell MC2, the resistance value of the variable resistance layer ME can be in the first state and the second state Change reversibly between.

According to the resistance change of the variable resistance layer ME, digital data such as "0" or "1" can be stored in the first memory cell MC1 and the second memory cell MC2 and can be transferred from the first memory cell MC1 and the second memory cell MC1 and the second memory cell MC1. The memory cell MC2 is erased. For example, in the first memory cell MC1 and the second memory cell MC2, the The high resistance state is written as data "0" and the low resistance state can be written as data "1". Here, the resistance change operation from the high resistance state ("0" data state) to the low resistance state ("1" data state) can be referred to as a "set" operation, and from the low resistance state ("1") The resistance change operation from the data state) to the high resistance state ("0" data state) can be referred to as a "reset" operation. However, the example embodiments are not limited to digital data in the high resistance state ("0" data state) and low resistance state ("1" data state). For example, the memory cells MC1 and MC2 can store various resistance states.

By selecting one of the word lines WL11, WL12, WL21, and WL22 and one of the common bit lines BL1, BL2, BL3, and BL4, the first memory cell MC1 and the second memory cell MC2 can be addressed Of any memory unit. By applying a signal between the corresponding ones of the word lines WL11, WL12, WL21, and WL22 and the corresponding ones of the common bit lines BL1, BL2, BL3, and BL4, the first memory cell MC1 and The corresponding one of the second memory cell MC2, and by measuring the current value through the corresponding one of the common bit lines BL1, BL2, BL3, and BL4, the readability depends on the first memory cell MC1 and the second Information on the resistance value of the corresponding variable resistance layer ME in the memory cell MC2.

In an example embodiment, the threshold voltage of the selection element SW of the first memory cell MC1 may be substantially the same as the threshold voltage of the selection element SW of the second memory cell MC2. For example, the magnitude difference between the threshold voltage of the selection element SW of the first memory cell MC1 and the threshold voltage of the selection element SW of the second memory cell MC2 may be smaller than that of the selection element SW of the first memory cell MC1 10% of the critical voltage. For example, the magnitude difference between the threshold voltage of the selection element SW of the first memory cell MC1 and the threshold voltage of the selection element SW of the second memory cell MC2 may be less than 0.5V. Because the selection element SW of the first memory cell MC1 The magnitude difference between the threshold voltage and the threshold voltage of the selection element SW of the second memory cell MC2 may be much smaller, so the sensing margin of the read/write operation can be improved or increased, thereby Reduce or prevent read/write failures. As a result, the memory device 100 can have improved reliability.

FIG. 2 is a perspective cross-sectional view illustrating a memory device according to an example embodiment, and FIG. 3 is a cross-sectional view illustrating a cross section taken along the lines A-A' and B-B' of FIG. 2 according to an example embodiment Sectional view.

2 and 3, the memory device 100 may include a first conductive line layer 110L, a second conductive line layer 120L, a third conductive line layer 130L, a first memory cell layer MCL1, and a second memory on the substrate 101 Unit layer MCL2.

The memory device 100 may further include an interlayer insulating layer 105 disposed on the substrate. The interlayer insulating layer 105 may include an oxide such as silicon oxide and a nitride such as silicon nitride, and may electrically separate the first conductive line layer 110L from the substrate 101.

The first conductive wire layer 110L may include a plurality of first conductive wires 110 extending in the first direction (X direction) and spaced apart from each other in the second direction (Y direction). The second conductive line layer 120L may be disposed on the first conductive line layer 110L, and may include a plurality of second conductive lines 120 extending in the second direction and spaced apart from each other in the first direction. The third conductive line layer 130L may be disposed on the second conductive line layer 120L, and may include a plurality of third conductive lines 130 extending in the first direction and spaced apart from each other in the second direction. The plurality of third conductive wires 130 and the plurality of first conductive wires 110 may be positioned at different levels in the third direction (Z direction), but may have substantially the same configuration.

With regard to the operation of the memory device, the plurality of first conductive lines 110 and the plurality of third conductive lines 130 may correspond to word lines (for example, the word line of FIG. 1 WL11, WL12, WL21, and WL22), and the plurality of second conductive lines 120 may correspond to bit lines (for example, the common bit lines BL1, BL2, BL3, and BL4 of FIG. 1). In some embodiments, the plurality of first conductive lines 110 and the plurality of third conductive lines 130 may correspond to bit lines (for example, the common bit lines BL1, BL2, BL3, and BL4 of FIG. 1), And the plurality of second conductive lines 120 may correspond to word lines (for example, the word lines WL11, WL12, WL21, and WL22 of FIG. 1). In the case where the plurality of first conductive lines 110 and the plurality of third conductive lines 130 correspond to word lines, the plurality of first conductive lines 110 may correspond to lower word lines (for example, FIG. 1 The lower word lines WL11 and WL12), and the plurality of third conductive lines 130 may correspond to upper word lines (for example, the upper word lines WL21 and WL22 in FIG. 1). Because the plurality of second conductive lines 120 can be shared by the plurality of first conductive lines 110 (ie, lower character lines) and the plurality of third conductive lines 130 (ie, upper character lines) Shared, so the plurality of second conductive lines 120 may correspond to a common bit line.

Each of the plurality of first conductive wires 110, the plurality of second conductive wires 120, and the plurality of third conductive wires 130 may include metal, conductive metal nitride, conductive metal oxide, or combination. In example embodiments, each of the plurality of first conductive wires 110, the plurality of second conductive wires 120, and the plurality of third conductive wires 130 may include W, WN, Au, Ag , Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, alloys or combinations thereof. In one embodiment, each of the plurality of first conductive wires 110, the plurality of second conductive wires 120, and the plurality of third conductive wires 130 may include a metal layer and A conductive barrier layer for covering at least a part of the metal layer. The conductive barrier layer may include, for example, Ti, TiN, Ta, TaN, or a combination thereof.

The first memory cell layer MCL1 may include a plurality of first memory cells 140-1 arranged in two dimensions separated from each other in the first direction and the second direction (for example, the first memory cell of FIG. 1 MC1). The second memory cell layer MCL2 may include a plurality of second memory cells 140-2 arranged in two dimensions separated from each other in the first direction and the second direction (for example, the second memory cell of FIG. 1 MC2).

As shown in FIG. 2, the plurality of second conductive lines 120 may cross the plurality of first conductive lines 110, and the plurality of third conductive lines 130 may cross the plurality of second conductive lines 120 . The first memory cell 140-1 may be disposed between the first conductive line layer 110L and the second conductive line layer 120L and the respective intersections of the plurality of first conductive lines 110 and the plurality of second conductive lines 120 Point at. The second memory cell 140-2 may be disposed between the second conductive line layer 120L and the third conductive line layer 130L and the plurality of second conductive lines 120 and the plurality of third conductive lines 130 respectively intersect Point at.

The first memory unit 140-1 and the second memory unit 140-2 may each have a pillar-like structure such as a square pillar, but it is not limited to this case. For example, the first memory unit 140-1 and the second memory unit 140-2 may each have various pillar shapes such as cylindrical pillars, elliptical pillars, or polygonal pillars. According to the method of forming the first memory unit 140-1 and the second memory unit 140-2, the lower portion of each of the first memory unit 140-1 and the second memory unit 140-2 may be larger than that The upper portion (for example, the width of the lower portion is greater than the width of the upper portion), or the upper portion of each of the first memory unit 140-1 and the second memory unit 140-2 may be larger than the lower portion thereof (for example, The width of the upper part is greater than the width of the lower part). In some embodiments, the first memory unit 140-1 and the second memory unit 140-2 may each have substantially vertical sidewalls, so there is almost no difference in width between the lower portion and the upper portion thereof. Although the first memory unit 140-1 and the first The second memory cell 140-2 is shown in other drawings as having substantially vertical sidewalls in addition to FIGS. 2 and 3, but the first memory cell 140-1 and the second memory cell 140-2 The lower part of each of them may be larger or smaller than the upper part thereof.

The first memory cells 140-1 may each include a first electrode layer 141-1, a first selection element layer 143-1, and a second electrode layer 145 that are sequentially disposed (or stacked) on the substrate 101 -1, the third electrode layer 147-1, the first variable resistance layer 149-1, and the fourth electrode layer 148-1. The second memory cells 140-2 may each include a fifth electrode layer 141-2 and a first memory cell layer MCL1 (or the plurality of second conductive lines 120) sequentially disposed (or stacked) on the first memory cell layer MCL1 The second selection element layer 143-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, the second variable resistance layer 149-2, and the eighth electrode layer 148-2. The first memory unit 140-1 and the second memory unit 140-2 may have substantially the same structure and substantially the same material. Therefore, for the sake of brevity, the first memory unit 140-1 will be mainly described below.

The first variable resistance layer 149-1 (for example, the variable resistance layer ME of FIG. 1) may include a phase change material that can be reversibly changed between the first state and the second state depending on the heating time. For example, the variable resistance layer 149-1 may include a certain material whose phase is attributable to joule heat generated by the voltage applied to the two terminals of the variable resistance layer 149-1. Change reversibly, and the resistance of this material can be changed due to phase change. More specifically, the phase change material may exhibit a high resistance state in an amorphous phase and may exhibit a low resistance state in a crystalline phase. The high resistance state can be defined as a "0" state and the low resistance state can be defined as a "1" state, and the data can be stored in the first variable resistance layer 149-1.

In some embodiments, the first variable resistance layer 149-1 may include one or more elements from group VI of the periodic table (for example, one or more chalcogen elements), and optionally include elements from group III, One or more chemical modifiers of group IV and/or group V. The first variable resistance layer 149-1 may include Ge-Sb-Te. The chemical composition notation represented by the hyphen (-) used herein represents the elements contained in a specific mixture or compound, and is used to represent all chemical structures containing the represented elements. For example, the Ge-Sb-Te material may include Ge ₂ Sb ₂ Te ₅ , Ge ₂ Sb ₂ Te ₇ , Ge ₁ Sb ₂ Te ₄ or Ge ₁ Sb ₄ Te ₇ .

In addition to the Ge-Sb-Te material, the first variable resistance layer 149-1 may also include multiple phase change materials. For example, the first variable resistance layer 149-1 may include at least one of the following: Ge-Te, Sb-Te, In-Se, Ga-Sb, In-Sb, As-Te, Al- Te, Bi-Sb-Te(BST), In-Sb-Te(IST), Ge-Sb-Te, Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te, Sn- Sb-Bi, Ge-Te-O, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge- Te-Sn-Ni, Ge-Te-Sn-Pd, Ge-Te-Sn-Pt, In-Sn-Sb-Te, As-Ge-Sb-Te, and combinations thereof.

The elements constituting the first variable resistance layer 149-1 may have various stoichiometric ratios. According to the chemical calculation ratio of the elements, the crystallization temperature, melting temperature, phase change rate and data retention characteristics of the first variable resistance layer 149-1 can be controlled (data retention characteristic).

The first variable resistance layer 149-1 may further include at least one impurity element. Impurity elements may include, for example, carbon (C), nitrogen (N), silicon (Si), bismuth (Bi), and At least one of tin (Sn). The operating current of the memory device 100 can be changed by impurity elements. Furthermore, the first variable resistance layer 149-1 may further include metal. For example, the first variable resistance layer 149-1 may include at least one of the following: aluminum (Al), gallium (Ga), zinc (Zn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pa), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), lead (Pb) and polonium (Po). The metal can increase the electrical conductivity and thermal conductivity of the first variable resistance layer 149-1 to increase its crystallization rate, thereby increasing the programming speed. In addition, the metal can improve the data retention characteristics of the first variable resistance layer 149-1.

The first variable resistance layer 149-1 may include a multi-layered structure, and two or more layers having different physical properties are stacked in the multi-layered structure. The number or thickness of the plurality of layers constituting the multilayer structure may not be limited. The barrier layer may be further inserted between the plurality of layers constituting the multilayer structure. The barrier layer can be used to prevent the diffusion of materials between the multiple layers. When a subsequent layer of the plurality of layers is formed, the barrier layer can reduce the diffusion of the material contained in the previous layer of the plurality of layers.

The first variable resistance layer 149-1 may include a superlattice structure constructed from a plurality of layers including different materials and alternately stacked on each other. For example, the first variable resistance layer 149-1 may include a stacked structure, and a first layer formed of Ge-Te and a second layer formed of Sb-Te are alternately stacked in the stacked structure. However, the first layer and the second layer are not limited to this case, and may include various materials described above.

The phase change material as the first variable resistance layer 149-1 can be described above, but the aspect of the concept of the present invention is not limited to this case. The first variable resistance layer 149-1 of the memory device 100 may include various materials having resistance changing properties.

In some embodiments, the memory device 100 may be a resistive random access memory (ReRAM) device under the condition that the first variable resistance layer 149-1 includes a transition metal oxide. In the first variable resistance layer 149-1 containing the transition metal oxide, at least one electrical path can be established or disappeared by a programming operation. The first variable resistance layer 149-1 may have a low resistance value when the electric path is established and may have a high resistance value when the electric path disappears. By using the difference in resistance value, the memory device 100 can store data.

x

1.5及0

y

0.5的範圍內選擇值x及值y，但並不限於此情形。 In the case where the first variable resistance layer 149-1 includes a transition metal oxide, the transition metal oxide may include Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, and Cr At least one of them. For example, the first variable resistance layer 149-1 including a transition metal oxide may include a single layer or multiple layers, formed of at least one of the following: Ta ₂ O _5-x , ZrO _2-x , TiO _2-x , HfO _2-x , MnO _2-x , Y ₂ O _3-x , NiO _1-y , Nb ₂ O _5-x , CuO _1-y and Fe ₂ O _3-x . In the above materials, they can be set at 0

x

1.5 and 0

y

The value x and the value y are selected within the range of 0.5, but it is not limited to this case.

In other embodiments, the first variable resistance layer 149-1 includes a magnetic tunnel junction (MTJ) with two electrodes formed of a magnetic material and a dielectric layer inserted between the two electrodes. In the case of a) structure, the memory device 100 may be a magnetic random access memory (MRAM) device.

One of the two electrodes may be a magnetization pinned layer, and the other of the two electrodes may be a magnetization free layer. The dielectric layer may be a tunnel barrier layer. The magnetized pinned layer may have a pinned magnetization direction, and the magnetized free layer may have a direction parallel to or anti-parallel to the magnetic The variable magnetization direction of the pinned magnetization direction of the pinned layer. The magnetization direction of the magnetization pinned layer and the magnetization free layer may be parallel to the surface of the tunnel barrier layer, but it is not limited to this case. The magnetization direction of the magnetization pinned layer and the magnetization free layer may be perpendicular to the surface of the tunnel barrier layer.

In the case where the magnetization direction of the magnetization free layer is parallel to the magnetization direction of the magnetization pinned layer, the first variable resistance layer 149-1 may have a first resistance value. Alternatively, in a situation where the magnetization direction of the magnetization free layer is antiparallel to the magnetization direction of the magnetization pinned layer, the first variable resistance layer 149-1 may have the second resistance value. By using the difference between the first resistance value and the second resistance value, the memory device 100 can store data. The magnetization direction of the magnetization free layer can be changed by the spin torque of electrons in the programming current.

The magnetization pinned layer and the magnetization free layer may include magnetic materials. The magnetized pinned layer may further include an antiferromagnetic material that fixes the magnetization direction of the ferromagnetic material in the magnetized pinned layer. The tunnel barrier layer may include an oxide having at least one of Mg, Ti, Al, MgZn, and MgB, but is not limited to this case.

The first selection element layer 143-1 (for example, the selection element SW of FIG. 1) may serve as a current control layer for controlling the flow of current. The first selection element layer 143-1 may include a material layer whose resistance may vary depending on the voltage applied to its two terminals. For example, the first selection element layer 143-1 may include a material layer with two-way critical switching (OTS) properties. Under the condition that the first selection element layer 143-1 includes a material layer with bidirectional critical switching properties, the first selection element layer 143-1 can maintain a high resistance state, wherein the threshold voltage of the first selection element layer 143-1 When a voltage of φ is applied to the first selection element layer 143-1, current hardly flows. When a voltage greater than the threshold voltage of the first selection element layer 143-1 is applied to the first selection element layer 143-1, the first selection element layer 143-1 may be in a low resistance state, so that the current Start to flow. When the current flowing through the first selection element layer 143-1 is less than a holding current, the first selection element layer 143-1 may be switched to a high resistance state. The bidirectional critical switching property of the first selection element layer 143-1 will be described in detail later with reference to FIG. 4.

The first selection element layer 143-1 may include a chalcogenide material as a bidirectional critical switching material layer. The first selective element layer 143-1 may include one or more elements from group VI of the periodic table (for example, chalcogen elements), and optionally include one from group III, group IV, and/or group V. Or a variety of chemical modifiers. The chalcogen element contained in the first selective element layer 143-1 may include sulfur (S), selenium (Se), and/or tellurium (Te). The chalcogen elements can be characterized by divalent bonding and the existence of lone pair electrons. The divalent bonding can lead to the formation of chain and ring structures after combining chalcogen elements to form chalcogenide materials, and the absence of shared electron pairs can provide an electron source for forming conductive filaments. Trivalent modification such as aluminum (Al), gallium (Ga), indium (In), germanium (Ge), tin (Sn), silicon (Si), phosphorus (P), arsenic (As) and antimony (Sb) Agents and tetravalent modifiers can enter the chain and ring structure of chalcogen elements, and can affect the structural rigidity of chalcogenide materials. Depending on the ability to withstand crystallization or other structural reconfiguration, the structural stiffness of the chalcogenide material may result in classification of the chalcogenide material into one of a critical switching material and a phase change material.

In some embodiments, the first selection element layer 143-1 may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), indium (In), or a combination thereof. For example, the first selection element layer 143-1 may include about 14% silicon (Si) concentration, about 39% tellurium (Te) concentration, about 37% arsenic (As) concentration, and about 9% germanium ( Ge) concentration, about 1% indium (In) concentration. Here, the percentage is an atomic percentage, This totals 100% of the atoms constituting the element.

In some embodiments, the first selection element layer 143-1 may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), or a combination thereof. For example, the first selection element layer 143-1 may include about 5% silicon (Si) concentration, about 34% tellurium (Te) concentration, about 28% arsenic (As) concentration, and about 11% germanium ( Ge) concentration, about 21% sulfur (S) concentration, and about 1% selenium (Se) concentration.

In some embodiments, the first selection element layer 143-1 may include tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), antimony (Sb), or a combination thereof. For example, the first selection element layer 143-1 may include about 21% tellurium (Te) concentration, about 10% arsenic (As) concentration, about 15% germanium (Ge) concentration, and about 2% sulfur ( S) concentration, about 50% selenium (Se) concentration, and about 2% antimony (Sb) concentration.

In the memory device 100 according to example embodiments, the first selection element layer 143-1 is not limited to the bidirectional critical switching material, but includes various materials that can be used to select the device. For example, the first selection element layer 143-1 may include a diode, a tunnel junction, a bipolar junction transistor, or a mixed ionic-electronic conduction switch (MIEC).

The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may serve as electrical paths and may be formed of conductive materials. The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may include metal, conductive metal nitride, conductive metal oxide, or a combination thereof. For example, each of the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may include a TiN layer, but is not limited thereto situation. In some embodiments, each of the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may include metal or A conductive layer formed of a conductive metal nitride and at least one conductive barrier layer covering at least a part of the conductive layer. The conductive barrier layer may include metal oxide, metal nitride, or a combination thereof, but is not limited to this case.

In some embodiments, the third electrode layer 147-1 and/or the fourth electrode layer 148-1 in contact with the first variable resistance layer 149-1 may include a material capable of producing enough to change the first variable resistance layer 149-1 Phase of thermal conductive material. For example, the third electrode layer 147-1 or the fourth electrode layer 148-1 may include a refractory metal, a refractory metal nitride, and/or a carbon-based conductive material. The third electrode layer 147-1 or the fourth electrode layer 148-1 may include, for example, TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or combinations thereof. However, the third electrode layer 147-1 or the fourth electrode layer 148-1 is not limited to this case.

In some embodiments, a heating electrode layer may be further inserted between the first variable resistance layer 149-1 and the third electrode layer 147-1 or the first variable resistance layer 149-1 and the fourth electrode layer 147-1. Between the electrode layers 148-1. The heating electrode layer may include a conductive material capable of generating heat sufficient to change the phase of the variable resistance layer 149-1. For example, the heating electrode layer may include refractory metal, refractory metal nitride, or carbon-based conductive material. The heating electrode layer may include, for example, TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN or a combination thereof, but not limited to this case.

Although the first variable resistance layer 149-1 is shown in FIGS. 2 and 3 as being disposed on the first selection element layer 143-1, the second electrode layer 145-1 and the third electrode The layer 147-1 is inserted between the first variable resistance layer 149-1 and the first selection element layer 143-1, but the aspect of the concept of the present invention is not limited to this case. Different from the situation shown in FIGS. 2 and 3, the first selection element layer 143-1 is disposed on the first variable resistance layer 149-1, in which the second electrode layer 145-1 and the third electrode layer 147-1 are inserted Between the first selection element layer 143-1 and the first variable resistance layer 149-1, and the first variable resistance layer 149-1 can be inserted between the first electrode layer 141-1 and the second electrode layer 145-1 between. For example, the first electrode layer 141-1 and/or the second electrode layer 145-1 contacting the first variable resistance layer 149-1 may include a phase capable of producing enough to change the first variable resistance layer 149-1. Thermal conductive material. Furthermore, the heating electrode layer may be further inserted between the first variable resistance layer 149-1 and the first electrode layer 141-1 and between the first variable resistance layer 149-1 and the second electrode layer 145-1.

The first electrode layer 141-1 and the fourth electrode layer 148-1 may be formed as appropriate. For example, the first electrode layer 141-1 and the fourth electrode layer 148-1 can be omitted. However, at least one of the first electrode layer 141-1 and the fourth electrode layer 148-1 may be disposed on one of the first conductive line 110 and the second conductive line 120 and the first selection element layer 143-1, respectively And/or between one of the first conductive line 110 and the second conductive line 120 and the first variable resistance layer 149-1, so as to prevent attributable to the first conductive line 110 and the second conductive line 120 Is caused by direct contact between one of the first selection element layer 143-1 and/or between one of the first conductive line 110 and the second conductive line 120 and the first variable resistance layer 149-1 Contamination or contact failure.

At least one of the second electrode layer 145-1 and the third electrode layer 147-1 may be disposed between the first selection element layer 143-1 and the first variable resistance layer 149-1 as necessary. When the first selection element layer 143-1 is based on the bidirectional critical switching property, the first selection element layer 143-1 may include a chalcogenide material in an amorphous state. According to the ratio For example, the trend of shrinking the memory device 100, in the variable resistance layer 149-1, the selection element layer 143-1, the second electrode layer 145-1, and the third electrode layer 147-1, the thickness, width and The distance in between. Therefore, during the operation of the memory device 100, the heating electrode layer (or the third electrode layer 147-1 when another heating electrode layer is not formed) may be heated to cause the phase of the first variable resistance layer 149-1 Change so that the adjacent first selection element layer 143-1 can be affected by heat. For example, the first selection element layer 143-1 may be partially crystallized by heat from the adjacent first variable resistance layer 149-1, thereby causing degradation or degradation in the first selection element layer 143-1. damage. Therefore, at least one of the second electrode layer 145-1 and the third electrode layer 147-1 may be disposed between the first selection element layer 143-1 and the first variable resistance layer 149-1 as necessary to prevent Or reduce the degradation or damage in the first selection element layer 143-1.

The first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, and the fourth electrode layer 148-1 may be formed of various materials. According to the configuration of the heating electrode layer, the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1 and the fourth electrode layer 148-1 may have varying thicknesses, respectively. For example, under the condition that the heating electrode layer is inserted between the third electrode layer 147-1 and the variable resistance layer 149-1, the third electrode layer 147-1 and the second electrode layer 145-1 can be formed as It is thick enough to prevent the heat of the heating electrode layer from being transferred to the first selection element layer 143-1. When the heating electrode is not formed and the third electrode layer 147-1 is formed of a conductive material capable of generating heat sufficient to change the phase of the first variable resistance layer 149-1, the second electrode layer 145-1 may be formed as It is thick enough to prevent the heat of the third electrode layer 147-1 from being transferred to the first selection element layer 143-1. For example, the second electrode layer 145-1 and the third electrode layer 147-1 may have a thickness of 10 nm to 100 nm, but it is not limited to this case. In addition, each of the second electrode layer 145-1 and the third electrode layer 147-1 may have at least one thermal barrier for blocking heat Wall layer. In the case where each of the second electrode layer 145-1 and the third electrode layer 147-1 has two or more thermal barrier layers, the second electrode layer 145-1 and the third electrode layer 147- Each of 1 may have a stacked structure, and the thermal barrier layer and the electrode material layer are alternately stacked in the stacked structure.

The first insulating layer 162-1 may be disposed between the plurality of first conductive lines 110. The first insulating layer 162-1 and the third insulating layer 163 may be disposed between the first memory cells 140-1 of the first memory cell layer MCL1. For example, the first insulating layer 162-1 may be disposed between the first memory cells 140-1 arranged in the second direction (Y direction), and the third insulating layer 163 may be disposed in the first direction ( X direction) between the first memory units 140-1. The third insulating layer 163 may be disposed between the second conductive lines 120 arranged in the first direction. The second insulating layer 162-2 may be arranged between the second memory cells 140-2 of the second memory cell layer MCL2 arranged in the second direction, and may be arranged on the third conductive layer arranged in the second direction. Between lines 130. The first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may be formed of the same insulating material, or in the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 At least one of may be formed of a material different from the other of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163. Each of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may be formed of oxide or nitride, and the memory cell (or device) of each memory cell layer ) Are electrically separated from each other. In some embodiments, at least one of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may be replaced by an air space. For example, at least one of the first insulating layer 162-1, the second insulating layer 162-2, and the third insulating layer 163 may not be formed, thereby between the first memory cells 140-1 and in the second A gap is formed between the memory cells 140-2. In the form of voids Next, an insulating liner with a certain thickness may be disposed between the gap and at least one of the first memory cell 140-1 and the second memory cell 140-2.

As illustrated in FIG. 3, the first selection element layer 143-1 of the first memory unit 140-1 may have a first height (or thickness) H1 in the third direction (the Z direction in FIG. 2), and the second memory The second selection element layer 143-2 of the body unit 140-2 may have a second height (or thickness) H2 smaller than the first height H1 in the third direction. In some embodiments, the first height H1 of the first selection element layer 143-1 of the first memory cell 140-1 may range from 10 nm to 500 nm, and the second selection element of the second memory cell 140-2 The second height H2 of the layer 143-2 may range from 5 nm to 450 nm, but is not limited to this case.

In some embodiments, the range of the second height H2 of the second selection element layer 143-2 may be, for example, 50% to 90% of the first height H1 of the first selection element layer 143-1, but is not limited to This situation.

The first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 can be controlled so that the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 is equal to The magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 is substantially the same.

In some embodiments, the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 can be controlled so that the first threshold voltage of the first selection element layer 143-1 The magnitude difference between V _T1 and the second threshold voltage V _{T2 of the} second selection element layer 143-2 is less than 0.5V. For example, the magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 may be smaller than or greater than 0.5V than the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1.

In some embodiments, the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 can be controlled so that the second threshold voltage of the second selection element layer 143-2 The range of the magnitude of V _T2 is, for example, 80% to 120% of the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1. The range of the magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 may be, for example, 90% to 110% of the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1.

The range of the magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 is, for example, 80% to 120% of the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 Under conditions, the difference between the electrical properties of the first memory cell MC1 and the electrical properties of the second memory cell MC2 can be reduced, thereby increasing the sensing margin of the read/write operation of the memory device 100.

Hereinafter, the relationship between the threshold voltage and the electrical properties of the selection element layers 143-1 and 143-2 with bidirectional critical switching (OTS) properties will be described in detail with reference to FIGS. 4 to 6.

FIG. 4 is a schematic diagram illustrating a voltage-current curve 40 of a two-way critical switching element representing the properties of a two-way critical switching (OTS). FIG. 4 schematically illustrates the current flowing through the bidirectional critical switching element in response to the voltage applied to the two terminals of the bidirectional critical switching element.

Referring to FIG. 4, the first curve 41 may represent the voltage-current relationship in a state where current does not flow through the bidirectional critical switching element. Here, the bidirectional threshold switching element can be used as a switching element having a threshold voltage V _T at the first voltage level 43. When the voltage gradually increases from the state where the current and the voltage are at zero, the current can hardly flow through the bidirectional critical switching element until the voltage reaches the critical voltage V _T (ie, the first voltage level 43). However, once the voltage exceeds the threshold voltage V _T , the current flowing through the bidirectional threshold switching element can increase sharply, and the voltage applied across the bidirectional threshold switching element can be reduced to the second voltage level 44 (or saturation voltage Vs ).

The second curve 42 may represent the voltage-current relationship in a state where current flows through the bidirectional critical switching element. As the current flowing through the bidirectional critical switching element increases above the first current level 46, the voltage applied across the bidirectional critical switching element may increase slightly greater than the second voltage level 44. For example, although the current flowing through the bidirectional critical switching element significantly increases from the first current level 46 to the second current level 47, the voltage applied across the bidirectional critical switching element can be from the second voltage level level 44 increased slightly. For example, once the current flows through the bidirectional critical switching element, the voltage applied across the bidirectional critical switching element can be almost maintained at the saturation voltage Vs (ie, the second voltage level 44). When the current decreases to less than the maintenance current level (ie, less than the first current level 46), the bidirectional critical switching element can switch back to the resistance state, thereby effectively blocking the current until the voltage increases to the critical voltage V Until _T.

5A and 5B are schematic diagrams illustrating an operation method of a memory device having a stacked cross-point structure according to example embodiments.

5A and 5B illustrate the read operation or write operation of the memory device having a stacked cross-point structure. In the stacked cross-point structure, the first lower memory cell MC11 and the second lower memory cell MC12 and The first upper memory cell MC21 and the second upper memory cell MC22 can be respectively disposed between the common bit line BL and the first lower word line WL11 and the second lower word line WL12 below the common bit line BL And between the common bit line BL and the first upper word line WL21 and the second upper word line WL22 above the common bit line BL.

Referring to FIG. 5A, the first lower memory cell MC11 at the intersection of the first lower word line WL11 and the common bit line BL can be selected. In order to select the first lower word line WL11, a lower voltage Vlow (for example, a bit line selection voltage or an inhibit voltage) can be applied to the common bit line BL and the word line selection voltage V _{WL(Sel) can be} applied To the first lower character line WL11.

For example, a write operation can be performed to store data in the first lower memory cell MC11 (for example, a write operation can be performed by a reset operation and a setting operation), and a read operation can be performed to read Get the data stored in the first lower memory unit MC11. A word line selection voltage V _WL(Sel) having a relatively high value can be applied to the selected first lower word line WL11, and a lower voltage Vlow having a relatively low value can be applied to the common bit line BL, therefore, a first switching voltage having a difference (V _WL(Sel) -Vlow) can be applied across the first lower memory cell MC11. The magnitude of the first switching voltage may be greater than the magnitude of the threshold voltage of the selection element SW having the bidirectional threshold switching property. Therefore, the selection element SW of the first lower memory cell MC11 can be turned on, so that the first current I _MC11 flows through the variable resistance layer R of the first lower memory cell MC11. In one embodiment, the magnitude of the first current I _MC11 may be changed based on the resistance state (for example, set or reset) of the variable resistance layer R of the first lower memory cell MC11.

At the same time, the word line unselected voltage V _{WL(Unsel) can be} applied to the unselected second lower word line WL12 and the first upper word line WL21 and the second upper word line WL22. Therefore, an off voltage having a difference (V _WL(Unsel) -Vlow) can be applied across the unselected memory cells MC12, MC21, and MC22. The magnitude of the turn-off voltage may be smaller than the magnitude of the threshold voltage of the selection element SW having a bidirectional critical switching property, so the selection element SW may not be turned on. As a result, current may not flow through the variable resistance layer R of the unselected memory cells MC12, MC21, and MC22.

Referring to FIG. 5B, the first upper memory cell MC21 at the intersection of the first upper word line WL21 and the common bit line BL can be selected. In order to select the first upper memory cell MC21, the lower voltage Vlow may be applied to the common bit line BL and the word line selection voltage V _{WL(Sel) may be} applied to the first upper word line WL21. Therefore, a second switching voltage having a difference voltage (V _WL(Sel) -Vlow) can be applied across the first upper memory cell MC21. The magnitude of the second switching voltage may be greater than the threshold voltage of the selection element SW having a bidirectional threshold switching property. Therefore, the selection element SW of the first upper memory cell MC21 can be turned on, so that the second current I _MC21 flows through the variable resistance layer R of the first upper memory cell MC21.

Compared to FIGS. 5A and 5B, the magnitude of the first switching voltage applied across the selected first lower memory cell MC11 may be equal to the second switching voltage applied across the selected first upper memory cell MC21 The magnitude of the voltage. However, the direction of the first current I _MC11 flowing through the first lower memory cell MC11 may be different from the direction of the second current I _MC21 flowing through the first upper memory cell MC21. Therefore, the amount of the first current I _MC11 flowing through the first lower memory cell MC11 may be different from the amount of the second current I _MC21 flowing through the first upper memory cell MC21.

For example, a relatively high voltage can be applied to the first lower word line WL11 with respect to the selection element SW of the first lower memory cell MC11, and the selection element SW of the first upper memory cell MC21 can be A relatively high voltage is applied to the first upper word line WL21. Therefore, the selection element SW of the first lower memory cell MC11 and the selection element SW of the first upper memory cell MC21 can respectively experience electric fields in different directions. 6 will be described with reference to the electric field in different directions. Influence or effect.

FIG. 6 illustrates a voltage-current graph 60 for applying a positive voltage and a negative voltage to the bidirectional critical switching element, respectively.

Referring to FIG. 6, in the bidirectional critical switching element of the first experimental example 62 and the bidirectional critical switching element of the second experimental example 64 with different sizes, it has been found that different voltage-current distributions are obtained when positive and negative voltages are applied. (voltage-current profile). More specifically, the bidirectional critical switching element of the first experimental example 62 has a first critical voltage 56 (V ₁ ) in a period of positive voltage and a second critical voltage 58 (V ₂ ) in a period of negative voltage. It has been clearly discovered that the magnitude of the first threshold voltage 56 (V ₁ ) is greater than the magnitude of the second threshold voltage 58 (V ₂ ).

For example, the current flowing through the selection element SW and the threshold voltage of the selection element SW may vary depending on the direction of the electric field acting on the selection element SW. In FIGS. 5A and 5B, even if the selection voltage V _WL(Sel) having the same magnitude is applied to the first lower word line WL11 and the first upper word line WL21, they are connected to the first lower word line The first lower memory cell MC11 of the WL11 and the first upper memory cell MC21 connected to the first upper word line WL21 may also have different current distributions and different threshold voltages.

This phenomenon can be understood as caused by the asymmetric defect density and composition distribution in the selection element SW. For example, the selection element SW with bidirectional critical switching properties may include chalcogenide materials. In the switching mechanism of the chalcogenide material, when a high electric field is applied to the chalcogenide material, it is known that the electron trap sites in the chalcogenide material are unevenly distributed , So that the electrons move along the electron trap site at a relatively high speed.

Furthermore, when a large number of defects are generated in the selection element SW, the electron trap The density of sites can be increased. Therefore, even in a small electric field, electrons can still move along the electron trap site, so that the threshold voltage of the selection element SW becomes reduced.

2 and 3 again, the first height H1 of the first selection element layer 143-1 of the first memory cell 140-1 may be greater than that of the second selection element layer 143-2 of the second memory cell 140-2 The second height H2. Such a structure can be formed as a result of: considering the defect density in the first selection element layer 143-1 and the second selection element layer 143-2, the first height H1 and the second height H2 are controlled so that the first selection element The magnitude of the threshold voltage of the layer 143-1 is substantially equal to the magnitude of the threshold voltage of the second selection element layer 143-2.

The defect density of the first selection element layer 143-1 positioned at the first level above the substrate 101 may be different from the defect density of the second selection element layer 143-2 positioned at the second level above the substrate 101. Here, compared to the first level, the second level means a position farther from the substrate 101 in the third direction (Z direction). For example, it means that the first selection element layer 143-1 is closer to the top surface of the substrate 101 than the second selection element layer 143-2.

Compared with the second selection element layer 143-2 at the second level, the first selection element layer 143-1 at the first level can be exposed to the process environment for a long time, such as the deposition process and/or etching to form the subsequent layer Process. In such a process environment, heat can be supplied from a chuck under the substrate 101 or from a heater to maintain a processing temperature ranging from tens of degrees Celsius to hundreds of degrees Celsius. Therefore, compared to the second selection element layer 143-2 at the second level, the first selection element layer 143-1 at the first level can be exposed to the deposition environment and/or the etching environment under a high temperature atmosphere for a long time. As a result, compared to the second selection element layer 143-2, the first selection element layer 143-1 can be easily damaged due to prolonged exposure to the deposition environment and/or etching environment, so that the first selection element layer at the first level Select component layer The defect density of 143-1 may be greater than the defect density of the second selection element layer 143-2 at the second level.

As described above, according to the switching mechanism of the selection element layers 143-1 and 143-2, under the condition that the defect density of the first selection element layer 143-1 is greater than the defect density of the second selection element layer 143-2, the first The threshold voltage of the first selection element layer 143-1 at the level may be smaller in magnitude than the threshold voltage of the second selection element layer 143-2 at the second level. The magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 can cause less sensing margin in the write operation and/or read operation, by This induces failure in the write operation and/or read operation of the memory device 100.

According to the example embodiment as described above, the first height H1 of the first selection element layer 143-1 of the first memory cell 140-1 and the second selection element layer 143 of the second memory cell 140-2 can be controlled The second height H2 of -2 makes the magnitude of the threshold voltage of the first selection element layer 143-1 and the magnitude of the threshold voltage of the second selection element layer 143-2 substantially the same.

For example, because the first height H1 of the first selection element layer 143-1 of the first memory cell 140-1 is greater than the second height H2 of the second selection element layer 143-2 of the second memory cell 140-2 Therefore, even if the switching voltage applied to the first selection element layer 143-1 is the same as the switching voltage applied to the second selection element layer 143-2, the magnitude of the electric field applied to the first selection element layer 143-1 will be smaller than the applied switching voltage. The magnitude of the electric field on the second selection element layer 143-2. Therefore, under the condition that the first selection element layer 143-1 contains a large defect density, the threshold voltage of the first selection element layer 143-1 can be prevented from being reduced due to defects, and the first selection element layer 143- can be reduced. The difference between the threshold voltage of 1 and the threshold voltage of the second selection element layer 143-2.

Furthermore, the existence of the difference between the first height H1 of the first selection element layer 143-1 and the second height H2 of the second selection element layer 143-2 may be the result of the following: Considering the application to the first selection element layer 143- 1 and the direction of the electric field of the second selection element layer 143-2 to control the first height H1 and the second height H2, so that the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 Essentially the same.

As described with reference to FIGS. 5A, 5B, and 6, compared to when a positive voltage is applied to the first selection element layer 143-1 and the second selection element layer 143-2, when a negative voltage is applied to the first selection element layer 143-2 When the element layer 143-1 and the second selection element layer 143-2 are used, it has been found that the first selection element layer 143-1 and the second selection element layer 143-2 have lower threshold voltages. Therefore, under the general condition that the first selection element layer 143-1 and the second selection element layer 143-2 have the same height, when a negative voltage is applied to the first selection element layer 143-1 and a positive voltage is applied to the second selection element layer 143-1 When the element layer 143-2 is selected, the threshold voltage of the first selection element layer 143-1 (for example, 58 (V ₂ ) in FIG. 6) may be smaller in magnitude than the threshold voltage of the second selection element layer 143-2 (for example, , 56 (V ₁ ) in Figure 6). For example, when a relatively low voltage is applied to the second conductive line 120 (for example, the common bit line BL) and a relatively high voltage is applied to the first conductive line 110 (for example, the first lower word line WL11) ) And the third conductive line 130 (for example, the first upper word line WL21) (that is, when the inhibit voltage or the bit line selection voltage is applied to the second conductive line 120 and will be greater than the inhibit voltage or bit line selection When the word line selection voltage of the voltage is applied to the first conductive line 110 and the third conductive line 130), the threshold voltage of the first selection element layer 143-1 (for example, 58 (V ₂ ) in FIG. 6) may be in the magnitude Is smaller than the threshold voltage of the second selection element layer 143-2 (for example, 56 (V ₁ ) in FIG. 6).

According to the example embodiment as described above, because the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, Therefore, when a negative voltage is applied to the first selection element layer 143-1 and a positive voltage is applied to the second selection element layer 143-2, the electric field acting on the first selection element layer 143-1 may be smaller in magnitude than the effect The electric field on the second selection element layer 143-2. Therefore, the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 can be reduced, and the electrical properties of the first memory cell 140-1 and the second memory can be reduced. The difference in electrical properties of the body unit 140-2.

As a result, since the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 is reduced, the write operation and/or read operation of the memory device 100 can be increased It can prevent or reduce the failure of the write operation and/or read operation of the memory device 100 due to the reduction of the sensing margin. Therefore, the reliability of the memory device 100 can be improved.

FIGS. 7-13 are respectively cross-sectional views illustrating memory devices 100A, 100B, 100C, 100D, 100E, 100F, and 100G according to example embodiments, and illustrate along the lines AA' and B-B of FIG. 2 'The cross section taken. In the embodiments related to FIGS. 7 to 13, the same elements as those described in the embodiments of FIGS. 1 to 6 will be indicated by the same drawing element symbols or the same reference designation symbols.

Referring to FIG. 7, in the memory device 100A according to the example embodiment, the first height H1A of the first selection element layer 143-1 of the first memory cell 140-1 is smaller than the second height H1A of the second memory cell 140-2 The second height H2A of the element layer 143-2 is selected. The first height H1A of the first selection element layer 143-1 and the second height H2A of the second selection element layer 143-2 can be controlled so that the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 is equal to The magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 is substantially the same. For example, the range of the magnitude of the second threshold voltage V _T2 of the second selection element layer 143-2 may be, for example, 80% of the magnitude of the first threshold voltage V _T1 of the first selection element layer 143-1 To 120%, preferably 90% to 110%.

In some embodiments, the first height H1A of the first selection element layer 143-1 and the second height H2A of the second selection element layer 143-2 can be controlled so that the first threshold voltage of the first selection element layer 143-1 is The magnitude difference between V _T1 and the second threshold voltage V _{T2 of the} second selection element layer 143-2 is within a range of less than 0.5V.

In some embodiments, the first height H1A of the first selection element layer 143-1 may range from, for example, 5 nm to 450 nm, and the second height H2A of the second selection element layer 143-2 may be, for example, 10 nm. To 500nm, but not limited to this case. For example, the range of the first height H1A of the first selection element layer 143-1 may be 50% to 90% of the second height H2A of the second selection element layer 143-2, but is not limited to this case.

As described with reference to FIGS. 5A, 5B, and 6, compared to when a positive voltage is applied to the first selection element layer 143-1 and the second selection element layer 143-2, when a negative voltage is applied to the first selection element layer 143-2 When the element layer 143-1 and the second selection element layer 143-2 are used, it has been found that the first selection element layer 143-1 and the second selection element layer 143-2 have lower threshold voltages. Therefore, under the general condition that the first selection element layer 143-1 and the second selection element layer 143-2 have the same height, when a positive voltage is applied to the first selection element layer 143-1 and a negative voltage is applied to the second selection element layer 143-1 When selecting the element layer 143-2, considering the direction of the electric field, the threshold voltage of the second selection element layer 143-2 may be smaller in magnitude than the threshold voltage of the first selection element layer 143-1. For example, when a relatively high voltage is applied to the second conductive line 120 (for example, the common bit line BL) and a relatively low voltage is applied to the first conductive line 110 (for example, the first lower word line WL11) ) And the third conductive line 130 (for example, the first upper word line WL21) (that is, when the inhibit voltage or the bit line selection voltage is applied to the second conductive line 120 and will be less than the inhibit voltage or bit line When the word line selection voltage of the line selection voltage is applied to the first conductive line 110 and the third conductive line 130), the threshold voltage of the second selection element layer 143-2 may be smaller in magnitude than the first selection element layer 143-1 The critical voltage.

According to example embodiments, because the second height H2A of the second selection element layer 143-2 is greater than the first height H1A of the first selection element layer 143-1, when a positive voltage is applied to the first selection element layer 143-1 and When a negative voltage is applied to the second selection element layer 143-2, the electric field applied to the second selection element layer 143-2 may be smaller in magnitude than the electric field applied to the first selection element layer 143-1. For example, the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 can be reduced, and the electrical properties and the first memory cell 140-1 can be reduced. The difference in electrical properties of the two memory unit 140-2.

As a result, since the magnitude difference between the threshold voltage of the first selection element layer 143-1 and the threshold voltage of the second selection element layer 143-2 is reduced, the write operation and/or read operation of the memory device 100A can be increased It can prevent or reduce the failure of the write operation and/or read operation of the memory device 100A due to the reduction of the sensing margin. Therefore, the reliability of the memory device 100A can be improved.

Referring to FIG. 8, in the memory device 100B according to example embodiments, a first inner spacer 152-1 may be formed on the sidewall of the first memory cell 140-1, and a second inner spacer 152 -2 may be formed on the sidewall of the second memory unit 140-2. The first inner spacer 152-1 may cover the sidewalls of the first electrode layer 141-1 and the first selection element layer 143-1 of the first memory cell 140-1, and the second inner spacer 152-2 may cover the first The sidewalls of the fifth electrode layer 141-2 and the second selection element layer 143-2 of the second memory cell 140-2. The first inner spacer 152-1 and the second inner spacer 152-2 can enclose the first memory unit 140-1 and the second memory The sidewalls of the body unit 140-2 protect the first memory unit 140-1 and the second memory unit 140-2, and preferably protect the first selection element layer 143-1 and the second selection element layer 143- respectively. 2. For example, each of the first inner spacer 152-1 and the second inner spacer 152-2 may include an insulating material.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIG. 8, the aspect of the concept of the present invention is not limited to this case. For example, the first height H1 of the first selection element layer 143-1 is smaller than the second height H2 of the second selection element layer 143-2.

Although the first electrode layer 141-1 and the fifth electrode layer 141-2 have the same thickness, as illustrated in FIG. 8, the aspect of the concept of the present invention is not limited to this case. For example, the thickness of the first electrode layer 141-1 is greater than or less than the thickness of the fifth electrode layer 141-2.

In some embodiments, the first electrode layer 141-1, the fifth electrode layer 141-2, the first selection element layer 143-1 and the second selection element layer 143-2 may be formed by a damascene process. , The second electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, the sixth electrode layer 145-2, the seventh electrode layer 147-2, and the eighth electrode layer 145-1 can be formed by an etching process. The electrode layer 148-2 and the first variable resistance layer 149-1 and the second variable resistance layer 149-2. Therefore, the first electrode layer 141-1, the fifth electrode layer 141-2, and the first selection element layer 143-1 and the second selection element layer 143-2 may each have a width (for example, in the first direction or the second direction). Top) Narrow structure down.

In some embodiments, when the first electrode layer 141-1 and the first selection element layer 143-1 are formed by a damascene process, the first inner spacer 152-1 may be formed in the trench (not shown) And then the first electrode layer 141-1 and the first selection element layer 143-1 can be sequentially formed on the side wall with the first inner spacer 152-1 To fill the trench. The second electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, and the first variable resistance layer 149-1 may be formed on the first selection element layer 143-1. The fifth electrode layer 141-2 and the second selection element layer 143-2 can be formed by a process similar to the process of forming the first electrode layer 141-1 and the first selection element layer 143-1.

Referring to FIG. 9, in the memory device 100C according to example embodiments, a first upper spacer 155-1 may be formed on the sidewall of the first memory cell 140-1, and a second upper spacer 155 -2 may be formed on the sidewall of the second memory unit 140-2. The upper spacer 155-1 may cover the sidewall of the first variable resistance layer 149-1 of the first memory cell 140-1, and the second upper spacer 155-2 may cover the second memory cell 140-2 Two sidewalls of the variable resistance layer 149-2. The first upper spacer 155-1 and the second upper spacer 155-2 can enclose the sidewalls of the first memory unit 140-1 and the second memory unit 140-2 to protect the first memory unit 140-1, respectively And the second memory unit 140-2, preferably protect the first variable resistance layer 149-1 and the second variable resistance layer 149-2, respectively. For example, each of the first upper spacer 155-1 and the second upper spacer 155-2 may include an insulating material.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIG. 9, the aspect of the concept of the present invention is not limited to this case. For example, the first height H1 of the first selection element layer 143-1 is smaller than the second height H2 of the second selection element layer 143-2.

In some embodiments, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 can be formed by a damascene process, and the first electrode layer 141-1 and the second variable resistance layer 149-2 can be formed by an etching process. The electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, the first selection element layer 143-1 and the second selection element layer 143-2, and the fifth The electrode layer 141-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, and the eighth electrode layer 148-2. Therefore, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may each have a structure with a narrower width (for example, in the first direction or the second direction) downward.

In some embodiments, when the first variable resistance layer 149-1 is formed by a damascene process, the first upper spacer 155-1 can be formed on the sidewall of the trench (not shown), and then The first variable resistance layer 149-1 is formed in the trench having the first upper spacer 155-1 to fill the trench. The second variable resistance layer 149-2 can be formed by a process similar to the process of forming the first variable resistance layer 149-1.

In an example embodiment, the memory device (not shown) may include a plurality of first memory units 140-1 and a plurality of second memory units 140-2. Each of the first memory cells 140-1 may include first internal spacers 152-1 formed on the sidewalls of the first selection element layer 143-1 and formed on the first variable resistance layer 149-1 The first upper spacer 155-1 on the side wall. Each of the second memory cells 140-2 may include a second internal spacer 152-2 formed on the sidewall of the second selection element layer 143-2 and a second internal spacer 152-2 formed on the second variable resistance layer 149-2 The second upper spacer 155-2 on the side wall.

10, in the memory device 100D according to example embodiments, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "L" cross-sectional shape. Specifically, the first electrode layer 141-1, the second electrode layer 145-1, the third electrode layer 147-1, the fourth electrode layer 148-1, and the first selection element layer 143- can be formed by an etching process. 1 and the second selection element layer 143-2, the fifth electrode layer 141-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, and the eighth electrode layer 148-2, and can be made by a damascene process Form the first variable resistance layer 149-1 and the second variable resistance layer 149-2.

The first upper spacer 155-1 and the second upper spacer 155-2 may be formed on the sidewalls of the first variable resistance layer 149-1 and the second variable resistance layer 149-2, respectively. Because the first variable resistance layer 149-1 and the second variable resistance layer 149-2 have an "L" cross-sectional shape, the first upper spacer 155-1 and the second upper spacer 155-2 may be formed as Asymmetric structure.

According to the example process for forming the first variable resistance layer 149-1 and the second variable resistance layer 149-2, it can be on each of the third electrode layer 147-1 and the seventh electrode layer 147-2 An insulating layer is formed, and trenches can be formed in the insulating layer. The trench may be formed to overlap with each of the adjacent first selection element layer 143-1 and the adjacent second selection element layer 143-2. The first material layer for forming the variable resistance layer may be thinly formed in the trench and on the insulating layer, and then the second material layer for forming the upper spacer may be formed. A planarization process such as a chemical mechanical polishing process may be performed on the first material layer and the second material layer until the top surface of the insulating layer is exposed. After the planarization process, a mask pattern can be used to etch the first material layer and the second material layer to serve as an etch mask to interact with the first memory cell 140-1 and the second memory cell. Unit 140-2 is aligned. Therefore, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "L" cross-sectional shape, and the first upper spacer 155-1 and the second upper spacer 155-2 They are respectively formed on the sidewalls of the first variable resistance layer 149-1 and the second variable resistance layer 149-2.

Referring to FIG. 11, in the memory device 100E according to example embodiments, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "I" cross-sectional shape. The first variable with the "L" cross-sectional shape of Figure 10 can be formed by and The manufacturing process of the resistance layer 149-1 and the second variable resistance layer 149-2 is similar to forming the first variable resistance layer 149-1 and the second variable resistance layer 149-2 having an "I" cross-sectional shape. For example, after thinly forming the first material layer for forming the variable resistance layer in the trench and on the insulating layer, an anisotropic etching process can be performed on the first material layer, so that The first material layer only remains on the sidewall of the trench. A second material layer including an insulating material may be formed to cover the first material layer. A planarization process (for example, a chemical mechanical polishing process) may be performed to expose the top surface of the insulating layer. After the planarization process, the mask pattern may be used to etch the second material layer to serve as an etching mask to align with the first memory cell 140-1 and the second memory cell 140-2. Therefore, the first variable resistance layer 149-1 and the second variable resistance layer 149-2 may be formed to have an "I" cross-sectional shape, and the first upper spacer 155-1 and the second upper spacer 155-2 They are respectively formed on the sidewalls of the first variable resistance layer 149-1 and the second variable resistance layer 149-2.

12, in the memory device 100F according to example embodiments, the first heating electrode layer 146-1 may be further formed between the first variable resistance layer 149-1 and the third electrode layer 147-1, and Two heating electrode layers 146-2 may be further formed between the second variable resistance layer 149-2 and the eighth electrode layer 148-2.

As illustrated in FIG. 12, the first variable resistance layer 149-1 and the first heating electrode layer 146-1 can be arranged in order in the direction from the second conductive line 120 to the first conductive line 110, and the The second variable resistance layer 149-2 and the second heating electrode layer 146-2 are sequentially arranged in the direction of the two conductive wires 120 facing the third conductive wire 130. Therefore, with respect to the second conductive line 120, the configuration of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory cell 140-1 can be the same as that of the second memory cell 140-2. The arrangement of the second variable resistance layer 149-2 and the second heating electrode layer 146-2 in the figure is symmetrical. Therefore, the difference between the resistance value of the first variable resistance layer 149-1 and the resistance value of the second variable resistance layer 149-2 can be reduced. For example, when each of the first variable resistance layer 149-1 and the second variable resistance layer 149-2 includes GeSbTe, the diffusion rate of positive ions (for example, Sb ⁺ ) and negative ions The diffusivity of (for example, Te ⁻ ) may be different from each other in the first variable resistance layer 149-1 and the second variable resistance layer 149-2. When a negative voltage is applied to the first variable resistance layer 149-1 and a positive voltage is applied to the second variable resistance layer 149-2, the first variable resistance layer 149-1 and the second variable resistance layer 149 In -2, the difference between the diffusivity of negative ions and the diffusivity of positive ions can induce a local concentration change. Therefore, the resistance value of the first variable resistance layer 149-1 and the resistance value of the second variable resistance layer 149-2 may be different from each other.

According to example embodiments, as compared to the second conductive line 120, the stacked structure of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory cell 140-1 and the second memory The stacked structure of the second heating electrode layer 146-2 and the second variable resistance layer 149-2 in the body unit 140-2 is symmetrical, so the resistance value of the first variable resistance layer 149-1 and the second resistance value can be reduced. The difference between the resistance values of the variable resistance layer 149-2 allows each of the first memory cell 140-1 and the second memory cell 140-2 to have uniform operating properties. The resistance value of each of the first variable resistance layer 149-1 and the second variable resistance layer 149-2 is assumed to be in the same state (for example, a set state or a reset state).

Referring to FIG. 13, in the memory device 100G according to example embodiments, the first heating electrode layer 146-1 may be further formed between the first variable resistance layer 149-1 and the fourth electrode layer 148-1, and Two heating electrode layers 146-2 may be further formed between the second variable resistance layer 149-2 and the seventh electrode layer 147-2.

As illustrated in FIG. 13, with respect to the second conductive line 120, the configuration of the first variable resistance layer 149-1 and the first heating electrode layer 146-1 in the first memory cell 140-1 can be the same as that of the second memory cell. The second variable resistance layer 149-2 and the second heating electrode layer 146-2 in the unit 140-2 are arranged symmetrically. As described above, the difference between the resistance value of the first variable resistance layer 149-1 and the resistance value of the second variable resistance layer 149-2 can be reduced, so that the first memory cell 140-1 and the second memory Each of the body units 140-2 may have uniform operation attributes.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIGS. 10 to 13, the aspect of the concept of the present invention is not limited to this case . For example, the first height H1 of the first selection element layer 143-1 may be formed to be smaller than the second height H2 of the second selection element layer 143-2.

In the example embodiments described with reference to FIGS. 1 to 13, it is described that the first memory cell 140-1 and the second memory cell 140-2 are vertically arranged on the first conductive line 110, the second conductive line 120, and the third conductive line. The structure between the conductive lines 130, but the aspect of the concept of the present invention is not limited to this case. In some embodiments, an insulating layer (not shown) may be formed on the third conductive line 130, and at least one stacked structure having a cross-point array as described with reference to FIGS. 1 to 13 may be disposed on the insulating layer.

FIG. 14 is a perspective view illustrating a memory device 200 according to an example embodiment, and FIG. 15 is a cross-sectional view taken along the line 2A-2A′ of FIG. 14 according to an example embodiment.

14 and 15, the memory device 200 may include a drive circuit region (drive circuit region) 210 disposed on the substrate 102 at a first level, and a memory disposed on the drive circuit region 210 at a second level Cell array area (memory cell array region)MCA.

Here, the level means the height (or position) spaced from the substrate 102 in the vertical direction (that is, the Z direction in FIGS. 14 and 15). The first level is closer to the substrate 102 than the second level. The driving circuit area 210 may be an area where peripheral circuits (or driving circuits) for driving memory cells in the memory cell area MCA are arranged. For example, the peripheral circuits in the driving circuit area 210 may include circuits that process data input to the memory cells in the memory cell array area MCA or data output from the memory cells in the memory cell array area MCA. Peripheral circuits may include, for example, page buffers, latch circuits, cache circuits, column decoders, sense amplifiers, Data in/out circuit or row decoder.

The active region AC used for the peripheral circuit (or driving circuit) can be defined by the device isolation layer 104 in the substrate 102. A plurality of transistors TR constituting the peripheral circuit in the driving circuit area 210 may be formed on and in the active area AC. The plurality of transistors TR may each include a gate G, a gate insulating layer GD, and source/drain regions SD. An insulating spacer 106 can be formed on the opposite sidewall of the gate G, and an etch stop layer 108 can be formed on the gate G and the insulating spacer 106. The etch stop layer 108 may include an insulating material, for example, silicon nitride or silicon oxynitride.

A plurality of interlayer insulating layers 212A, 212B, and 212C may be sequentially stacked on the etch stop layer 108. Each of the plurality of interlayer insulating layers 212A, 212B, and 212C may include, for example, silicon oxide, silicon nitride, and/or silicon oxynitride.

The driving circuit area 210 may include a circuit electrically connected to the plurality of transistors TR Multilevel interconnection structure 214. The multilayer interconnect structure 214 may be covered by the plurality of interlayer insulating layers 212A, 212B, and 212C. The multilayer interconnection structure 214 may include a first contact 216A, a first interconnection layer 218A, a second contact 216b, and a second contact 216A that are electrically connected to each other sequentially on the substrate 102. The interconnection layer 218B. The first interconnection layer 218A and the second interconnection layer 218B may include metal, conductive metal nitride, metal silicide, or a combination thereof. The first interconnection layer 218A and the second interconnection layer 218B may include, for example, tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

Although the multi-level interconnect structure 214 includes a two-level interconnect structure with a first interconnect layer 218A and a second interconnect layer 218B, as illustrated in FIG. 15, the aspect of the concept of the present invention is not limited to this situation. For example, according to the layout of the driving circuit area 210 and the configuration or type of the gate G, the multi-level interconnect structure 214 may include a three-level or more than three-level interconnect structure.

The upper interlayer insulating layer 220 may be formed on the interlayer insulating layer 212C. The memory cell array area MCA may be disposed on the upper interlayer insulating layer 220. In the memory cell array area MCA, at least one or a combination of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, and 100G as described with reference to FIGS. 1 to 13 can be disposed.

An interconnection structure (not shown) penetrating the upper interlayer insulating layer 220 may be further arranged to electrically connect the memory cells in the memory cell array area MCA to the peripheral circuits in the driving circuit area 210.

In the memory device 200 according to the example embodiment, because the memory cell array area MCA is disposed on the driving circuit area 210, the memory device can be increased The integration degree of 200.

Although the first height H1 of the first selection element layer 143-1 is greater than the second height H2 of the second selection element layer 143-2, as illustrated in FIG. 15, the aspect of the inventive concept is not limited to this case. For example, the first height H1 of the first selection element layer 143-1 may be formed to be smaller than the second height H2 of the second selection element layer 143-2.

16A to 16I are cross-sectional views illustrating stages of a method of manufacturing a memory device 100 according to example embodiments.

The method of manufacturing the memory device 100 as illustrated in FIGS. 2 and 3 will be described with reference to FIGS. 16A to 16I. 16A to 16I illustrate the cross-sectional architecture corresponding to the cross-sections taken along the lines AA′ and B-B′ of FIG. 2 according to the process stages. The same drawing element symbols are used to denote the same elements as those in FIGS. 1 to 15, and repeated descriptions thereof are omitted for brevity.

Referring to FIG. 16A, an interlayer insulating layer 105 may be formed on the substrate 101. The interlayer insulating layer 105 may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The first conductive layer 110P can be formed on the interlayer insulating layer 105, and can form a first stacked structure CPS1, in which a preliminary first electrode layer 141-1P, a preliminary first selection element layer 143-1P, and a preliminary second electrode layer 145- 1P, the preliminary third electrode layer 147-1P, the preliminary first variable resistance layer 149-1P, and the preliminary fourth electrode layer 148-1P are sequentially formed on the first conductive layer 110P. The first stack structure CPS1 can be used to form a cross-point array.

First conductive layer 110P, preliminary first electrode layer 141-1P, preliminary first selection element layer 143-1P, preliminary second electrode layer 145-1P, preliminary third electrode layer 147-1P, preliminary first variable resistance layer 149-1P and preliminary fourth electrode layer 148-1P can be As described with reference to FIGS. 2 and 3, the first conductive line 110, the first electrode layer 141-1, the first selection element layer 143-1, the second electrode layer 145-1, the third electrode layer 147-1, The first variable resistance layer 149-1 and the fourth electrode layer 148-1 are formed of the same material.

The first mask pattern 410 may be formed on the preliminary fourth electrode layer 148-1P.

The first mask pattern 410 may include a plurality of line patterns extending in the first direction (X direction in FIG. 2) and spaced apart from each other in the second direction (Y direction in FIG. 2). The first mask pattern 410 may include a single layer or a multilayer stack. The first mask pattern 410 may include, for example, a photoresist pattern, a silicon oxide pattern, a silicon nitride pattern, a silicon oxynitride pattern, and a polysilicon pattern. (poly-silicon pattern) or a combination thereof, but not limited to this case. The first mask pattern 410 may be formed of various materials.

16B, the first mask pattern 410 can be used as an etching mask to sequentially and anisotropically etch the first stacked structure CPS1 and the first conductive layer 110P to separate the first stacked structure CPS1 into a plurality of first The lines CPL1 are stacked and the first conductive layer 110P is separated into a plurality of first conductive lines 110.

As a result, the plurality of first conductive lines 110 and the plurality of first stack lines CPL1 may be formed to extend in the first direction. The plurality of first conductive lines 110 may be spaced apart from each other in the second direction, and the plurality of first stack lines CPL1 may be spaced apart from each other in the second direction. The plurality of first conductive lines 110 may form a first conductive line layer 110L. The plurality of first stack lines CPL1 may each include a first electrode layer line 141-1L, a first selection element layer line 143-1L, a second electrode layer line 145-1L, a third electrode layer line 147-1L, and a A variable resistance layer line 149-1L and a fourth electrode layer line 148-1L.

Furthermore, a plurality of first gaps GX1 may be formed between the plurality of conductive lines 110 and between the plurality of first stacked lines CPL1 by an anisotropic etching process. The plurality of first gaps GX1 may extend in the first direction and may be spaced apart from each other in the second direction. A part of the top surface of the substrate 101 may be exposed by the plurality of first gaps GX1.

16C, the mask pattern 410 may be removed to expose the top surface of the fourth electrode layer line 148-1L, and then a first insulating layer 162-1 may be formed to fill the plurality of first gaps GX1.

In some embodiments, the formation of the first insulating layer 162-1 may include forming an insulating material on the substrate 101 to fill the plurality of first gaps GX1 and planarizing the upper portion of the insulating material until the plurality of first gaps GX1 are exposed. One stack line up to the top surface of CPL1. The first insulating layer 162-1 may include, for example, a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer. The first insulating layer 162-1 may be made of one type of insulating layer or multiple insulating layers, but is not limited to this case.

Referring to FIG. 16D, the second conductive layer 120P may be formed on the exposed top surface of the fourth electrode layer line 148-1L and the exposed top surface of the first insulating layer 162-1.

The second stack structure CPS2 may be formed on the second conductive layer 120P. The second stack structure CPS2 may include a preliminary fifth electrode layer 141-2P, a preliminary second selection element layer 143-2P, a preliminary sixth electrode layer 145-2P, and a preliminary seventh electrode layer 141-2P sequentially formed on the second conductive layer 120P. The electrode layer 147-2P, the preliminary second variable resistance layer 149-2P, and the preliminary eighth electrode layer 148-2P.

The second conductive layer 120P, the preliminary fifth electrode layer 141-2P, the preliminary second selection element layer 143-2P, the preliminary sixth electrode layer 145-2P, and the preliminary seventh electrode layer 147- 2P, the preliminary second variable resistance layer 149-2P and the preliminary eighth electrode layer 148-2P can be combined with the second conductive line 120, the fifth electrode layer 141-2, and the second selection as described with reference to FIGS. 2 and 3 The element layer 143-2, the sixth electrode layer 145-2, the seventh electrode layer 147-2, the second variable resistance layer 149-2, and the eighth electrode layer 148-2 are formed of the same material.

The mask pattern 420 may be formed on the preliminary eighth electrode layer 148-2P. The mask pattern 420 may include a plurality of line patterns extending in the second direction and spaced apart from each other in the first direction.

16E, the second mask pattern 420 may be used as an etching mask pattern to sequentially and anisotropically etch the second stacked structure CPS2, the second conductive layer 120P, and the plurality of first stacked lines CPL1, The second stack structure CPS2 is separated into a plurality of second stack lines CPL2, the second conductive layer 120P is separated into a plurality of second conductive lines 120, and the plurality of first stack lines CPL1 are separated into a plurality of first stack patterns CPP1.

As a result, the plurality of second stack lines CPL2 may extend in the second direction and may be spaced apart from each other in the first direction, and the plurality of second conductive lines 120 may extend in the second direction and may be spaced from each other in the second direction. Spaced from each other in one direction. Furthermore, the plurality of first stack patterns CPP1 may be spaced apart from each other in the first direction and the second direction. The plurality of second conductive lines 120 may form a second conductive line layer 120L. The plurality of second stack lines CPL2 may each include a fifth electrode layer line 141-2L, a second selection element layer line 143-2L, a sixth electrode layer line 145-2L, a seventh electrode layer line 147-2L, and a Two variable resistance layer lines 149-2L and an eighth electrode layer line 148-2L. The plurality of first stack patterns CPP1 may include a first electrode layer 141-1, a first selection element layer 143-1, a second electrode layer 145-1, a third electrode layer 147-1, and a first variable resistance layer 149-1 and the fourth electrode layer 148-1.

Furthermore, an anisotropic etching process may be used to form between the plurality of second stack lines CPL2, between the plurality of second lines 120, and between the plurality of first stack patterns CPP1 Multiple second gaps GY1. The plurality of second gaps GY1 may extend in the second direction and may be spaced apart from each other in the first direction.

In some embodiments, an anisotropic etching process may be performed until the top surfaces of the plurality of first conductive lines 110 are exposed. Although not shown, a groove with a certain depth can be formed in the upper portion of the plurality of first conductive lines 110 by an anisotropic etching process.

In some embodiments, the anisotropic etching process may be performed until the top surface of the first electrode layer line 141-1L is exposed, and then the etching process may be performed under a certain etching condition. Under this etching condition, the first An electrode layer line 141-1L has etching selectivity with respect to the plurality of first conductive lines 110 to remove the first electrode layer line 141-1L exposed by the plurality of second gaps GY1 A part of each to expose the top surface of the plurality of first conductive lines 110.

Referring to FIG. 16F, the second mask pattern 420 may be removed to expose the top surface of the plurality of second stack lines CPL2. The third insulating layer 163 may be formed to fill the plurality of second gaps GY1.

In some embodiments, the formation of the third insulating layer 163 may include on the plurality of first conductive lines 110, on the sidewalls of the plurality of first stack patterns CPP1, and on the plurality of second stack lines An insulating material is formed on the sidewall of the CPL2 to fill the plurality of second gaps GY1 and planarize the upper portion of the insulating material until the top surface of the plurality of second stack lines CPL2 is exposed.

Referring to FIG. 16G, the third conductive layer 130P may be formed on the plurality of second stacked lines CPL2 and the third insulating layer 163.

The third mask pattern 430 may be formed on the third conductive layer 130P. The third mask pattern 430 may include a plurality of line patterns extending in the first direction and spaced apart from each other in the second direction.

16H, the third mask pattern 430 can be used as an etching mask to sequentially and anisotropically etch the third conductive layer 130P and the plurality of second stacked lines CPL2 to separate the third conductive layer 130P into The plurality of third conductive lines 130 separate the plurality of second stack lines CPL2 into a plurality of second stack patterns CPP2.

As a result, the plurality of third conductive lines 130 may extend in the first direction and may be spaced apart from each other in the second direction, and the plurality of second stack patterns CPP2 may be spaced apart from each other in the first direction and the second direction. open. The plurality of third conductive lines 130 may form a third conductive line layer 130L. The plurality of second stack patterns CPP2 may include a fifth electrode layer 141-2, a second selection element layer 143-2, a sixth electrode layer 145-2, a seventh electrode layer 147-2, and a second variable resistance layer 149-2 and the eighth electrode layer 148-2.

Furthermore, a plurality of third gaps GX2 may be formed between the plurality of third conductive lines 130 and between the plurality of second stack patterns CPP2 by an anisotropic etching process. The plurality of third gaps GX2 may extend in the first direction and may be spaced apart from each other in the second direction.

In some embodiments, an anisotropic etching process may be performed until the top surfaces of the second conductive lines 120 are exposed. Although not shown, a groove with a certain depth can be formed in the upper portion of the plurality of second conductive lines 120 by an anisotropic etching process.

In some embodiments, the anisotropic etching process may be performed until the top surface of the fifth electrode layer line 141-2L is exposed, and then the etching process may be performed under a certain etching condition. Under this etching condition, the first The five-electrode layer line 141-2L is relative to the The plurality of second conductive lines 120 have etching selectivity to remove a part of each of the fifth electrode layer lines 141-2L exposed by the plurality of third gaps GX2 to expose the plurality of second conductive lines Top surface of 120.

Referring to FIG. 16I, the third mask pattern 430 may be removed to expose the top surface of the plurality of second stack patterns CPP2. The second insulating layer 162-2 may be formed to fill the plurality of third gaps GX2.

In some embodiments, the formation of the second insulating layer 162-2 may include forming an insulating material on the plurality of third conductive lines 130 and on the sidewalls of the plurality of second stack patterns CPP2 to fill the plurality of A third gap GX2 and an upper portion of the insulating material are planarized to expose the top surface of the plurality of third conductive lines 130.

As a result, the memory device 100 can be realized by executing the process described above.

The plurality of first stack patterns CPP1 may be a plurality of first memory cells 140-1, and the plurality of second stack patterns CPP2 may be a plurality of second memory cells 140-2. In addition, the plurality of first memory cells 140-1 may form a first memory cell layer MCL1, and the plurality of second memory cells 140-2 may form a second memory cell layer MCL2.

According to the method of manufacturing the memory device 100, the first patterning process (patterning process) using the first mask pattern 410 extending in the first direction, and the second patterning process using the second mask extending in the second direction can be performed sequentially. The second patterning process of the mask pattern 420 and the third patterning process of using the third mask pattern 430 extending in the first direction. As a result, the plurality of first conductive wires 110 extending in the first direction, the plurality of second conductive wires 120 extending in the second direction, and the plurality of second conductive wires extending in the first direction can be formed. Three conductive wires 130, in the plurality of first conductive wires The plurality of first memory cells 140-1 at the respective intersection points of the electric wire 110 and the plurality of second conductive lines 120 and the plurality of second conductive lines 120 and the plurality of third conductive lines 120 The plurality of second memory cells 140-2 at the respective intersection points of the line 130.

Therefore, because only three patterning processes are used to form the plurality of first memory cells 140-1 and the plurality of second memory cells 140-2, the first variable resistance layer 149-1 can be prevented And the second variable resistance layer 149-2 and/or the first selection element layer 143-1 and the second selection element layer 143-2 are attributable to the degradation or damage due to exposure to the etching atmosphere during the patterning process. In addition, the manufacturing cost of the memory device 100 can be reduced.

Figure 17 is a block diagram illustrating a memory device according to certain embodiments.

Referring to FIG. 17, the memory device 800 may include a memory cell array 810, a decoder 820, a read/write circuit 830, an input/output buffer 840, and a controller 850. The memory cell array 810 may include at least one of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 200 described with reference to FIGS. 1-15.

A plurality of memory cells in the memory cell array 810 can be connected to the decoder 820 via a plurality of word lines WL, and can be connected to the read/write circuit 830 via a plurality of bit lines BL. The decoder 820 can receive the address ADD from the outside of the memory device 800, and can decode the column address and the row address under the control of the controller 850 which operates in response to the control signal CTRL to be in the memory cell array 810 access.

The read/write circuit 830 can receive data from the input/output buffer 840 and multiple data lines DL, and can write the received data into the selected memory of the memory cell array 810 under the control of the controller 850 In the body unit. Read/write circuit 830 can read data from the selected memory cell of the memory cell array 810 under the control of the controller 850, and can send the read data to the input/output buffer 840.

Figure 18 is a block diagram illustrating an electronic system according to some embodiments.

18, the electronic system 1100 may include a memory system (memory system) 1110, a processor (processor) 1120, a random access memory (random access memory; RAM) 1130, input/output (input/output; I/O ) Unit 1140, power supply unit 1150. The memory system 1110 may include a memory device 1112 and a memory controller 1114. Although not shown, the electronic system 1100 may further include a port for communicating with a video card, a sound card, a memory card, a USB device, or other electronic devices. The electronic system 1100 can be a personal computer or a mobile electronic device, such as a notebook computer, a mobile phone, a personal digital assistant (PDA) or a camera.

The processor 1120 may perform specific calculations or tasks. The processor 1120 may be a microprocessor or a central processing unit (CPU). The processor 1120 can communicate with the random access memory 1130, the input/output unit 1140, and the memory system 1110 via a bus 1160 (such as an address bus, a control bus, or a data bus). Here, the memory system 1110 or the random access memory 1130 may include at least one of the memory devices 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, and 200 described with reference to FIGS. 1 to 15 .

In some embodiments, the processor 1120 may be connected to an expansion bus, such as a peripheral component interconnection (PCI) bus.

The random access memory 1130 can store data necessary for operating the electronic system 1100. The random access memory 1130 may include DRAM, mobile DRAM, SRAM, ReRAM, FRAM, MRAM, or PRAM.

The input/output unit 1140 may include an input unit such as a keypad, keyboard, or mouse, and an output unit such as a display or a printer. The power supply unit 1150 can supply the operating voltage necessary for operating the electronic system 1100.

The subject matter disclosed above should be regarded as illustrative rather than restrictive, and the appended patent scope is intended to cover all such modifications, enhancements and other embodiments within the true spirit and scope of the concept of the present invention. Therefore, to the greatest extent permitted by law, the scope should be determined by the broadest permitted interpretation of the scope of the following patents and their equivalents, and should not be limited or restricted by the foregoing detailed description.

100‧‧‧Memory device

BL1, BL2, BL3, BL4‧‧‧Common bit lines

MC1‧‧‧First memory unit

MC2‧‧‧Second memory unit

ME‧‧‧Variable resistance layer

SW‧‧‧Select component

WL11, WL12‧‧‧Lower character line

WL21, WL22‧‧‧Upper character line

X, Y, Z‧‧‧direction

Claims (20)

A memory device includes: a substrate; a plurality of first conductive lines, on the substrate, the plurality of first conductive lines extend in a first direction parallel to the top surface of the substrate and are in contact with the The first direction is spaced apart from each other in a second direction crossing; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and in the Spaced apart from each other in the first direction; a plurality of third conductive lines above the plurality of second conductive lines, the plurality of third conductive lines extending in the first direction and in the second direction Are spaced apart from each other; a plurality of first memory cells, at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines, each of the plurality of first memory cells One includes a first selection element layer and a first variable resistance layer; and a plurality of second memory cells, at respective intersections of the plurality of second conductive lines and the plurality of third conductive lines, Each of the plurality of second memory cells includes a second selection element layer and a second variable resistance layer, wherein the first selection element layer is perpendicular to the first direction and the second direction The first height in the third direction is different from the second height of the second selection element layer in the third direction, and wherein the first variable resistance layer and the second variable resistance layer are made of the same And the first selection element layer and the second selection element layer are made of the same material. The memory device described in item 1 of the scope of patent application, wherein the first The magnitude difference between the threshold voltage of a selection element layer and the threshold voltage of the second selection element layer is less than 10% of the threshold voltage of the first selection element layer. The memory device according to claim 1, wherein the magnitude of the threshold voltage of the first selection element layer ranges from 90% to 110% of the magnitude of the threshold voltage of the second selection element layer . The memory device according to claim 1, wherein the first height of the first selection element layer is greater than the second height of the second selection element layer. The memory device according to claim 4, wherein the memory device is configured to apply a word line selection voltage to one of the plurality of first conductive lines or to the plurality of One of the third conductive lines, and a bit line selection voltage smaller than the word line selection voltage is applied to one of the plurality of second conductive lines. The memory device according to claim 4, wherein the range of the second height of the second selection element layer is 50% to 90% of the first height of the first selection element layer . The memory device according to claim 1, wherein the first height of the first selection element layer is smaller than the second height of the second selection element layer. The memory device according to claim 7, wherein the range of the first height of the first selection element layer is 50% to 90% of the second height of the second selection element layer . The memory device according to claim 7, wherein the memory device is configured to apply a character line selection voltage to the plurality of first conductive lines One of or applied to one of the plurality of third conductive lines, and a bit line selection voltage greater than the word line selection voltage is applied to one of the plurality of second conductive lines . The memory device according to claim 1, wherein each of the first selection element layer and the second selection element layer has a bidirectional critical switching property. The memory device according to claim 1, wherein each of the plurality of first memory cells is further included in the first variable resistance layer and the plurality of first conductive lines The first heating electrode layer between the corresponding ones, and each of the plurality of second memory cells is further included in the corresponding second variable resistance layer and the plurality of third conductive lines Between the second heating electrode layer. The memory device according to claim 1, wherein each of the plurality of first memory cells is further included in the first variable resistance layer and the plurality of second conductive lines The first heating electrode layer between the corresponding ones, and each of the plurality of second memory cells is further included in the corresponding second variable resistance layer and the plurality of second conductive lines Between the second heating electrode layer. A memory device includes: a substrate; a plurality of first conductive lines, on the substrate, the plurality of first conductive lines extend in a first direction parallel to the top surface of the substrate and are in contact with the The first direction is spaced apart from each other in a second direction crossing; a plurality of second conductive lines above the plurality of first conductive lines, the plurality of second conductive lines extending in the second direction and in the Spaced apart from each other in the first direction; a plurality of third conductive lines, above the plurality of second conductive lines, the plurality of first Three conductive wires extend in the first direction and are spaced apart from each other in the second direction; a plurality of first memory cells are located between the plurality of first conductive wires and the plurality of second conductive wires At respective intersections, each of the plurality of first memory cells includes first selection element layers sequentially stacked in a third direction perpendicular to the first direction and the second direction, and A first variable resistance layer; and a plurality of second memory cells, at respective intersections of the plurality of second conductive lines and the plurality of third conductive lines, the plurality of second memory cells Each of them includes a second selection element layer and a second variable resistance layer that are sequentially stacked in the third direction, wherein the thickness of the first selection element layer in the third direction is greater than that of the third direction. The thickness of the second selection element layer in the third direction, and wherein the first variable resistance layer and the second variable resistance layer are made of the same material, and the first selection element layer and the The second optional element layer is made of the same material. The memory device according to claim 13, wherein the first selection element layer and the second selection element layer, and the first variable resistance layer and the second variable resistance layer Each has at least one of the chalcogen elements. The memory device according to claim 13, wherein the thickness of the second selection element layer in the third direction ranges from 50% of the thickness of the first selection element layer in the third direction. % To 90%. A memory device comprising: a substrate; a first character line layer arranged on the substrate; a common bit line layer arranged on the first character line layer; The second word line layer is arranged on the common bit line such that the common bit line layer is vertically located between the first word line layer and the second word line layer; first memory The bulk cell layer includes a vertically stacked first variable resistance layer and a first bidirectional critical switching layer. The first memory cell layer is vertically arranged on the first word line layer and the common location Between the element line layers; and the second memory cell layer, including a second variable resistance layer and a second bidirectional critical switching layer stacked vertically, the second memory cell layer is arranged in the vertical direction on the first Between the two-character line layer and the common bit line layer, wherein the first variable resistance layer and the second variable resistance layer are made of the same material, and the first bidirectional critical switching layer It is made of the same material as the second bidirectional critical switching layer, and the first thickness of the first bidirectional critical switching layer in the vertical direction is different from the second bidirectional critical switching layer in the vertical direction. Two thickness. The memory device according to claim 16, wherein the first thickness of the first bidirectional critical switching layer ranges from 50% to the second thickness of the second bidirectional critical switching layer 90%, or wherein the range of the second thickness of the second bidirectional critical switching layer is 50% to 90% of the first thickness of the first bidirectional critical switching layer. The memory device according to claim 16, wherein the first variable resistance layer and the second variable resistance layer, the first bidirectional critical switching layer and the second bidirectional critical switching layer Each of them contains at least one of the chalcogen elements. The memory device described in claim 16 further includes sidewalls covering the first bidirectional critical switching layer and the second bidirectional critical switching layer and/ Or spacers on the sidewalls of the first variable resistance layer and the second variable resistance layer. The memory device according to claim 19, wherein each of the first variable resistance layer and the second variable resistance layer has an L shape or an I shape.

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