TWI287233B - Memory having a precharge circuit and method therefor - Google Patents
Memory having a precharge circuit and method therefor Download PDFInfo
- Publication number
- TWI287233B TWI287233B TW092117670A TW92117670A TWI287233B TW I287233 B TWI287233 B TW I287233B TW 092117670 A TW092117670 A TW 092117670A TW 92117670 A TW92117670 A TW 92117670A TW I287233 B TWI287233 B TW I287233B
- Authority
- TW
- Taiwan
- Prior art keywords
- write
- memory
- current
- coupled
- transistor
- Prior art date
Links
- 230000015654 memory Effects 0.000 title claims description 139
- 238000000034 method Methods 0.000 title claims description 27
- 238000003860 storage Methods 0.000 claims description 4
- 238000013459 approach Methods 0.000 claims description 2
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- 238000001459 lithography Methods 0.000 description 2
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2263—Write conditionally, e.g. only if new data and old data differ
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/185,488 US6711052B2 (en) | 2002-06-28 | 2002-06-28 | Memory having a precharge circuit and method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200414216A TW200414216A (en) | 2004-08-01 |
| TWI287233B true TWI287233B (en) | 2007-09-21 |
Family
ID=29779641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092117670A TWI287233B (en) | 2002-06-28 | 2003-06-27 | Memory having a precharge circuit and method therefor |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6711052B2 (enExample) |
| EP (1) | EP1581951A2 (enExample) |
| JP (1) | JP4388889B2 (enExample) |
| AU (1) | AU2003232038A1 (enExample) |
| TW (1) | TWI287233B (enExample) |
| WO (1) | WO2004003923A2 (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002230965A (ja) * | 2001-01-24 | 2002-08-16 | Internatl Business Mach Corp <Ibm> | 不揮発性メモリ装置 |
| CA2455766C (en) * | 2001-07-31 | 2011-02-08 | Tyco Healthcare Group Lp | Bioabsorbable adhesive compounds and compositions |
| US7020008B2 (en) * | 2001-12-26 | 2006-03-28 | Renesas Technology Corp. | Thin film magnetic memory device writing data with bidirectional current |
| US6873542B2 (en) * | 2002-10-03 | 2005-03-29 | International Business Machines Corporation | Antiferromagnetically coupled bi-layer sensor for magnetic random access memory |
| JP4283011B2 (ja) * | 2003-03-13 | 2009-06-24 | Ｔｄｋ株式会社 | 磁気メモリデバイスおよびその読出方法 |
| US7286378B2 (en) * | 2003-11-04 | 2007-10-23 | Micron Technology, Inc. | Serial transistor-cell array architecture |
| US7502248B2 (en) * | 2004-05-21 | 2009-03-10 | Samsung Electronics Co., Ltd. | Multi-bit magnetic random access memory device |
| US7102916B2 (en) * | 2004-06-30 | 2006-09-05 | International Business Machines Corporation | Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption |
| DE102005001667B4 (de) * | 2005-01-13 | 2011-04-21 | Qimonda Ag | Nichtflüchtige Speicherzelle zum Speichern eines Datums in einer integrierten Schaltung |
| US7269050B2 (en) * | 2005-06-07 | 2007-09-11 | Spansion Llc | Method of programming a memory device |
| US7206223B1 (en) | 2005-12-07 | 2007-04-17 | Freescale Semiconductor, Inc. | MRAM memory with residual write field reset |
| US7280388B2 (en) * | 2005-12-07 | 2007-10-09 | Nahas Joseph J | MRAM with a write driver and method therefor |
| EP1863034B1 (en) * | 2006-05-04 | 2011-01-05 | Hitachi, Ltd. | Magnetic memory device |
| KR100855965B1 (ko) * | 2007-01-04 | 2008-09-02 | 삼성전자주식회사 | 서브 셀 어레이를 구비하는 양방향성 ｒｒａｍ 및 이를이용하는 데이터 기입 방법 |
| US7880209B2 (en) * | 2008-10-09 | 2011-02-01 | Seagate Technology Llc | MRAM cells including coupled free ferromagnetic layers for stabilization |
| US8102720B2 (en) * | 2009-02-02 | 2012-01-24 | Qualcomm Incorporated | System and method of pulse generation |
| US8279659B2 (en) * | 2009-11-12 | 2012-10-02 | Qualcomm Incorporated | System and method of operating a memory device |
| US9183910B2 (en) | 2012-05-31 | 2015-11-10 | Samsung Electronics Co., Ltd. | Semiconductor memory devices for alternately selecting bit lines |
| WO2014058994A2 (en) * | 2012-10-11 | 2014-04-17 | Everspin Technologies, Inc. | Memory device with timing overlap mode |
| CN114974340A (zh) * | 2021-02-27 | 2022-08-30 | 华为技术有限公司 | 一种存储装置 |
| US12249365B2 (en) * | 2023-03-06 | 2025-03-11 | Windbond Electronics Corp. | Memory device capable of performing in-memory computing |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS568435B2 (enExample) * | 1972-09-19 | 1981-02-24 | ||
| US4713797A (en) * | 1985-11-25 | 1987-12-15 | Motorola Inc. | Current mirror sense amplifier for a non-volatile memory |
| US5777923A (en) * | 1996-06-17 | 1998-07-07 | Aplus Integrated Circuits, Inc. | Flash memory read/write controller |
| US6256224B1 (en) * | 2000-05-03 | 2001-07-03 | Hewlett-Packard Co | Write circuit for large MRAM arrays |
| US6236611B1 (en) * | 1999-12-20 | 2001-05-22 | Motorola, Inc. | Peak program current reduction apparatus and method |
| JP4726290B2 (ja) * | 2000-10-17 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
| JP4667594B2 (ja) * | 2000-12-25 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
-
2002
- 2002-06-28 US US10/185,488 patent/US6711052B2/en not_active Expired - Lifetime
-
2003
- 2003-05-01 WO PCT/US2003/013750 patent/WO2004003923A2/en not_active Ceased
- 2003-05-01 AU AU2003232038A patent/AU2003232038A1/en not_active Abandoned
- 2003-05-01 JP JP2004517531A patent/JP4388889B2/ja not_active Expired - Lifetime
- 2003-05-01 EP EP03761896A patent/EP1581951A2/en not_active Withdrawn
- 2003-06-27 TW TW092117670A patent/TWI287233B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US6711052B2 (en) | 2004-03-23 |
| EP1581951A2 (en) | 2005-10-05 |
| US20040001351A1 (en) | 2004-01-01 |
| TW200414216A (en) | 2004-08-01 |
| JP2006503387A (ja) | 2006-01-26 |
| JP4388889B2 (ja) | 2009-12-24 |
| WO2004003923A3 (en) | 2005-08-11 |
| WO2004003923A2 (en) | 2004-01-08 |
| AU2003232038A1 (en) | 2004-01-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |