TWI285899B - Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays - Google Patents
Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays Download PDFInfo
- Publication number
- TWI285899B TWI285899B TW092133863A TW92133863A TWI285899B TW I285899 B TWI285899 B TW I285899B TW 092133863 A TW092133863 A TW 092133863A TW 92133863 A TW92133863 A TW 92133863A TW I285899 B TWI285899 B TW I285899B
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- row
- rows
- coupled
- voltage
- Prior art date
Links
- 238000003491 array Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000001939 inductive effect Effects 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000003321 amplification Effects 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 239000002699 waste material Substances 0.000 claims 1
- 238000011067 equilibration Methods 0.000 abstract 4
- 230000002950 deficient Effects 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 241000237536 Mytilus edulis Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000020638 mussel Nutrition 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/309,572 US6934208B2 (en) | 2002-12-03 | 2002-12-03 | Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200428403A TW200428403A (en) | 2004-12-16 |
| TWI285899B true TWI285899B (en) | 2007-08-21 |
Family
ID=32392903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092133863A TWI285899B (en) | 2002-12-03 | 2003-12-02 | Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6934208B2 (https=) |
| EP (1) | EP1576347A2 (https=) |
| JP (1) | JP2006518523A (https=) |
| KR (1) | KR100788182B1 (https=) |
| CN (1) | CN101405809A (https=) |
| AU (1) | AU2003298793A1 (https=) |
| TW (1) | TWI285899B (https=) |
| WO (1) | WO2004051662A2 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6934208B2 (en) | 2002-12-03 | 2005-08-23 | Boise Technology, Inc. | Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays |
| KR100587080B1 (ko) * | 2004-05-17 | 2006-06-08 | 주식회사 하이닉스반도체 | 메모리 장치의 감지 증폭기를 제어하여 컬럼성 페일을검출하는 방법 및 그 장치 |
| US7698607B2 (en) * | 2004-06-15 | 2010-04-13 | Intel Corporation | Repairing microdisplay frame buffers |
| US10020038B1 (en) | 2017-04-14 | 2018-07-10 | Micron Technology, Inc. | Apparatuses and methods for controlling wordlines and sense amplifiers |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5235550A (en) | 1991-05-16 | 1993-08-10 | Micron Technology, Inc. | Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts |
| US5499211A (en) * | 1995-03-13 | 1996-03-12 | International Business Machines Corporation | Bit-line precharge current limiter for CMOS dynamic memories |
| JP3782227B2 (ja) * | 1997-03-11 | 2006-06-07 | 株式会社東芝 | 半導体記憶装置 |
| US5896334A (en) | 1997-08-14 | 1999-04-20 | Micron Technology, Inc. | Circuit and method for memory device with defect current isolation |
| JP3505373B2 (ja) * | 1997-11-14 | 2004-03-08 | 株式会社東芝 | 半導体記憶装置 |
| JP2000077628A (ja) * | 1998-06-19 | 2000-03-14 | Toshiba Corp | 半導体記憶装置 |
| US6078538A (en) | 1998-08-20 | 2000-06-20 | Micron Technology, Inc. | Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts |
| JP2001052476A (ja) | 1999-08-05 | 2001-02-23 | Mitsubishi Electric Corp | 半導体装置 |
| US6356492B1 (en) | 2000-08-16 | 2002-03-12 | Micron Technology, Inc. | Method and apparatus for reducing current drain caused by row to column shorts in a memory device |
| US6333882B1 (en) | 2000-08-25 | 2001-12-25 | Micron Technology, Inc. | Equilibration/pre-charge circuit for a memory device |
| US6678199B1 (en) | 2002-06-19 | 2004-01-13 | Micron Technology, Inc. | Memory device with sense amp equilibration circuit |
| US6934208B2 (en) | 2002-12-03 | 2005-08-23 | Boise Technology, Inc. | Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays |
-
2002
- 2002-12-03 US US10/309,572 patent/US6934208B2/en not_active Expired - Lifetime
-
2003
- 2003-12-01 AU AU2003298793A patent/AU2003298793A1/en not_active Abandoned
- 2003-12-01 EP EP03796551A patent/EP1576347A2/en not_active Withdrawn
- 2003-12-01 WO PCT/US2003/038226 patent/WO2004051662A2/en not_active Ceased
- 2003-12-01 CN CNA200380109481XA patent/CN101405809A/zh active Pending
- 2003-12-01 JP JP2004557464A patent/JP2006518523A/ja active Pending
- 2003-12-01 KR KR1020057010141A patent/KR100788182B1/ko not_active Expired - Fee Related
- 2003-12-02 TW TW092133863A patent/TWI285899B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| AU2003298793A1 (en) | 2004-06-23 |
| US20040105333A1 (en) | 2004-06-03 |
| TW200428403A (en) | 2004-12-16 |
| KR20050084162A (ko) | 2005-08-26 |
| EP1576347A2 (en) | 2005-09-21 |
| KR100788182B1 (ko) | 2008-01-02 |
| WO2004051662A2 (en) | 2004-06-17 |
| CN101405809A (zh) | 2009-04-08 |
| US6934208B2 (en) | 2005-08-23 |
| JP2006518523A (ja) | 2006-08-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |