TWI280624B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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TWI280624B
TWI280624B TW093103184A TW93103184A TWI280624B TW I280624 B TWI280624 B TW I280624B TW 093103184 A TW093103184 A TW 093103184A TW 93103184 A TW93103184 A TW 93103184A TW I280624 B TWI280624 B TW I280624B
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insulating film
gate insulating
film
semiconductor device
gate
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TW093103184A
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TW200425350A (en
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Takafumi Morikawa
Akihide Kashiwagi
Takayoshi Kato
Tomoyuki Hirano
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Description

1280624 玖、發明說明： 發明所參考之文獻 [專利文獻1] 曰本專利特開2001-291865 【發明所屬之技術領域】 本發明係關於一種半導體裝置之製造方法，具體言之， 係關於一種朝細微化發展之MOS型半導體裝置之閘極絕緣 膜之製造方法。 【先前技術】 隨著半導體裝置之高集成化和高性能化之要求，在MOS 型矽半導體裝置中，現正朝向遵守莫爾定標定律之裝置構 造之細微化推進。近年來，在CMOS構成之半導體裝置中， 為了突破由該種細微化對於裝置特性提高之限制，在P型 MOS電晶體（以下稱為PMOS)中使用含有P型雜質之閘極， 在N型MOS電晶體（以下稱為NMOS)中使用包含N型雜質之 閘極，即採用所謂的雙閘極構造。 但是，習知在具有雙閘極構造之半導體裝置中，在PMOS 之閘極中包含之作為P型雜質之硼（B)會隨著裝置構造之細 微化而穿過薄膜化之閘極絕緣膜向基板擴散，因而對於載 子之遷移率低落或者固定電荷之增大等裝置特性產生不良 影響。 此處，在雙閘極之製程中，為了抑制硼之穿過，廣泛進 行有對閘極絕緣膜之氮化，且為了不使裝置特性劣化，亦 進行有氮濃度之調整等措施（例如參照上述專利文獻1)。 90136.doc 1280624 發明所欲解決之問題 但是，在閘極絕緣膜中導入氮，則有所謂NBTI(Negativ卜 Bias-Temperature-Instability)現象產生之新問題。NBTH|、閘 極絕緣膜中之氮藉由熱擴散而到達基板介面形成電洞之陷 阱，造成正固定電荷或者載子之散亂因子，使PM〇s中之載 子之遷移率或者臨限值徐徐變動之現象，亦成為半導體裝 置之壽命顯著低落之原因。 【發明内容】 此處，本發明之目的係提供一種半導體裝置之製造方 法，俾使能夠在上述之閘極絕緣財導人有氮之刪電晶 體中抑制NBTI現象之發生。 為了實現該種目的之本發明之半導體裳置之製造方法， 其特徵在於以如下之順序進行之。首先，在第—步驟，在 基板上形成包含氮之氧化膜作為閘極絕緣膜。之後，在第 二步驟’在包含氧之環境氣體中對閘極絕緣膜進行退火處 理。另外，在第二步驟和相繼進行之第三步驟中，在不含 氧之惰性環境氣體中對前㈣極絕緣膜進行敎處理。: 後，在第四步驟，在滋古Λ、A卞，& “有兩-退火處理之閘極絕緣膜上形 成電極胺。 卜 褙田卸由包含氮之氧化膜構成之 極絕緣膜在包含氧之環境氣髀 兄轧把中進仃退火處理，藉由奇 之導入使間極絕緣膜中生成 褙田氮 打…m 成<〇H基寺電洞之陷阱從該 極絕緣版中排出。同梓，丄 ' 门時，由於基板和開極絕緣膜之介面: 造尤散亂復原，故介面能階差 降低另外，藉由將該閘入 90136.doc 1280624 絕緣膜在不含氧之惰性環境氣體中 於閘極絕緣膜中之結合不穩定 以火處理’使存在 邱。另休〃 # ^出到閘極絕緣膜之外 4。另外，與此同時，謀灰蘀 Γ 缘膜之囊π#、, ，奴疋、、、°合之氮與構成閘極絕 =:=結合狀態之穩定化。藉此，使造成電洞之 见（正固定電荷）從閱極每緣膜中排除。 L貫施万式】 以下’基於圖1、圖2之截面庠 丰導歸费番、“、哉面序圖來評細說明本發明之 雜4月將本發明應用於具有 又閘極構k之CMOS構成之半導體裳置之製造中之實施方 式0 首先，如圖1⑷所示，在由單晶珍構成之基板工上形成場 氧化膜（元件分隔區域）3,將基板】之表面側分隔為讀卿 域a和PMOS區域b。接著’在基板以露出表面形成犧牲氧 化膜5’藉以該犧牲氧化膜5進行離子体植，藉此在刪$ 區域a形成p-井7, pMos區域形成卜井卜然後，利用離 子佈植將用於進行臨限值控制之雜質分別導入舰⑽區心 和ΡΜΌ S區域b。 將以上之一連串步驟應用於通常之c M 〇 s製程之後，如圖 1(b)所示，剝離基板丨表面之犧牲氧化膜⑺，露出基板u 面。 之後，如圖1(c)、圖1(d)所示，在基板1上形成由包含氮 之氧化膜（所謂之氮氧化矽膜）構成之閘極絕緣膜u。該種閘 極絕緣膜11之形成係藉由例如以下之①〜③中之任一種方法 來進行。 90136.doc 1280624 ①之万法，首先，如圖w — )所不’形成不包含氮之氧化膜 (氧化矽膜）1〇。之後，葬山v、 、^ 進行電漿氮化處理在氧化膜1 〇 中導入氮，而如圖1 (d)所示上、、一 7成由氮氧化矽構成之閘極絕緣 膜11。 《万法#先，如圖Hc)所示，形成不含氮之氧化膜（氧 化石夕膜）。之後，藉由左一备&， 精録減氮⑽）氣體或者一氧化二氮 (n2〇)氣體之環境氣體中進行退火處理，而如圖叫所示形 成由乳化膜氮化之氮氧切構成之閘極絕、緣膜u。該種退 火處理可以是爐内退火和RTA(Rapid_Thermai_A_ 快速加熱退火）中之任一種處理。 方法係藉由在NO氣體或者ν2〇氣體之環境氣體中進 行爐内氧化（Oxidation)，如圖丨⑷所示，使基板丨表面氮化 減而成長氮氧切，將其作㈣極絕緣膜u。 藉由以上<任何-種万法，在基板1之表面形成由氣氧化 碎構成之閘極絕緣膜11後，進行本發明特徵之第！退火處理 和弟2退火處理之兩次退火處理。又，第丨退火處理和第城 火處理進行之先後不拘。 作為该種設定條件之一例 首先，在包含氮衷境氣體中進行第以火處理。該退火 處理係利用例如RTA或者爐内退火來進行。但是，在該退 火處理中，係在閘極絕緣膜u和基板丨之介面中進行氧化。 為此’本第i退火處理係適當設定處理環境氣體中之氧之壓 力條件和溫度條件來進行，以抑•該氧化導致之閑極絕 緣膜11之厚膜化和閘極絕賴llt之氮之偏析。 在進行RTA之情況下，在減 90136.doc 1280624
TllvxJ2?a^ ^ ^9〇〇〇c '仃30秒左右之處理。藉此，將氧化 絕緣膜11之膜厚增加抑制敎5⑽之下。 .、第火處理亦可以在將氮或者惰性氣體等不會與 S i反應《^性乳體與氧氣混合之混合氣體之環境氣體中進 行二況下，處理環境氣體可以是減壓狀態，亦可以是 吊[狀恐：而根據氧氣和惰性氣體之分壓和溫度條件，抑 制由上述氧料致之祕絕緣mi之厚膜化和閘極絕緣膜 11中之氮之偏、析。 "、方面第2退火處理係在不含氧之惰性環境氣體中進 行。該退2處理係利用例如RTA或者M内退火來進行。此 處―不《氧·^惰性氣體係指不會引起由氧化導致之閑極絕 ’《1=膜厚增加之惰性環境氣體。因此，處理環境氣體 係指氮氣或者氬氣等之惰性氣體之減壓或常壓環境氣體， 更進V係扣真空J幕境氣體。而且，只要在不引起閘極絕 緣膜U之膜厚增加之内，亦可以包含微量之氧，例如， 亦可以包含在使用氣體中於製造上混人作為雜質之1〇 ppb(體積ppb)以下之微量氧。 另外，為了維持在此形成之M〇s電晶體之特性，該第2 退火處理係在閘極絕緣膜11中不會使氮大幅進行再分佈之 溫度範圍内進行。為此，第2退火處理係設在9〇〇。〇〜i2〇〇t 之範圍内進行。 作為該種第2退火處理之一例，在進行例如RTA之情況 下’係在減壓之氮環境氣體中，以1000X：進行20秒左右之 90136.doc -10- 1280624 處理。 又’以上說明之第1退火處理和第2退火處理，可以在同 -處理：中連續進行，亦可以在個別裝置中分別進行。此 外，f弟1退火處理和第2退火處理之間，可以將基板旧放 於大氣中，亦可以加入洗淨等其他工序。 然後，在以上之兩次退火處理結束後，如圖2⑷所示，在 基板1上全面形成例如由多晶矽構成之電極膜13。 以下，如圖2(b)所示，將電極膜13加工成希望之圖案而形 成閘極14。此時，將利用微影工序形成之抗蝕圖案（省略圖 不）作為掩模將電極膜13進行圖案蝕刻，在蝕刻結束後除去 抗I虫圖案。 以下’如圖2(c)所示’將閘極14和此處省略圖示之抗姓圖 案作為掩模進行離子佈植，藉此在NMOS區域a和PMOS區域 b導入用以形成LDD擴散層iSa、1%之雜質。此時，在NMOS 區域a導入作為N型雜質之磷（p)，在pm〇s區域b導入作為P 型雜質之硼（B)。之後，在各個閘極14之側壁上，形成由例 如氧化矽構成之側壁絕緣膜17。又，利用形成該侧壁絕緣 膜17時之氧化矽膜之回蝕工序，除去基板1上之閘極絕緣膜 11、 以下，將閘極14、侧壁絕緣膜17和此處省略圖示之抗蝕 圖案作為掩模進行離子佈植，藉此在NMOS區域a和PMOS 區域b導入用以形成源極/汲極擴散層19a、19b之雜質。此 時，例如，在NMOS區域a導入作為N型雜質之磷（P)，在PMOS 區域b導入作為P型雜質之硼（B)。 90136.doc -11· 1280624 另外，藉由如上之兩次離子佈植，在NMOS區域a之閘極 14a中導入作為N型雜質之磷（p)，在PMOS區域b之閘極14b 中導入作為P型雜質之硼（B)。 藉由以上，在基板1之表面側，形成設有NMOS 21a和 PMOS 21b而成之半導體裝置23。該半導體裝置23具有對 NMOS21a之閘極14a導入N型雜質、對PMOS21b之閘極14b 導入P型雜質之雙閘極構造。 根據以上祝明之製造方法，如使用圖1 (d)所做之說明，在 形成由氮氧化矽構成之閘極絕緣膜11後，藉由在包含氧之 環境氣體中對該閘極絕緣膜1 1實施退火處理（第1退火處 理）’可藉由氮之導入而將閘極絕緣膜11中生成之OH基等電 洞之陷阱從該閘極絕緣膜11中排出。同時，由於基板1和閘 極絕緣膜11之介面之結晶狀態之散亂復原，故介面能階差 降低。 另外，藉由在不含氧之惰性環境氣體中對該閘極絕緣膜 11實施退火處理（第2退火處理），可將存在於閘極絕緣膜1 Γ 中之結合不穩定之氮排出到閘極絕緣膜丨丨之外部。另外， 與此同時，能夠實現閘極絕緣膜丨丨中結合不穩定之氮與氧 化物（氧化石夕）之結合狀態之穩定。藉此，可將造成電洞陷味 之不穩定之氮（正固定電荷）從閘極絕緣膜中排除。 而且’藉由如以上之兩次退火處理，從閘極絕緣膜丨i中 除去電洞之陷阱因子，使其與基板丨之介面之結晶狀態之散 I復原，藉此能夠抑制NBTI之發生。 特別是，根據本實施形式中說明之本發明之製造方法， 90136.doc -12 - 1280624 無需改變製造工序或元件構造，亦即僅在製造工序中增加 第1退火處理和第2退火處理，即可改善上述之NBTI。 另外，藉此，能夠使半導體裝置具有高可靠性（增長壽 命）。即，由於能夠減小因NBTI導致之MOS電晶體之特性變 動，所以能夠延長因特性變動導致裝置無法運作之壽命期 限，且能夠穩定運作之半導體裝置。 此外，能夠進一步使半導體裝置高性能化。即，如果MOS 電晶體之特性變動大，就需要加大機器之設計俾使得變動 後亦可運作。如果加大機器之設計，則裝置之性能劣化。 為此，藉由使用特性變動小之MOS電晶體，能夠設計和製 造高性能（例如高速）裝置。 在以上之實施形式中，說明了將本發明應用於CMOS構成 之半導體裝置之製造方法中之情況。但是，本發明能夠廣 泛應用於使用包含氮之氧化膜作為閘極絕緣膜之半導體裝 置中，且同樣能夠得到防止NBTI發生之效果。 依照如以上說明之本發明之半導體裝置之製造方法，對 於由包含氮之氧化膜構成之閘極絕緣膜，在包含氧之環境 氣體中和不含氧之惰性環境氣體中進行兩次退火處理，藉 此無需改變製造工序或元件構造，即可從閘極絕緣膜中除 去電洞之陷阱，使其與基板之介面中之結晶狀態之散亂復 原而抑制NBTI之發生。 【圖式簡單說明】 圖1(a)〜(d)係用於說明本發明之製造方法之截面工序圖 (其 1) 〇 90136.doc -13- 1280624 圖2(a)〜(c)係用於說明本發明之製造方法之截面工序圖 (其 2)。 【圖式代表符號說明】
1 基板 11 閘極絕緣膜 13 電極膜 90136.doc -14-

Claims (1)

1280624 拾、申請專利範®: 以下之步 -種半導體裝置之製造方法，其特徵在於進行 閘極絕 第Γ步驟，在基板上形成包含氮之氧化臈作為 緣膜， 第二步驟，在包含4^ & ψ 衣兄虱體中對前述閘極絕緣膜 進打退火處理； w 緣含，性環境_對前述絕 第四步驟，在施有前诚 形成電極膜。 4兩-人退火處理之㈣絕緣膜上 2. 如申請專利範圍第i項之半導體裝置之製造方法，复 述第二步k包含氧之環境氣體係減壓之氧氣環境氣 體，或者將氣氣和惰性氣體混合而成之環境氣體。 3. 如申„月專利乾圍第旧之半導體裝置之製造方法， 述第三步驟係以贿以上、12〇〇t以下之溫度進；。 90136.doc
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