TWI278938B - Method for forming transistor of semiconductor device - Google Patents

Method for forming transistor of semiconductor device Download PDF

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TWI278938B
TWI278938B TW095100577A TW95100577A TWI278938B TW I278938 B TWI278938 B TW I278938B TW 095100577 A TW095100577 A TW 095100577A TW 95100577 A TW95100577 A TW 95100577A TW I278938 B TWI278938 B TW I278938B
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oxide film
gate
semiconductor substrate
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forming
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TW095100577A
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TW200713462A (en
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Jae-Soo Kim
Hye-Jin Seo
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Hynix Semiconductor Inc
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Description

•1278938 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種用於形成半導體元件之電晶體的方 法，其中以高速形成具有均勻厚度之一間隙壁氧化膜。 . 【先前技術】 一半導體元件之電晶體，特別是周圍電晶體 (peri-transistor)包括PMOS電晶體與NMOS電晶體，具有高 度依賴閘極厚度均勻性之電氣特性。即是，具有均勻厚度 φ 之閘極係形成於單一晶圓或不同晶圓中，一致地改善半導 體元件之電氣特性，藉以允許半導體元件更穩健操作且改 善半導體元件之良率。 在此，用於形成具有以上閘極之半導體元件之電晶體 的習知方法將予描述。 首先，複數個閘極堆疊包括一閘極絕緣膜、一閘極傳 導膜與一硬罩膜被形成於一半導體基板上，且一低濃度雜 質被注入半導體基板，藉以在半導體基板上形成LDD區於 _ 該閘極堆疊之二側。 其後，一氧化層，如一 TEOS層，使用CVD如LPCVD 被沉積於半導體基板上，藉以形成一間隙壁氧化膜於閘極 堆疊上。實施全面蝕刻於間隙壁氧化膜上，藉以形成閘極 間隙壁於閘極堆疊之二側壁。因此，形成具有閘極堆疊之 複數個閘極與閘極間隙壁於半導體基板上。 接著，一高濃度雜質被注入半導體基板之閘極二側， 藉以形成源極/汲極。結果，產生具有LDD結構之半導體元 件之電晶體。 1278938 以上習知方法已被應用至需要高速運作之具有 PMOS電晶體與NMOS電晶體之周圍電晶體之製造方法，且 應用至半導體元件之其他製程。 因目前趨勢朝向高度積體化與超精細半導體元件之發 . 展，增加在具有相同尺寸之半導體基板上所形成之複數個 閘極堆疊密度。又，因爲大量閘極堆疊密集設置之區域， 與少量閘極堆疊稀疏設置之區域同時形成在單一半導體基 板上，在該二區域之閘極堆疊密度爲不同的。 Φ 因此，不論閘極堆疊之密度，具有均勻厚度之閘極間 隙壁須被形成於全部區域之閘極堆疊的側壁上，且包含閘 極堆疊與閘極間隙壁之複數個閘極，亦須以一均勻厚度被 形成於半導體基板上。因此包含閘極之半導體元件的電晶 體可具有均勻改善之電氣特性。 然而，依據以上習用於形成電晶體已知方法，當以CVD 如LPCVD方法形成間隙壁氧化膜，且以全面蝕刻該間隙壁 氧化膜形成閘極間隙壁時，以C V D所形成之間隙壁氧化膜 φ 在半導體基板上不能具有均勻厚度，其中依據區域複數個 閘極堆疊以不同密度設置，且因此於全部區域中形成在閘 極堆疊之側壁之閘極間隙壁不能具有均勻厚度。即是，當 以CVD形成間隙壁氧化膜時，在大量閘極堆疊密集設置區 域中之間隙壁氧化膜具有小厚度，且在少量閘極堆疊散置 區域中之間隙壁氧化膜具有大厚度。因此，在單一半導體 基扳上以全面蝕刻間隙壁氧化膜所得到之閘極間隙壁，依 據區域具有不同厚度，且在不同半導體基板上之閘極間隙 壁具有不同厚度。 1278938 形成在一既定基板之不同區域上之閘極間隙壁，經常試圖 會有不同厚度。類似地，形成在不同基板上之閘極間隙壁 試圖會有不同厚度。因此，在不同區域之閘極堆疊與 不同電晶體之間隙壁通常具有不同厚度。因此，半導體元 • 件之電晶體的電氣特性，例如PMOS之臨界電壓（Vt)特性， , 爲非均勻的。即是，增加在不同區域中PMOS電晶體之Vt差 異。 因此，於以上習知方法中，半導體元件之電晶體的電 φ 氣特性，如PMOS之Vt特性，爲非均勻的且被劣化，降低 半導體元件之良率。又，半導體元件之電晶體，特別是周 圍電晶體（形成在基板周圍之電晶體），更可能是故障失常 的。 爲解決以上問題，不用CVD如LPCVD方法，間隙壁 氧化膜之形成使用原子層沉積（ALD)，以形成閘極間隙壁與 具有均勻厚度之閘極。 然而，如對業界技藝人士將是顯明的，ALD具有低沉 p 積速度，每ALD循環僅單一原子層成長，對半導體元件之 大量生產將是困難的。 因此，用於在高速形成具有均勻厚度之間隙壁氧化 膜，而不論複數個閘極堆疊之密度的製程發展爲需要的。 【發明內容】 本發明有關於一種用於形成半導體元件之電晶體的方 法，其中具有均勻厚度之一間隙壁氧化膜以高速度被形 成。 1278938 依據本發明之一觀點，一種用於形成半導體元件之電 晶體的方法包括：藉另外供應氣體三甲基鋁與供應氣態參 -(第三烷氧基）-矽烷醇至半導體基板，形成複數個閘極堆 疊於一半導體基板上，且形成一間隙壁氧化膜於複數個閘 . 極堆疊。 _ 於閘極堆疊形成後，將複數個閘極堆疊之表面氧化。 形成LDD區於半導體基板上之閘極堆疊之二側上。連續形 成一緩衝氧化膜與一間隙壁氮化膜於複數個閘極堆疊上。 # 於一實施中，參-(第三烷氧基）-矽烷醇爲參-(第三丁 氧基）-矽烷醇或參-(第三戊氧基）-矽烷醇。 又’間隙壁氧化膜之形成宜在小於氣體壓力與溫度 225〜250°C下執行。 該方法’於間隙壁氧化膜之形成前，可進而包括以水 性酸溶液沖洗半導體基板之表面。較佳地，該水性酸溶液 可爲水性HF溶液。 【實施方式】 B 本發明將參考附圖與對應實施例詳細描述。這些實施 例係描述以例示本發明給業界通常技藝人士，且將不用以 限制本發明之範疇。 第1A至1D圖爲依據本發明之一實施例之示意切面 圖，例示用以形成半導體元件之電晶體的方法，且第2圖 爲一視圖，例示依據第1 A至1 D圖所示之方法用於形成間 隙壁氧化膜之一反應機構。 依據本發明之此實施例爲形成半導體元件之電晶體， 首先，如第1 A圖所示，形成複數個閘極堆疊丨丨〇於半導體 * 1278938 基板100上。更特定地，以連續積層一閘極絕緣膜1 02如 一氧化膜，形成閘極堆疊1 1 0，閘極傳導膜 1 04如多晶矽 膜，金屬矽化物膜106如鎢矽化物膜，與硬罩膜108如氮 化物膜，且以使用光阻膜之光蝕刻製程（未顯示）連續圖案 • 化硬罩膜108、金屬矽化物膜106、閘極傳導膜 104與閘 . 極絕緣膜102。 於形成複數個閘極堆疊1 1 0後，將閘極堆疊1 1 0之表 面輕度氧化以修復因蝕刻製程所生對閘極堆疊1 1 0之損 ® 壞。接著，注入一低濃度雜質至半導體基板1 00，藉以形成 LDD區域（未顯示）於半導體基板1〇〇上閘極堆疊11〇之二 其後，如第1 B圖所示，連續形成緩衝氧化膜1 1 4與間 隙壁氮化膜1 1 6於半導體基板1 〇〇上，包含形成在閘極堆 疊1 10上。設置緩衝氧化膜1 14於氮化物膜1 16與基板100 間，以減低該高應力，其係若氮化物膜直接形成在基板1 00 上時將會產生。間隙壁氮化膜116由氮化矽（Si3N4)組成， ® 且作爲在雜質注入步驟中一障蔽層，且一蝕刻步驟將接著 實施於該基板上。 參考第1 C圖，於形成間隙壁氮化膜1 1 6後，沉積間隙 壁氧化膜11 8於包含整個閘極堆疊1 1 〇、緩衝氧化膜1 1 4與 間隙壁氮化膜1 1 6之半導體基板1 〇〇上。更特定地，於此實 施例中間隙壁氧化膜1 1 8未以習知使用之CVD如LPCVD或 ALD方法形成，而以脈衝介電層（PdL)沉積形成，其中氣態 之三甲基鋁與氣態之參-(第三烷氧基）-矽烷醇交替供應至 1278938 • # 基板100。間隙壁氧化膜1 18、氮化物膜1 16與緩衝氧化膜1 14 在選擇位置被蝕刻以提供閘極間隙壁1 20，如第1 D圖所示。 因此，得到具有閘極間隙壁1 20、閘極絕緣膜1 02、傳導膜 104、矽化物膜106與硬罩膜108之結構130。 • 以下，參考第2圖，使用PDL沉積形成一氧化層之反 . 應機構將予描述。 如第2圖所示，供應氣態之三甲基鋁至標的層200，其中 氧化層將形成其上。接著，標的層200之矽與三甲基鋁的 ® 鋁彼此反應，藉以形成甲基鋁膜於標的層200之表面上。 其後，供應氣態之參-(第三烷氧基）-矽烷醇，如氣態之 參-(第三丁氧基）-矽烷醇或參-(第三戊氧基）-矽烷醇，至覆 鍍甲基鋁膜之標的層200。在此步驟，參-(第三烷氧基）-矽 烷醇與覆鍍在標的層200之表面上的甲基鋁膜彼此反應， 使得甲基鋁膜之鋁與參-(第三烷氧基）-矽烷醇之氧彼此鍵 結（參考第2圖之第一步驟）。 於甲基鋁之一分子與參-(第三烷氧基）-矽烷醇之一分 W 子彼此反應後，參-(第三烷氧基）-矽烷醇之其他分子可擴 散，且另外與以上鋁-氧鍵結反應由於鋁之催化反應。即 是，在標的層200之表面上之鋁不僅與參-(第三烷氧基）· 矽烷醇之一分子反應，而且與參-(第三烷氧基）-矽烷醇之多 個分子反應（參考第2圖之第二步驟）。 於一矽氧烷聚合物經由以上步驟，以參_(第三烷氧基）-矽烷醇之多個分子與鋁反應後，形成於標的層200之表面 上，矽氧烷聚合物之分子彼此反應，藉以於矽氧烷聚合物 之分子間形成交鏈（crosslinkageK參考第2圖之第3步驟）。 -10- 1278938 上述交鏈展現一自我規範特性，其中矽-氧鍵結合鋁於標的 層200之表面上，其係形成於標的層200之整個區域，具 有均勻數目。 經由上述製程，一鋁膜，即，一氧化鋁膜，形成於標 • 的層200上，且一氧化膜形成於鋁膜上（參考第2圖之第4 步驟）。以重覆供應氣態三甲基鋁與另一形式氣態參-(第三 烷氧基）-矽烷醇，形成具有所需厚度之氧化膜。 當氧化膜依據以上反應機構以 PDL沉積形成時，氧化 • 膜之多分子層由於鋁之催化反應，每周期成長於半導體基 板上。因此’ PDL沉積可以較習知ALD爲高之速度形成氧 化膜（約100倍快速於ALD)。同時，PDL沉積展現自我規範 特性，其中如ALD具有均勻厚度氧化膜被形成於基板上之 全部區域。 結果’當間隙壁氧化膜1 1 8使用以上PD L沉積，藉另 外供應氣態三甲基鋁與氣態參-(第三烷氧基）-矽烷醇至半 導體基板1 00之表面，而形成於閘極堆疊1 1 〇上時，間隙 φ 壁氧化膜118在半導體基板1〇〇之全部區域上，具有一均 勻厚度而不論閘極堆疊1 1 〇之密度。 較佳地’使用PDL沉積形成間隙壁氧化膜1 1 8在小於 大氣壓力與溫度225〜250°C下實施。此條件爲依據本發明 之一實施例，在最高速度使用PDL沉積，用以形成具有均 勻厚度之氧化層的最佳條件。 較佳地，半導體基板1 〇〇之表面，具有形成於上之複 數個閘極堆疊1 1 〇，於間隙壁氧化膜1 1 8形成前，以水性酸 溶液清洗，如水性HF溶液。經由以上清洗，半導體基板 -11- 1278938 100之表面成水化合物，且半導體基板100與/氣態三甲基鋁 之反應爲高度改善的。因此，可使用 PDL沉積以較高速 度，形成具有均勻厚度之間隙壁氧化膜1 1 8 。 回到參考第1 D圖，於形成間隙壁氧化膜1 1 8後，連續蝕刻 . 緩衝氧化膜1 1 4與間隙壁氮化膜1 1 6，且依據一習知電晶體 形成方法間隙壁氧化膜1 1 8被全面蝕刻，藉以形成閘極間 隙壁1 20於閘極堆疊1 1 〇之二側壁上。因此，複數個閘極 130分別包括閘極堆疊1 10且形成於半導體基板100上之閘 φ 極間隙壁120被形成。接著，一高濃度雜質在閘極130之 二側被注入於半導體基板100，藉以形成源極/汲極（未顯 示）。如此得到具有LDD結構之電晶體。 依據較佳實施例，於以上用於形成半導體元件之電晶 體的方法，具有均勻厚度之間隙壁氧化膜1 1 8被形成於半 導體基板1 0 0之全部區域，而不論閘極堆疊1 1 0之密度。 因此，以全面蝕刻間隙壁氧化膜1 1 8所得之閘極間隙壁 120，與含有閘極間隙壁120之閘極130，亦具有均勻厚度， 0 藉以改善半導體元件之電晶體的電氣特性，例如PMOS之 Vt特性。 鑒於本發明者所實施之實驗結果，當一間隙壁氧化膜 以習知CVD形成，如LPCVD方法，閘極間隙壁與閘極具 有因區域而變化之非均勻厚度，使得在PMOS之區域中之 Vt差異達到220mV，因而劣化半導體元件之電晶體的電氣 特性。另一方面，當一間隙壁氧化膜依據此實施例以PDL 沉積形成，閘極間隙壁與閘極在整個全部區域中具有均勻 厚度，使得在PMOS之區域中之Vt差異僅爲150mV(大約 -12- 1278938 降低70mV)。又，當間隙壁氧化膜以習知CVD形成，在PM〇S 之區域中之Vt負載效果差異爲172mV，且當間隙壁氧化膜 以PDL沉積形成，在PMOS之區域中之Vt負載效果差異爲 29mV(降低約 140mV)。 因此，依據以上描述之實施例用於形成電晶體之方 法，電晶體之電氣特性，即，周圍電晶體之電氣特性，係 均勻改善，因而允許半導體元件穩定操作與增加半導體元 件之良率。 • 從以上描述爲明顯的，本發明提供一種形成半導體元 件之電晶體的方法，其中閘極間隙壁形成電晶體與含有在 整個區域具有均勻厚度閘極間隙壁之閘極，而不論複數個 閘極堆疊之密度。 又，因爲以本發明之方法所得到之電晶體的電氣特性 被均勻改善’本發明方法允許半導體元件穩定地操作，藉 以高度改善半導體元件之品質與信賴度。本發明之方法亦 改進半導體元件之良率。 _ 本發明之以上實施例係揭示爲例示目的，技藝中人士 將瞭解各種修改、增加與替換，可不逸離所附申請專利範 圍所揭示之本發明範疇。 例如，雖然以上較佳實施例已描述藉蝕刻一緩衝氧化 膜、一間隙壁氮化膜與一間隙壁氧化膜形成閘極間隙壁， 閘極間隙壁可由僅含有間隙壁氧化膜之單一膜或含有間 隙壁氮化膜與間隙壁氧化膜之雙層膜製成。 【圖式簡單說明】 第1A至1D圖爲依據本發明之一實施例之示意切面 圖，例示用以形成半導體元件之電晶體的方法。 -13- 1278938 1 D圖所示之方法， 第2圖爲一視圖例示依據第1 Α ΐ 用於形成間隙壁氧化膜之一反應機構 【主要元件符號說明】 100 半 導 體 基 板 102 閘 極 絕 緣 膜 104 閘 極 傳 導 膜 106 金 屬 矽 化 物 膜 108 硬 罩 膜 1 10 閘 極 堆 疊 1 14 緩 衝 氧 化 膜 116 間 隙 壁 氮 化 物膜 1 18 間 隙 壁 氧 化 膜 120 閘 極 間 隙 壁
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Claims (1)

1278938 十、申請專利範圍： 1 · 一種用於在半導體基板上形成電晶體之方法，包括： 在一既定環境下提供半導體基板； 形成複數個閘極堆疊於該半導體基板上；及 . 藉另外供應氣態三甲基銘與氣態參-(第三院氧基）-砂院 醇進入提供半導體基板之既定環境，形成一間隙壁氧化 膜於複數個閘極堆疊上。 2 ·如申請專利範圍第1項之方法，其中於閘極堆疊形成 _ 後，進而包括： 氧化複數個閘極堆疊之表面； 形成LDD區於半導體基板上閘極堆疊之二側；及 連續形成一緩衝氧化膜與一間隙壁氮化膜於複數個閘 極堆疊上。 3.如申請專利範圍第2項之方法，其中參·（第三院氧基卜矽 烷醇爲參-(第三丁氧基）_矽烷醇或參-(第三戊氧基）·矽烷 醇。 d 4 ·如申請專利範圍第2項之方法，其中間隙壁氧化膜之形 成在小於大氣壓力與溫度225〜250 °C下實施。 5 ·如申請專利範圍第2項之方法，進而包括： 於形成間隙壁氧化膜前，以水性酸溶液清潔半導體基 板之表面。 6 ·如申請專利範圍第5項之方法，其中該水性酸溶液爲水 性HF溶液。 -15- 1278938 7. 如申請專利範圍第1項之方法，其中參第三烷氧基）-矽 烷醇爲參-(第三丁氧基）-矽烷醇或參-(第三戊氧基）-矽烷 醇。 8. 如申請專利範圍第丨項之方法，其中間隙壁氧化膜之形 、 成在小於大氣壓力與溫度225〜25(TC下實施。 β 9 ·如申請專利範圍第1項之方法，更包括： 於形成間隙壁氧化膜前，以水性酸溶液清潔半導體基 板之表面。 # 1 〇 ·如申請專利範圍第9項之方法，其中水性酸溶液爲水性 HF溶液。
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US20020127763A1 (en) * 2000-12-28 2002-09-12 Mohamed Arafa Sidewall spacers and methods of making same
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US6638879B2 (en) * 2001-12-06 2003-10-28 Macronix International Co., Ltd. Method for forming nitride spacer by using atomic layer deposition
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