TWI270140B - A method for forming a thin complete high-permittivity dielectric layer - Google Patents

A method for forming a thin complete high-permittivity dielectric layer Download PDF

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TWI270140B
TWI270140B TW094132436A TW94132436A TWI270140B TW I270140 B TWI270140 B TW I270140B TW 094132436 A TW094132436 A TW 094132436A TW 94132436 A TW94132436 A TW 94132436A TW I270140 B TWI270140 B TW I270140B
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Taiwan
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layer
high dielectric
substrate
dielectric constant
thin
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TW094132436A
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English (en)
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TW200623264A (en
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Cory Wajda
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Tokyo Electron Ltd
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8232—Field-effect technology
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    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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Description

1270140 九、發明說明： 【發明所屬之技術領域】 應用於，顧於半導雜 【先前技術】 半導體產業中，微電子元件之最小特徵尺寸； f代合對於較快和較低功率之微 電^^ 侷限，其中標準之二氧化卿侧極以 i了電(〜1_(AngstiOm))，射雜紐並大大影 總增進元件可靠度並減少由_極至電日日日體通道之漏·， 大約少於r5ii=度 效氧化層厚度(Ε〇τ)維持在 j叙姉1度方法，係錢具有 = ΐ由於電料與=以匕 认入1Z介電常數材料—般泛指具有比Si()2 (k〜3.9)更大之介雷當赵
Hfi電ί(Γ、:ίϊ ’高介電常數材料係指沈積於基板(例如： 上之2介電材(例如：_、_y) 包括Ta η Γμ電數材科亦可包括金屬石夕酸鹽或氧化物， (^Τ1Γ;(Μ0)'Zr〇2 (k^25)' αιλ ^^ 微電子元#艮2 (〜25)。在次微米世代中，製造具尺寸特徵之 有形成具有最小間隙和最小厚度變化(例如··具 厚度)之極薄高介電常數層。 ' 錄提出-種在基板上形成—完全高介電常數之薄介電層之方 1270140 一忒方法&供一種形成具有隶小間隙和好的厚度—八 之薄介電層的製程，其中又包含以下步驟:d 板；積，介電常y薄化以在該基板 將常!層高==良或薄化’及使用蝴程⑶介ϊ
=明之—實施例中，所述完全高介電f數之厚介電芦可且 ^大、、、勺；,於30〜200埃之厚度。另外，該完全高介電常數之^電 層之厚度可大約介於5〇〜1〇〇埃之間。需知道，形成 古人 J層，,二、厚度也許因為不同的高介電常數材料而有；電： ^因此，達到希望之完全高介電f數層，__如4b) f層之一 °卩分，使該完全高介電常數層維持在一希望之較薄厚 二。本發明之-實施例中’所述完全高介電常數之薄介電声可且 $約介於5〜5G埃之厚度。又，該完全高介電常數 厚度可大約介於30〜40埃之間。 辟"电層乙 【實施方式】 圖1A-1B係顯示含有依據本發明之實施例所形成之 ，層之閘極堆疊的剖面圖。圖认係顯示一經過非等向性餘刻 ，理$、形成齡]特性之不完全閘極堆疊刚。用來作為範例之間 極堆豐100，包含一具有源極區113和汲極區114之基板1〇2、j一介 電介面層1G4、-★介電常數層1Q6、—閘電極層⑽、 佈(ARC)/硬光罩層11〇、及一光阻層112。該基板1〇2可含有別、&、 Si/Ge、或GaAs。本發明之一實施例中，基板1〇2可為一含有矽石 晶^itaxial S〇或多晶矽(ρ〇1Μ〇之矽基板。端視所形成之元件= 定，該矽基板可為η型或ρ型。基板1〇2可以為任何尺寸，像是一2〇〇 mm基板、300mm基板、或甚至為更大之基板。 1270140 所述介電介面層104,可為一氧化層(例如ji〇2)、一氮化層(例 如：SiNx)、或一氧氮化矽層(例如：Si〇xNy)，或是由其中數者所組 成。在基板表面之介電介面層104可維持介面狀態特性，並且在高 介電常數層106和基板1〇2之間形成一具有好的電特性之介面。然 而，所述介面層104之存在可降低閘極堆疊1〇〇之整體介電當了
薄·。積體電路含有一通常運用二氧化矽(Si〇2)和/或氧氮化矽 (SiOxNy)介面層之矽基板，可具有極佳之電特性(包含高電子移動 率和電子缺陷您度）。目前，含有一層於二氧化矽(Si〇2)和/或氧氮 化矽(SiOxNy)介面層形成之高介電常數層之閘極堆疊僅 ^ 約5〜10埃之介面層厚度。 ’ =述高介電常數層係依據本發明之方法而形成，茲將詳述於 下。南介電常數層106可包含-金屬氧化物或-金屬御_，包括
Ta205、Ti02、Zr02、Α12〇3、Y2〇3、HfSi〇x、Hf〇2、ZrSi〇x、TaSi〇x、
SrOx、SrSiOx、La〇x、LaSiOx、Y〇x、或YSi〇x，或是由二種或X多 種所組成。該高介電常數層1〇6之厚度，可大約介於5〜5〇埃之間， 亦可大約^於30〜40埃之間。圖丨之閘電極層應可以是摻雜多晶 石f。那些热悉微景^技術和電漿韻刻的人，係習知如何選擇適當之 杬反射塗佈(ARC)/硬光罩層110和光阻層112，以獲得具希望^ 寸的姓刻特性。 圖1B係顯不經過形成蝕刻特性所需之非等向性電漿蝕 之後之另一不完全閘極堆疊1〇1。除了圖丨入中所示之材料層之 所巧極堆疊101又含有一金屬閘電極層1〇7。該金屬閘電价 之厚度大約可為100埃，並且包含 射夕夕閘電極層可帶來幾個好處，包括去除多晶 “之#it潛穩=進階之高介電常數層上達到 圖2Α〜2D係顯示依本發明之一實施例之在基板上形成一完全 Ι270Ϊ40 二數之薄介電層。圖2A係顯示—基板結構2⑻，1中又 其上之介電介面層綱之基板2G2。如上所^，該介面 :04可以為一氧化層、一氮化層、或一氧氮化石夕層 ^，些熟悉半導體處理的人應該狀形成氧氮及 觀化石夕層之製程。另外，介面層204不-定要呈現。 及 長模ΪΪ，ΪΪ積—薄膜於基板時，可以使用各種不同之薄膜成 破，V〇lmer_Weber薄膜成長係以基板上之島狀成長為其特 ^ ’而StranskHrastanov薄膜成長係以高介電常數材料在基板上之 島狀結構和層狀成長為其特徵。v〇lmer_Weber和/ StmnSki_Kmstan〇v成長模式時常被奉行。 ^ 圖2B係顯示形成在介面層2〇4上之高介電常數材料2〇3之島狀 如上所述，該高介電常數材料2〇3可包含一金屬氧化物或一 H石夕酸鹽，或由二者組成。圖2輯顯示當將一高介電常數材料 203沈積於一介面層2〇4之v〇lmer_Webei^長模式。並非形成沒 隙且具有好的厚度均勻度之完全高介電常數之薄介電層 (Frank-Van der Merw^長模式），圖沈描述之沈積製程係形成數^ =過沈，、具有間隙之高介電常數材料2〇3之島狀結構，係暴露於 介於各高介電常數島狀結構之介面層2〇4。在圖2B，各島狀結構具 有大約介於5〜50埃(或更大)之厚度，端視使用之高介電常數g 料203和介面層204之類型，該島狀結構之厚度ο%3和橫向尺寸可能 有^不同。另外，該島狀結構之厚度Ο%3和橫向尺寸可視所述高 電常數材料203和介面層2〇4之沈積和退火狀況而定。 高介電常數材料203，可經由使用各種那些熟悉薄膜沈積技術 之人所習知之沈積製程而被沈積於介面層204，其中薄膜沈積包括 (但不侷限於此)熱化學氣相沈積(TCVD)、電漿輔助化學氣相沈積 (PECVD)、原子層沈積(ALD)、及物理氣相沈積(PVD)。圖4係顯^ 和說明一在熱化學氣相沈積(TCVD)製程中用以將高介電常 沈積於一基板之電漿處理系統。 θ 1270140 ，-尚介電常數層整合於該基板結構細，其必要條 W ”電常=203在介面層204(沒有介面層時即在基板2〇2)形成 '電吊數層，及該完全高介電常數層需具有好的厚 ϋ了具有好的厚度均勻度之完全高介電常數層，以增 靠/和減少由—在高介電常數層203上面之閘4極到i 3全及該完全高介電常數層需具有好的厚度均 可 板202之漏電
面常數層進一步沈積於基板結構200，即在介 曰上形成一凡王尚介電常數之厚介電層200 (如圖2C所示 ，此之完全高介電常數層係指—種完全覆蓋(例 持續覆蓋其 3下介面層204★基板202、其間沒有任何間隙之高介電常 完全冑介電常數之厚介電獅6可具社_〜埃之 f度〇2〇6，並且有好的厚度均勻度。如上所述，在達到完全 前必須沈積之高介電常數層必之最小厚度，因為不同之 二而Ϊ所不同’但是通常大於50埃。然而，厚度〜6 处^午夕半V體兀件而言(例如··需要大約介於1〇〜4〇埃之⑽)可 小於心之厚度之完全高介㈣數之薄介電層無法輕 ^沈積於;丨面層204。因此，藉由本發明之方法，首先形成具厚 度D2o6之完全高介電常數層，然後將其薄化以達到想要之小於 之厚度。 圖2D係顯不依據本發明之一實施例而形成一完全高介電常數 之溥^電層207。該完全高介電常數之薄介電層2G7，係經由如圖 2—C所示之完全高介電常數之厚介電層2〇6之第一沈積而形成，接 著丄將完全高介電常數之厚介電層206薄化以形成一具厚度d2o6 ，完全高介數之*介電層2。7，其巾厚度D2G7，】、於D2c)6。依據 本發明之一貫施例，厚度DM可大約介於3〇〜2〇〇埃。又。厚度D%6 可大約介於50〜1〇〇埃。根據本發明之一實施例，厚度D撕可大約介 於5〜50埃。又，厚度D2〇7可大約介於30〜40埃。 根據本發明之一實施例，完全高介電常數之厚介電層2〇6之薄 化可在一電漿處理系統中實施。根據本發明之一實施例，所述薄 1270140 化可經由使用侵蝕性含鹵素氣體之完全高介電常數之厚介電層 206之反應性電漿姓刻而進行，該侵|虫性含鹵素氣體與該完全高介 電常數之厚介電層206產生反應，以形成將由該電漿處理系統移除 之含鹵素蝕刻生成物。可使用具有HX、X2、cxXz、或CxHyXz之一 般分子之含鹵素氣體，其中X為鹵素。
圖2E-2F係顯示依本發明之一實施例在基板上形成一完全高 介電常數之薄介電層。圖2C之完全高介電常數之厚介電層2〇6之薄 化可藉由一種結合濕式製程之電漿改良/薄化製程而實施。離子轟 擊(Ion bombardment)可用來部分移除和/或改良圖21?之完全高介電 常數之厚介電層206，而不會完全將其移除。 ，2E係顯示一在完全高介電常數之厚介電層2〇6上實施電漿 改良/薄化製程之後所呈現之改良部分2〇6a。在一實例，電漿可含 有一種反應性氣體(例如：HBr或HC1)及一種惰性氣體。在另一實 例中，電漿也許只含有在一電漿環境中對該完全高介電常數之厚 介電層206不反應之化學惰性氣體種類，但是其中離子具有足夠之 能量來有效的崩解和/或薄化該高介電常數層2〇6，以致豆後之濕 蝕刻製程能夠有效的將已崩解（已改良)部分2〇6a由未'改良g ^ 206b移除。所述惰性氣體可含有各高貴氣體，例如He、Ne、Ar、 Kr、及Xe。所述電漿改良/薄化製程之確切效果係取決於用於 處理中之氣體。據悉，電漿處理也許會增加完全高介電常數之^ 介電層206之非晶矽含量，及有可能破壞建立在該已改良部分 之原子片段之化學鍵。所提議之在電漿處理中崩解已 206a之分子結構，可給μ改良部分施在騎赋糊化 用時較大之選擇性，即使其相較於所述未改良部分2〇6b、 204、及基板202具有高侧選擇性。接下來之濕式敍刻 : 用熱硫酸(HAO4)或氫氟酸(HF(aq))以將該已改良部分2〇 良部分206b移除，藉此形成一具有厚度DM之完全高介 i電ΐΤί，介電常數層之已改良部分為在電製改良/薄;匕 製程中並不會來回移動，在介面層204和基板2〇2之下笋化 1270140 可能性隨即減少。用以從各基板移除各薄層之濕式製程係為那些 熟悉導體處理技術者所熟知。 、〃二 將完全高介電常數之厚介電層206加以電漿處理，可導致介面 層204厚度之增加。在與本案(之美國對應專利申請案)同日提出的 美國專利申請案第10/954，104號，其標題為”A METHOD AM) SYSTEM FOR FORMING A FEATURE IN A HIGH-K LAYER" 中，已說明一種在電漿處理中將完全高介電常數之厚介電層2〇6之 介面層204之厚度增加減至最小的方法。該專利案之内容整9體供作 本案之參考。 ' 圖3係一說明依本發明之實施例形成一完全高介電常數之薄 介電層之方法流程圖。所述製程3〇〇包含在步驟3〇2於一處理室設 置一基板，其中該處理室係用以將高介電常數層沈積於一基板二 在本發明之-實關中，所述基板又包含—形成於職板上之介 =。在步驟304，-高介電常數層係沈積於該基 ^程5施了所希望之-段時間，以在基板形成—完全高^電^ 2旱;1電f °在步驟3G6 ’該完全高介電常數之厚介電層被加以 以形成-完全高介電常數之薄介騎。本㈣之一實施例 中丄薄化可經由使用反應性電漿_而加以實行 ’電漿處理可包含—賴改良/薄化製程，係接續在一 ^ =仗^冋介電常數層之未改良部分移除其中已 =此技術之人應知道，圖3之流程圖中各步驟或ί ^ 又已3或多個步驟和/或操作。因 Γ另皮，縣發明之方法限定於只有^^或階 ΐ製ί 、304、306不應被視為受限於僅為一單 奸圖發明之—實_之—__高介電常數 層於基板之私康處理系統。尤其，處 一 述處理糸統400包括-處理室4〇2、一氣體注入系統柳、一幫浦系 1270140 一處理[視系統438、及一控制器436。該處理室4〇2又包 妹* 土一’其上附有一將要處理之基板406。絲板406可 槽閥(未顯示於圖中)及處理室饋通部(未顯示於圖中)藉由一 v 土板轉移系統而被傳送於該處理室402之内外間，其中該基板 Ϊ由ΐΐ於基板平台撕中之基板升降銷(未顯示於圖中所接收， 二ί怂：,於其中之裝置加以機械轉移。一旦基板406由該基板傳 =糸，收到，該基板即降低至基板平台姻之上表面。所述基板概 ^以為-雜板，而且視所形成之元件類型而定，可含有具任何 直徑之基板，例如2〇〇mm、300mm、或甚至更大之基板。 基板406可藉由-靜電钳(未顯示於圖中）而附著於基板平台 另禮、另^卜’该基反平/4〇4又包含一含有能由基板平台404接收熱 專=,、、、至一熱交換系統(未顯示於圖中）、或當加熱時由該埶交換 送熱之再循還冷卻劑流的冷卻系統。另外，氣體也許被傳 =至基板406之背面，以提昇基板4〇6和基板平台4〇4之間之 率°此—系統可以在升高麟低溫度時需要控縣板406之 溫度時加以運用。
/一氣體注入系統408導入處理氣體41〇至處理室4〇2。該氣體注 統包括一液體傳遞系統(LDS) 420，係包含至少一含有一種 间介電常數前驅物質之前驅物源422。將前驅物質導入蒸餾哭“ :經由使用-液態氣體流量控制器(LMFC) 424而加以控制。TO來自 =餾器42=之已蒸發前驅物質可與經由氣體管線43〇由氣瓶幻8傳 承載氣體混合，而該混合物又可藉由氣體管線434而傳送至處 J室402。淨化氣體(例如：Ar)及其他氣體(例如：〇2、N2、H =使賴外之氣體管線432而由氣瓶428直接傳送至處理室 二。氣f注人系統他能對於將處理氣體41°由非即時量測氣體源 =至處理室搬野以獨立控制。該氣體注人系統儒可運用一 ，喷佈氣體源，例如處理室4。2巾之—蓮蓬頭。在本發明之另 ，例，該氣體注入系統408可被設置來蒸發一固態前驅物質，及二 由氣體管線434傳送已蒸發之前驅物質至處理室4〇2。 g 12 一真空幫浦系統412，包括一真空幫浦418、一收集哭416 二自動壓力控制器(APC) 414。該真空幫浦418可包含加速 每秒5000公升(及更大)之分子渦輪真空幫浦(ΤΜΡ)和一用以調r 處理室壓力之閘閥。另，該真空幫浦418可包含一乾式幫浦。 過程中，處理氣體410可經由氣體注入系統408被導入處理室4〇2， 處理壓力可藉由自動壓力控制器414來加以調整。該收集器416 由處理室402收集未反應之前驅物質和附帶產生之結果。
1270140 一控制器436，包含一微處理器、記憶體、及一數位1/〇埠，能 夠產生足以傳達和啟動輸入至處理系統4〇〇並監控由該處理系^ 4〇〇輸出之控制電壓。另外，控制器436係與處理室4〇2、處理“視 :系統438、氣體注入系統408、及真空幫浦系統412耦合並且交^資 ，。了儲存於記憶體中之程式係依據儲存之製程配方以控制上述 處理系統400之各元件。該控制器436之一例子為Ddl公司 n
Texas)之DELL PRECISION WORKSTATION 610™。 ’ 處理監視纽438可啦各魏體物種，例如獅物、反應附 f產物、及處理環境中之其他氣體。圖4中之處理監視系統438各 讀係依附在該處理室4G2。在另-實施例中，處理監視系統438 ，一些元件係位於該處理室4〇2之下游。所述處理監視系統438可 二控制器436’使用，_定該沈積製程之狀態，及提供以 確保符合製程。 基板406係曝露於該處理氣體一段時間，導致所希望之該高介 ，系數層之沈積。能促使該高介電常數層獲致所希望之沈積之製 ，狀況，也許是由直接實驗和(或)實驗設計所決定。舉例而言，可 ^整^製程參數可包括時間、溫度(例如··基板溫度）、處理壓力、 ^理氣體和處理氣體之相對氣流、及其他參數。所述沈積製程之 工，參數可使_小於1GT()rr之處理室壓力、小於2_§_之處 ^軋體解、祕1GGG seem之前驅物氣體辭、及狀於攝氏2〇〇 度之基板溫度。 當運用熱化學氣相沈積(TCVD)製程沈積—金屬氧化高介電 13 1270140 常數層’包括一種含金屬前驅物之處理氣體被導入一含有將要處 理之加熱基板的處理室。該基板暴露於該處理氣體一段時間，因 而〒致所希望之该金屬氧化高介電常數層之沈積。金屬氧化高介 電常數材料可因為該金屬氧化化學氣相沈前驅物而 • 加以沈積。在一具有Hf和Zr (M=Hf，Zr)範例中，該金屬氧化化學 氣相沈積(MOCVD)前驅物可包括金屬烷氧化物(例如：M(〇R)n)和 金屬烧酸胺(例如·· M(NR)4)，可在高於攝氏3〇〇度之基板溫度沈積 金屬氧化層。所述金屬烧氧化物前驅物可由四配位複合物選出， 例如 MCOMeVMCOEtVMCOPi^jMCOBAjtMegmethylCf •基)、Et 為 ethyl(乙基)、Pr 為 propyl(丙基)、及Bu%tert-buty(特丁基）。 響 所述金屬烧醯胺前驅物可由M(NMe2)4、M(NEt2)4、及M(NPr2)4當 中選出。所述金屬氧化化學氣相沈積(MOCVD)前驅物亦可由六配 位複合物選出，例如：MCOBu^MMP)〗和M(MMP)4，其中 MMP=〇CMe2CH2〇Me。熟習於此技術者應悉知，使用其他含/有金 屬之前驅物並沒有脫離本發明之範嘴。 Ηί^ΟΒιι%係一含給金屬氧化化學氣相沈積(M〇cVD)前驅 物，能促使元件製造所需之Hf02高介電常數層之沈積。Hf(〇But)4 -係包括一較高蒸氣壓(攝氏65度時為Pvap〜iTorr)，因此需要將前驅 物稍微加熱及傳送該前驅物至處理室所需之前驅物傳輸線。此 _ 外’ Hf^OBu)4在小於攝氏200度之溫度下不會分解，由於其與室壁 之作用和氣相反應’即會大大減少前驅物之分解。所述pjf(〇But)4 前驅物可經由使用一含有一溫度維持在攝氏5〇度或更高之蒸餾器4 之液體注入系統而被傳送至該處理室。一種惰性載氣(例如：He、 NO可與該蒸發之前驅物混合，以促使該前驅物被傳送至處理室。
Hf(OBu)4係含有在適當之製程狀況下長成化學當量 (stoichiometric) Hf〇2層所需之Hf金屬和氧氣，藉此能減少製程^雜 度。又，含有該金屬氧化化學氣相沈積(M〇CVD)前驅物之處理 體，可又含有弟一含氧氣體作為氧氣之第二來源。 ' 同樣的，金屬矽酸鹽高介電常數材料可以由金屬氧化化學氣 1270140 相沈積(MOCVD)前驅物和一種含矽氣體而沈積。舉例而言， HfSiOx南介電常數層經由使用Hf(OBu)4前驅物和一種含石夕氣體 而被沈積於一基板。所述含石夕氣體可包含silane (SiH4)[石夕烧]、 disilane ^2¾)[乙矽烷]、dichlorosilane (SiH2Cl2)[二氯矽甲烷]、 hexachlorodisilane (Si2Cl6)[六氣二矽乙烷]、bis (tertbutylamino) silane (8ϋ12(ΝΒιι)2)[雙（第三 丁氨基）矽烷]、或 tetrakis • (dimethylamino) silane (Si(NMe2)4)[四（二曱氨基）矽烷]、 tetraethylorthosilicate (TEOS，Si(OEt)4))[四乙基石夕]，或由二者或多 種所組成。 所述處理氣體又可包括一承載氣體(例如：惰性氣體)和一氧化 氣體。該惰性氣體可包含下列至少一種氣體：Ar、He、Ne、Kr、 Xe、及N2。惰性氣體之加入可稀釋該處理氣體或調節該處理氣體 之部分氣壓。氧化氣體可含有包括〇2、〇3、Η2〇、Η2〇2、Ν〇、ν〇2、 及即等其中至少一種含氧氣體。該含氧氣體在沈積製程之角色係 可以在該金屬氧化物或金屬矽酸鹽高介電常數層中填補任何氧空 缺，、或以化學物改良該金屬氧化前驅物。所述改良又可包括在氣 相或沈積表面以金屬氧化前驅物與該含氧氣體產生作用。 ;圖/〜8係顯雜^發明之各實施例之電漿處理系統，該系統也 許可藉由對-完全高介f常數之厚介t層電漿處理則彡成 高介電常數之薄介電層。圖5細雜本發明之—實_之 ίί ίί電ίΐ層ί ΐί處理系統。圖5所描述之電漿處理系統1 月匕夠維持-電水，及包含—用以促進電聚在處理區 ，理室Η)。該電漿處理系，又包括—其上附著—將要處理= ϊΐίΐϊ:台'—用以導入處理氣體42至電漿處理室1〇之i 入υ4〇、収傳捕頻神至基板平㈣之射頻產 路32、一真空幫浦系統50、-電製監視系統57 °、 至】里氣體由非即時量測氣體源傳送 至搞理至予以獨立控制。—種離子化氣體或混合氣體係藉^氣 15 1270140 體注入系統40被導入，而處理壓力係被加以調整。舉例而古， 制器55係用來控制真空幫浦系統50和氣體注入系統4〇。 σ玉 基板25係藉由一槽閥(未顯示於圖中)和處理室饋通部(未顯示 於圖中）藉由一自動基板轉移系統而被傳送到處理室及傳送7出 來，其中該基板係由設置於基板平台2〇中之基板升降銷(未顯示於 圖中)所接收，並且由設置於其中之裝置加以機械轉移。一旦基板 25由該基板傳送系統收到，該基板即降低至基板平台2〇之上表^。 : 另一實施例中，基板乃係藉由一靜電鉗（未顯示於圖中^而依 附於基板平台20。另外，基板平台20又包含一含有能由基板 _ 接收熱及傳送熱至一熱交換系統(未顯示於圖中）、或當加熱時: 忒熱父換系統傳送熱之再循還冷卻劑流的冷卻系統(未顯示於圖 中）。另外，氣體也許被傳送至基板25之背面，以促進所^基板& 和基板平台20之間之氣體空隙熱導率。此一系統可以在升高 低溫度時需要控制基板之溫度時加以運用。舉例而言，控^基 之溫度也許對於超過穩態溫度之溫度有用，因為藉由基板平=2〇 ^傳導使得由電漿傳送至基板25之熱流量和由基板25去除之&流 量達到平衡。其他實施例中包含各種發熱元件，例如電阻加 ‘ 件、或熱電加熱器/冷卻器。 …、 ▲咖、圖5所示之實施例巾，基板平台2〇又可作為一電極，藉此射頻 鲁()功率係與處理區45之電漿麵合。舉例而言，基板平台2〇可、妙 由傳送射頻功率由一射頻產生器30、經由一阻抗匹配網路幻至^ ^台2G而在—射頻電壓受到電性偏壓。所述射頻偏壓係用來& ，"、、電子，藉此形成及維持電漿。在此配置下，所述系統係操作 為了活性離子蝕刻(RIE)反應裝置，其中該處理室和上氣體注入電 極係當作接地表面。所述射頻偏壓之一般頻率係介於1〜1〇〇mh 而且最好為13.56 MHz。
“在另一貫施例中，射頻功率可以多重頻率用於該基板平台之 電極。另外，阻抗匹配網路32係用來經由將反射率減 二 將處理室ω中傳送射頻功率至電漿增至最大。匹配丰網路拓K 16 1270140 二型)^自動控制方法係在先前技術為人所熟知。 處理i: 42係由—可包含-蓮蓬頭，其中該處理氣體 示於圖中圖n_—氣體注人空間(未顯 及-多孔触(未齡於_、 之分=真===二=，更大) ;4ί4ί；：,ί lOOmTorr)，即可使用機械升壓幫浦和乾式低真空幫浦。大於 豹遙If制Ϊ5!包含一微處理器、一記憶體、及-數位1/0埠，能 ，產^以傳達和啟動輸人至處理系統以監早; 出之控制碰。另外，該㈣狀健棚產生阻 網路32、氣體注人系統4G、f浆監視系統57、及真空幫浦％ 儲存於記憶體之程式係依據儲存製程配方 控制上述電水處理糸統1之各元件。所述控制器55之一 公司(驗，τ—之數位訊號處理器(型‘ 電漿監視系統57可包括-光學放射光譜儀(〇ES)系統 量電漿環境和/或-電漿診斷系統中之激發分子，例如用旦’雷 漿密度之朗米爾(Langmuir)電子探針。該電漿監視系統57可盘二 器55-起使用’以裁定舰刻製程之狀態，及提供反饋^= 合製程。另’電漿監視系統57可包括—微波和/或一射頻診缔付 圖6係顯示依本發明之另一實施例之一用以處理高介電; 層之電漿處理系統。除了包含描述於圖5之電漿處理系统丨^一 件之外，圖6之電漿處理系統2又包含一機械或電力轉動〇(：磁俨= 統60，以潛在增加電漿密度和/或提升電漿處理之均勻性。另 17 1270140 $制器55係與該轉動磁場系統_合，以調節旋轉速度和磁場強 層之實關LX處理高介電常數 由一阻抗匹配網路74由一射镅吝丛哭79妯缸入m 、力半係猎 頻功率之-㈣隸人j頻產生被1合。祕上電極之射 !力旱之U羊係，丨於10〜200 mhz，如60mhz 土板平台2?之功率的一般頻率係介於〇卜雇出，如2應Z。』 外’控制器55係與㈣產生器72和阻抗匹 制用於上電極70之射頻功率。 ❽斗雜口，以控 圖8係顯示依本發明之另—實施例之—用以處理高介電 ς J電，處理系統。圖8之電漿處理系統4除了包含圖 f處理糸統1之各元件’又包含-感應線酬，藉此射頻功率係J 由一Ρ且抗匹配網路84由-射難生觀被搞合。射頻功率係由^ 應線圈80經由-介電窗(未顯示於圖中）而與電漿處理區45電、感& 合。用於感應線圈80之射頻功率的一般頻率可介μ1〇〜1〇〇ΜΗζ， 例如13.56 MHz。相似的，用於基板平台2〇之功率的一般頻率可介 =〜30 MHz ’如13.56 MHz。此外，可使用一狹縫式法拉第遮 罩(未顯示於圖中）’以減少感應線圈80和電漿之間之電容耦合。另 外’控制器55係與射頻產生器82和阻抗匹配網路84相轉合，以控 制用於感應線圈80之功率。 口 二 、在另一實施例中，電漿係經由使用電子迴旋共振(ECR)而形 成。而在另一實施例，電漿係藉由發動螺旋波而形成。在另一實 施例中，電漿係經由傳導表面波而形成。 本發明可在不離開隨附之申請專利範圍内作各種修改和變 化。那些熟悉本技術的人將察覺到本發明之範圍並非由在此之說 明所限制，所有在本發明之範圍内之變化均應包含於本發明之中。 【圖式簡單說明】 附加圖示中： 18 1270140 圖1A〜1B係顯示含右— 數層之閘極堆疊的剖面^了由本發明之實施例所形成之高介電常 圖2 A〜2 D係顯示依太 介電常數之薄介電層；I月之一實施例在基板上形成一完全高 圖2E〜2F係顯示依太 高介電常數之薄介電芦· &月之另一實施例在基板上形成一完全 圖3係顯示依本發明 ^ /丄 數之薄介電層的流程圖;之-貫施例之用以形成-完全高介電常
之處—依本發明之實施例設置以沈積—高介電常數層 之電Si:依本發明之-實施例之-用以處理高介電常數層 層發明之另-實施例之-用以處理高介電常數 昆示依本發明之另一實施例之一用以處理高介電常數 層之電漿處理系統；及 圖8係顯示依本發明之另一實施例之用以處理高介電常數層 之電漿處理系統。 、 【主要元件符號說明】 1 ' 2'3、4 :電漿處理系統 10 :處理室 20 :基板平台 25 ·基板 3Q ' 72 ' 82 :射頻產生器 32 ' 74 N 84 :阻抗匹配網路 40 ··氣體注入系統 42 :處理氣體 45 ·•電漿處理區 50 ··真空幫浦系統 1270140 55 :控制器 57 :電漿監視系統 60 ··機械或電力轉動DC磁場系統 70 :上板電極 80 :感應線圈 100 ··閘極堆疊 101 :不完全閘極堆疊 102、202 :基板 104、204 ··介電介面層 106 :高介電常數層 107 :金屬閘電極層 108 :閘電極層 110 :抗反射塗佈(ARC)/硬光罩層 112 :光阻層 113、114 :源極區 200 :基板結構 202:基板 203 :南介電常數材料 204:介面層 206 :完全高介電常數之厚介電層 206a:高介電常數層之改良部分 206b:高介電常數層之未改良部分 207 :完全高介電常數之薄介電層 〇203、〇2〇6、D207 :厚度 300 :製程 302 ··在一處理室設置一基板 304 :沈積一完全高介電常數之厚介電層於該基板 306 :將該完全高介電常數之厚介電層薄化，以在該基板形成 一完全高介電常數之薄介電層 1270140 400 :處理系統 402 :處理室 404 :基板平台 406 :將要處理之基板 408 :氣體注入系統 410 :處理氣體 412 :幫浦系統 414 :自動壓力控制器（APC) 416 :收集器 418 ··真空幫浦 420 :液體傳遞系統(LDS) 422 :前驅物源 424 :液態氣體流量控制器(LMFC) 426 :蒸餾器 428 :氣瓶 430、432、434 :氣體管線 436 :控制器 438 :處理監視系統 21

Claims (1)

1270140 十、申請專利範圍： L ，在^板形成完全高介電常數之薄介電層之方法，包括： 在—處理室設置一基板； 一 高介電常數材料到至少-最小厚度，以在基板上形成 元王鬲；丨電常數之厚介電層；及 戸声將,ν二全南介電常數之厚介電層薄化至小於最小厚度之希望 尽度，以形成-完全高介電常數之薄介電層。 項之在基板形成完全高介電常數之薄介電層 =該高介電常數材料包紐办、Ti〇2、加2、Al2〇3、 YO 3> Hf〇2'ZrSl〇X Λ TaSi〇x Λ Sr〇x N SrSi〇x'La〇x'LaSi〇x Λ Y〇x、或ys1〇x，或其中二種或多種之組合。 第巧之在基板形成完全高介電常數之薄介電層 於30^200^該完全高介電常數之厚介電層之最小厚度，大約介 板形成完全高介電常數之薄介電層 於5(M〇’(^中該完全高介電常數之厚介電層之最小厚度，大約介 項之在基板形成完全高介電錄之薄介電層 電健助;1^?，介電常數材料之沈積又包括熱化學氣相沈積、 電水輔助化學氣相沈積、原子層沈積、或物理氣相沈積。 介於5〜50埃所希王 间介電常數之薄介電層之厚度，大約 22 1270140 7.：^申μ專利域幻項之在基板形成完全高 中所希望之完全高介電常數之薄介電層之厚ί= 範圍第1項之在絲職完全高介電常數之薄介電層 /，八中在一處理室設置一基板之製程又包括設置一且右一 高介電常數材料之製程又 狀在基板形紋全高介tt數之薄介電層 層，ΐ由:：=面層包括一氧化層、-氮化層、或-氧氮化矽 曰及由一者或多種所組成。 圍第1項之在基板形成完全高介電常數之薄介電 其中_高介電常數層薄化又包括_沈積之 吊數層曝路於電漿處理中。 請專利範圍第ι〇項之在基板形成完全高介電常數之薄介電 曰 法，其中電漿處理包括一種含有惰性氣體之處理氣體。 ==請專利範圍第η項之在基板形成完全高介電常數之薄介電 二法’其中該惰性氣體包括He、Ne、Ar、Kr、或Xe， 一種或多種氣體之組合。 /、肀 申請專利範圍第11項之在基板形成完全高介電常數之薄介電 曰方法，其中該處理氣體又包括一種反應性氣體。 請專概圍第13項之在基板形成完全高介t常數之薄介電 曰方法’其中該反應性氣體包括HC1、HBr、Cl2、Br2、cxH&、 23 1270140 或CxHyXz’或其中二種或多種氣體之組合。 如申請相制第1_之在基娜成完全高介電常數之薄介電 每之方法，其中該電漿處理又包括在反應性蝕刻處理 全高介電常數之厚介電層。 〖爾“亥疋 上專fr15第1。項之在紐形成完全高介f常數之薄介電 :方法，其中該電漿處理又包括將該完全高介電常數之厚介 曰之邛伤加以改良，然後使用濕式製程以移除已改良之部分。 17· — 包 括 厂種在基板形成含铪之完全高介電常數之薄介電層的方法， 在處理室設置一基板，該基板上形成有一介面層； 厚声ttt之高介電常數材料沈積到至少—最小厚度，該最小 財在上形成 狀在基板職含铪之完全高介電常數之 其中該含銓之完全高介電常數之厚介電層的最 w予度，大約介於30〜200埃。 全高介電常數 法，其中所希望之該含給之完全高介料狀薄 尾層的厚度，大約介於5〜50埃。 專利範圍第17項之在基板形成含給之完全高介電常數之 ι電層的方法，其帽該完全高介料數層薄化又包括經由反 24 1270140 應性蝕刻處理將該沈積之含铪高介電常數層加以蝕刻。 21.如申請專利範圍第17項之在基板形成含铪之完全高介電常數 之薄介電層的方法，其中將該高介電常數層薄化又包括在電漿處 理中將該含铪之完全高介電常數之厚介電層之一部份加以改良， 及使用濕式製程移除已改良之部分。 十一、圖式：
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