TWI263704B - Wiring board - Google Patents

Wiring board

Info

Publication number
TWI263704B
TWI263704B TW093107252A TW93107252A TWI263704B TW I263704 B TWI263704 B TW I263704B TW 093107252 A TW093107252 A TW 093107252A TW 93107252 A TW93107252 A TW 93107252A TW I263704 B TWI263704 B TW I263704B
Authority
TW
Taiwan
Prior art keywords
plated layer
disposed
layer
main surface
metal terminal
Prior art date
Application number
TW093107252A
Other languages
English (en)
Other versions
TW200422438A (en
Inventor
Haruhiko Murata
Kazuhisa Sato
Tomonori Matsuura
Original Assignee
Ngk Spark Plug Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ngk Spark Plug Co filed Critical Ngk Spark Plug Co
Publication of TW200422438A publication Critical patent/TW200422438A/zh
Application granted granted Critical
Publication of TWI263704B publication Critical patent/TWI263704B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
TW093107252A 2003-03-18 2004-03-18 Wiring board TWI263704B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003073767 2003-03-18

Publications (2)

Publication Number Publication Date
TW200422438A TW200422438A (en) 2004-11-01
TWI263704B true TWI263704B (en) 2006-10-11

Family

ID=33398263

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093107252A TWI263704B (en) 2003-03-18 2004-03-18 Wiring board

Country Status (3)

Country Link
US (1) US7067918B2 (zh)
CN (1) CN100405881C (zh)
TW (1) TWI263704B (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006080493A (ja) * 2004-08-12 2006-03-23 Ricoh Microelectronics Co Ltd 電極基板
JP4055015B2 (ja) * 2005-04-04 2008-03-05 セイコーエプソン株式会社 半導体装置の製造方法
US7217656B2 (en) * 2005-05-31 2007-05-15 Texas Instruments Incorporated Structure and method for bond pads of copper-metallized integrated circuits
FI119714B (fi) 2005-06-16 2009-02-13 Imbera Electronics Oy Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi
US7381635B2 (en) * 2005-07-18 2008-06-03 International Business Machines Corporation Method and structure for reduction of soft error rates in integrated circuits
JP2007059485A (ja) * 2005-08-22 2007-03-08 Rohm Co Ltd 半導体装置、基板及び半導体装置の製造方法
KR100744930B1 (ko) * 2006-02-01 2007-08-01 삼성전기주식회사 Ｌｔｃｃ 모듈의 제조 방법
US7960825B2 (en) * 2006-09-06 2011-06-14 Megica Corporation Chip package and method for fabricating the same
TWI471958B (zh) * 2006-09-06 2015-02-01 Qualcomm Inc 晶片封裝結構及其製程
JP5214139B2 (ja) * 2006-12-04 2013-06-19 新光電気工業株式会社 配線基板及びその製造方法
KR100826360B1 (ko) * 2007-04-18 2008-05-02 삼성전기주식회사 반도체 패키지용 인쇄회로기판의 제조방법
US8110752B2 (en) * 2008-04-08 2012-02-07 Ibiden Co., Ltd. Wiring substrate and method for manufacturing the same
DE102008050983B4 (de) 2008-10-13 2023-09-21 Heidenhain-Microprint Gmbh Verfahren zur Herstellung eines lötbaren Mehrschichtaufbaus
JP4758470B2 (ja) * 2008-12-18 2011-08-31 シャープ株式会社 突起電極の形成方法及び置換金めっき液
US8592691B2 (en) * 2009-02-27 2013-11-26 Ibiden Co., Ltd. Printed wiring board
TW201041469A (en) * 2009-05-12 2010-11-16 Phoenix Prec Technology Corp Coreless packaging substrate, carrier thereof, and method for manufacturing the same
KR101070098B1 (ko) * 2009-09-15 2011-10-04 삼성전기주식회사 인쇄회로기판 및 그의 제조 방법
JP5566771B2 (ja) * 2010-05-18 2014-08-06 日本特殊陶業株式会社 多層配線基板
US8492892B2 (en) 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
TWI447864B (zh) * 2011-06-09 2014-08-01 Unimicron Technology Corp 封裝基板及其製法
CN104047041B (zh) * 2013-03-15 2017-04-26 深圳市九和咏精密电路有限公司 一种印刷电路板制备方法
CN105009295B (zh) * 2013-03-29 2017-10-10 富士电机株式会社 半导体装置及半导体装置的制造方法
US9153550B2 (en) * 2013-11-14 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design with balanced metal and solder resist density
US10495521B2 (en) * 2016-04-26 2019-12-03 Kyocera Corporation Sensor substrate and sensor apparatus
CN113170579A (zh) * 2019-02-21 2021-07-23 华为技术有限公司 封装结构及其制备方法
US20210035818A1 (en) * 2019-07-30 2021-02-04 Intel Corporation Sacrificial pads to prevent galvanic corrosion of fli bumps in emib packages
CN112216675A (zh) * 2020-09-11 2021-01-12 中国电子科技集团公司第十三研究所 微组装基板结构及芯片微组装方法
JP7061247B1 (ja) * 2020-12-28 2022-04-28 松田産業株式会社 ニッケル電解めっき皮膜及びめっき構造体

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235139A (en) * 1990-09-12 1993-08-10 Macdermid, Incorprated Method for fabricating printed circuits
US5364460A (en) 1993-03-26 1994-11-15 C. Uyemura & Co., Ltd. Electroless gold plating bath
JP2874088B2 (ja) 1993-03-26 1999-03-24 上村工業株式会社 無電解金めっき浴
JP3317691B2 (ja) 2000-06-19 2002-08-26 日本特殊陶業株式会社 基板の製造方法及びメッキ装置
JP4932094B2 (ja) 2001-07-02 2012-05-16 日本リーロナール有限会社 無電解金めっき液および無電解金めっき方法
US6815126B2 (en) * 2002-04-09 2004-11-09 International Business Machines Corporation Printed wiring board with conformally plated circuit traces

Also Published As

Publication number Publication date
US20040227239A1 (en) 2004-11-18
TW200422438A (en) 2004-11-01
CN1535103A (zh) 2004-10-06
US7067918B2 (en) 2006-06-27
CN100405881C (zh) 2008-07-23

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees