TWI257722B - Package structure of light-emitting diode with electrothermal component - Google Patents

Package structure of light-emitting diode with electrothermal component Download PDF

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Publication number
TWI257722B
TWI257722B TW094124165A TW94124165A TWI257722B TW I257722 B TWI257722 B TW I257722B TW 094124165 A TW094124165 A TW 094124165A TW 94124165 A TW94124165 A TW 94124165A TW I257722 B TWI257722 B TW I257722B
Authority
TW
Taiwan
Prior art keywords
light
emitting diode
thermoelectric
unit
substrate
Prior art date
Application number
TW094124165A
Other languages
English (en)
Other versions
TW200703708A (en
Inventor
Chih-Kuang Yu
Chun-Kai Liu
Ra-Min Tain
Jen-Hau Cheng
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW094124165A priority Critical patent/TWI257722B/zh
Priority to US11/255,915 priority patent/US20070012938A1/en
Application granted granted Critical
Publication of TWI257722B publication Critical patent/TWI257722B/zh
Publication of TW200703708A publication Critical patent/TW200703708A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/645—Heat extraction or cooling elements the elements being electrically controlled, e.g. Peltier elements

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

1257722 九、發明說明： 【發明所屬之技術領域】 切ί發明係有關—種發光二極體封裝結構，應用於以覆晶方 之發光—鋪，制是指—種可增加發光二極 ^成力之具熱電元件之發光二極體封裝結構。 【先前技術】 主遑 Ϊίϊ1 鐘（Lighting Emitting Dk)des; led)是—種由 子：料構成：利用半導體中的電子與電洞結合而發出光 有戸好率之光错的發光元件，由於發光二極體光源具 ^哭北H庙無果、壽命長及省電等特色，因此在照明及 積體ii,ί因為發光二極體⑽裝結構與-般的 杳相间同，其封裝方式及散熱方法也與積體電路不 決的1^=二極體之封裝技術與散熱問題為目前亟待解 主要有兩種，—騎線（_ 所使用之ml另一為復晶（PChip)方式；其中打線方式 ! R ^、、友€阻擋到光路，覆晶方式則可避免此缺點。如「第 光1極=〇’，1^利US6483196為一翻用覆晶結構的發 糸/、使用兩顆錫球凸塊（solder bump) π、12作 為電性連接，但沒有提供散熱的設計。 作法有ΐΓίΓ提出以錫球凸塊作為散熱體（therma制）的 的散熱鰭i將in熱由熱傳導方式傳熱，並由下方 錫球凸塊在發光二極體的覆晶封裝上，僅有兩顆 傳導將發光：極=其餘的錫球凸塊當成散熱體，利用熱 限。九—桎肢產生的熱量導至下方基板，但其傳熱能力有 6 1257722 曰如第2圖」所示，美國專利US6455878是一種使用覆 曰曰方式接合的發光二極體13,利用錫球凸塊層Μ中無電信作 用之錫球凸塊為散熱體15，以傳遞熱量。 〜又、?第3圖」戶斤示，美國專利US6_618則以微機 16上另外製作出凸塊17，覆晶接合後， 空^會被基板16的凸塊17所填充，增加其 热得接觸面積，以提供熱傳量。 夫而ί L卜’如「第4圖」所示，美國專利US6573537是利用 與幽合墊 冷卻方式_電元件，心魏^;、、文果不影而固恶、主動 有效率的冷;能力件了收“光二極體元件更為直接、更 使溫稱動冷卻方式，而能致冷 境才有«功能。若溫度須要高於環 性能提昇有报大的幫助力之用，對於元件的 連續工作，無污染、無動#:、、^^不f使用任何冷卻劑，可 體積小重量輕，應用^ 二木日，哥命長，安裝容易，且 美國專利_32。：:二優勢。 法，其利用鱗姓佳但電導^ —f壯整合熱電元件的散熱方 封裝架内，再將雷射 U衣^ ’先將熱電元件置於 中’其散熱效率非常有限式疋知用外加的熱電元件於封裝結構 1257722 【發明内容】 祺1 - f問題，本發明的主要目的在於提供一種具熱電 途之揣^二極體封裝結構，乃將熱電元件取代f知無1/0用 Φ，兹直^製作並整合於發光二極體封裝結構與應用 # - 提咼發光二極體元件的散熱效率，以及降低發 所7在‘ 正合上的困難與複雜度，並大體上解決先前技術 上述目的，本發騎揭露之具熱電元件之發光 盘其二至少—對熱電單元的熱電元件，發光二極體單元 求凸塊層電性連接，而熱電元件則設置於發光 == 錫球凸塊層，並利用絕緣層於發㈣ …電材料早兀以及η型熱電材料單元，當電流 :之、、電τΜ牛會將熱由發光二極體單元散去，而於發光二極體 單70侧形成冷端、基板一侧形成熱端。 f關本發_舰與實作’兹配合圖示作最佳實施例詳細 €兄明如下。 【實施方式】 第5圖」所示，本發明之第一實施例所提供之具 :電!0f之發光二極體封裝結構，包含有發光二極體單元 、絕緣層40、基板50、錫球凸塊層6〇與兩組熱電元件％。 ” iff狀發光二極體單元3°是藉域長P型發光層 、動每（Actlve Layer) 33、η型發光層34、p型接觸層 35以及η型接觸層36於藍寶石基板（Sapphire)3i上所製成， 且P型發光層32設置於藍寶石基板31上，主動層％與 ，觸層35設置於p型發光層32上，n型發光層％設置於主 動層33上，n型接觸層36設置於n型發光層34上，且p型 接觸層35與η型接觸層36分別連接至正電壓源、與負電壓源， 1257722 入順向電壓’使P型發光層32之電洞與n型發光層34 =主動層33結合而發光。此發光二極體單元3〇是以 式使賴球凸塊層6g反貼接合於基板5g上，且錫球凸 开^ θ之錫球凸塊6〇的形狀並不與限定，其可以是圓形、方 形或疋任何需要應用的形狀。 材料:iH70包“含有ρ型熱電材料單元71以及η型熱電 ^ 上相互乂錯方式排列於發光二極體單元3〇盥基 ίΓ/Ζ球，層6G4G包含上躲層41與下 方，^為當^別叹置於發光二極體單元30下方與基板50上 ^ 提供電路層8〇、81便於佈線，藉由電路 凸塊層60與發光二極體單元3〇、基板％ 型二ϋ: 件70之13型熱電材料單元71與n 可電性互連以及可電性連接至發光二極體 90 5 由毛光一極肢早兀3〇流經熱電元件70 ft基板5G，而在發光二鋪單元3卜側形成冷^ i 光-極^^成^端^用熱電元件70冷端吸熱的功能，將ί 醜生賴轉鱗地輕紐％，並由ί ΐ元俥τΐϊ連接的散熱模組9〇將熱量帶走；或者，可利用埶 一固定溫^溫的魏，將發光"極體單元3G的溫度控制在某' 接著’請參照「第6A〜6E圖丨，Λ太者#办丨+ η丸& 之=二極體封裝結構的製作^程。為本^例之具熱電元件 30盘^第6A〜6C圖」所示，顯示於發光二極體單元 兩者同^絕與電路層80、81之過程，:於 作先，在發光二極體單元30表面鍍上玻璃保= 作為4緣層41 (第6Α圖）’以提供密封保護並防 1257722 思、H ’然後’在上絕緣層41之錫球凸塊層60及熱電材料 70接墊位置上開出導孔，而熱電材料70的導孔並不穿透上絕 緣層41 (第6B圖），並在上絕緣層41開出熱電元件70的線 路後，再濺鍍上如鉻-銅_金等之多層金屬薄膜(通稱為凸塊底層 金屬（UBM，Under Bump Metallurgy ))，而形成電路層 go (第 6C圖）’以提供黏著、擴散障礙、增進銲錫潤濕與防止氧化等 功能，隨後，再將錫球凸塊層60與熱電材料7〇以覆晶機植球 於基板50上各個接墊位置（第6D圖），並經由精密對位，將 ，光一極體單元30與基板50上的接墊位置接合（第6£圖）， 最後，以回焊（reflow)將錫球凸塊層6〇固定， 此具熱電元件之發光二極體封裝結構。 其中，熱電元件70可以使用微機電加工、半導體力、 機械加工，或是其他加玉製作方絲製作，減電 法Γ利用覆晶方式、網板印刷或其^方法組 熱件70製作於錫球凸塊層60上的方法，則可以 鍍^putter)、蒸鐘—〇rati g 其他可做域電元件70在錫球凸塊層6G上面的^mg)或疋 4ft S 第7圖」所示，本實施例之發光二極體封f έ士 鏡ti7 ’以提高發光二極體之整體亮ί艺 層62與另」裝，^方更可藉由錫球凸塊 熱電元件73設置f 第9圖」所示，將多對 #，球凸塊層63内，來提高整體散熱的效果。 9ι之連接亦極體封裝結構與另-元件 二極體封裝結構底端也^由弟11圖」所示，發光 件。 而也J稭由數個接腳92來結合於其他元 内，可以開設有散熱通道 如「第12圖」所示，於基板50 10 1257722 (thermal vias)51，用以提昇基板5〇的導熱能力，而可更快速 的將熱帶至底部的散熱模組90。如「第13圖」所示，在這些 散熱通道Μ内，以電鍍、塊材置入、流質注入等方式將軌^ =製作於散熱通道51内，在基板5G _成第二組(級)的敎 t 所示，包含# P型熱電材料單元52以及Π型熱電 而丄气面，請參閱「第14圖」’ 板50加以省略， t 光二極體連同熱電單元直接襄設於散熱模組9〇 ，：：表面有一層經過陽極處理之絕緣層(薄膜或厚膜皆 制製作方法可制如氧化、陽極處理等，此 ^觸熱阻(C〇ntaCtreSi缝e)，提昇熱電元㈣ 7 >此同日守’散熱模組90可以為熱管93的形式，袁閱「第 ^」，熱管93與熱電單元連接的一側，其表面有一層絕= 可）’絕緣層的製作方法同樣可如氧化、陽極 々制在特二ίτΐ可ί ί降低接觸熱阻，同時亦可將熱端溫度 f提昇熱電元件的工作效能。當然，請參閱 弟16圖」，也可將熱管93體積整個放 熱鰭片94，更增加散熱效果。 夕卜礼3有放 而非整： 的困^者降轉統熱f ^件與g #封裝整合上 阻，進而^元__題’以及減少接觸熱 光二極體性與可靠度，藉此可因應未來發 限定ίί 佳倾綱露如上，雜並非用以 " <何热白相像技藝者，在不脫離本發明之精神和 1257722 當可作些許之更動與潤飾，因 芗之中請專利範圍所界定者為準 ί ^ ’ ί'ΐ前技#之發光二極體結構之示意圖 第3 ΐ ’ ^前技術之發光二極體結構之示意圖 ^ϊ，ίί!技術之發光二亟體結構之示意圖 圖係先則技術之發光二極體結構之示意 圖’係本發明之實施例之具熱電元件之發·光-朽辦去 構之示意圖； 卞又嗌光一極體封裝結 之實_之具_林之發先二極體 之縣二極體封 【主要元件符號說明】 10 " 13發光二極體 17 19 20 30 31 32 33 34 35 36 37 11 ' 12'15、18、61 錫球凸塊 14 Λ 60 ' 62、63 錫球凸塊層 16 基板 凸塊 η型接合墊 Ρ型接合墊 發光二極體單元 藍寶石基板 p型發光層 主動層 η型發光層 Ρ型接觸層 η型接觸層 鏡體 12 1257722 40 絕緣層 41 上絕緣層 42 下絕緣層 50 基板 51 通孔 52 P型熱電材料早元 53 η型熱電材料單元 70、 73 熱電元件 71 Ρ型熱電材料早元 72 η型熱電材料早元 80、 81 電路層 90 散熱模組 91 元件 92 接腳 93 熱管 94 散熱鰭片
13

Claims (1)

1257722 十、申請專利範圍： h —種元叙發光二鋪封I轉 一發光二極體單元； 亍已3有· 一蜿緣層，設置於該發光二極體單元· 二絕緣與該發光二極體單元設置； 錫球凸塊層（solder bump丨），讲土 體單元與該基板間，將該發光二極體光二極 以及 兀仵與该基板電性連接; ΐί^ΙΙ：^^^ ^具熱電元件之發光二極體封果 之間，耠供該發光二極體與該基板可透 ς =板 連接、該熱電元件之Ρ型熱電材料;性 之iiit、以及該p型熱電材料單元與該n型熱電材ίί 該發光二極體單元與該基板，以形成該冷端 3.如申請專機㈣1項所述之具熱電元件之發光二極體封壯 結構，其中該Ρ型熱電材料單元與該η型熱電材料 ^ 相互交錯方式排列連線。 以节以 4.如申請專利範圍第1項所述之具熱電元件之發光二極體 結構’其中該基板下方更包含有一組熱電元件。 5·如申請專利範圍第1項所述之具熱電元件之發光二極體封壯 結構’其中該基板内設置複數個散熱通道。 、 6·如申請專利範圍第5項所述之具熱電元件之發光二極體封妒 結構’其中該散熱通道内更包含有另一熱電單元。 、衣 7· —種具熱電元件之發光二極體封裝結構，係包含有： 14
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