TWI317162B - - Google Patents

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TWI317162B
TWI317162B TW095102097A TW95102097A TWI317162B TW I317162 B TWI317162 B TW I317162B TW 095102097 A TW095102097 A TW 095102097A TW 95102097 A TW95102097 A TW 95102097A TW I317162 B TWI317162 B TW I317162B
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Taiwan
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electrode
led
layer
eutectic
flip
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TW095102097A
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TW200729438A (en
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Huga Optotech Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

1317162 > ^ 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種發光二極體（Light Emitting Diode, LED)之封裝結構，尤其是關於一種具有高散熱效率之覆 晶式LED封裝結構及其封裝方法。 « ' 【先前技術】 鲁 led光源由於具有體積小、耗電量低、使用壽命長等 特性，在可預見的未來，將可取代目前燈泡或日光燈源等 照明設備或其他顯示裝置之發光源，而成為最重要之發光 元件。然而’為提高發光源之整體亮度，勢必要提高發光 功率或增加LED裝設之數目或密度，但如此設置將大幅 ' 增加LED光源之產熱量，若該些熱量無法儘速導出，將 - 嚴重影響led之發光亮度，同時加速LED之劣化狀況而 減短使用壽命。
Φ 為改善LED之散熱效率，曾有如第—圖所示之LED 封裝結構。該習知創作中，1^〇1〇係藉由共晶（61^(：如） 結合方式形成一共晶層30而與铭基板2〇相接合。铭基板 . 20表面預定區域内分別形成有一絕緣層21，該絕緣層21 表面再形成一銲墊22’各銲墊22則分別與第—電極u與 第二電極12以導接線23電性相連接。前述方式雖然可藉 由共晶層30將LED 10所產生之熱量以傳導方式，透過鋁 基板20傳出來增加散熱效率，但因藍寶石層13之阻礙， 致使散熱效果不如理想，且該種封裝方式，第一電極u 5 1317162 與第二電極12皆位於LED 1〇發光層之上方，將遮蔽部分 的出射光’對於LED 10之發光面積有著相當程度的縮 減’而影響其發光效率。 ’’ 因此，為避免前述缺失，即產生如第二圖所示以覆晶 (flip chip )接合方式進行封裝之創作。其中，1 〇係 倒置後與印刷電路板4〇相接合。印刷電路板4〇係於表面 預定位置分別設有一銲墊41，銲墊41並與印刷電路板仞 中之導接線42電性相連接。 1〇接合日夺，係藉由金屬 凸塊43分別將第一電極u與第二電極丨2與銲墊4丨相連 接。以此賴方式雖可改善前述光麵所產生發光效率減 少之缺點’但LED 10所產生之缝卻僅可透過金屬凸塊 43傳導至印刷電路板4〇，一方面傳導之接觸面積小，一 方面印刷電路板40之導熱率有限，並無法使LEDl〇整體 散熱效率能財效改善’因而仍存有前述LED劣化與因 受高溫而使光度縮減之缺失。 【發明内容】 • ^改善1知封裝時發光效率之不足，同時提升
’ LED之散熱效率’本發明將提供〜種以覆日日日技術將LED 以共晶方式與導熱基板相結合之封裝結構與封裝方法，使 LED發光部分不受侷限，㈣轉最佳之發級率，並同 日杨，所產生之熱量續大之接觸㈣與熱傳導效率，傳 導至高導熱餘之導祕板上，俾能大巾談高LED之散 熱效能，使LED避免處於高溫之下，而增加哪之使用 6 、1317162 壽命，並能進一步提高LED之發光亮度。
本發明覆晶式發光二極體封裝結構’包括：一導熱基 板，該導熱基板表面於―預定區域_成有—絕緣層，該 絕緣層表®並形成有—銲塾；以及—LED，該led係呈 覆曰s方式接合於該導熱基板上，該LED包括有一第一電 極與-第二電極，該第―電極與該導熱基板間共晶結合有 -共晶層而電性相連接，而該第二電極則與該銲墊電性相 連接。共sa層可先於該導熱基板上該第—電極相對應處鑛 上有鍵金層後’再與該第—電極加熱共晶所形成丨其亦 可於該導熱基板上該第一電極相對應處與該第一電極間 夾設-金片’再加熱共晶所形成。#中，該導熱基板係一 鋁（A1)板、銅（Cu)板、氮化鋁（A1N)或其他高導熱 係數之金屬或介質層’但並不僅限於此。 藉由本發明之封裝結構，LED發光層所發散之光線不 會受到電極之遮蔽，故有較佳之發光效率。且其所產生之 熱能得藉由較大接觸面積之共晶層直接導出，而無庸再如 習知透過導熱係數較差之藍寶石層傳遞，故能迅速將熱能 傳導至高導熱係數之導熱基板上，使lED溫度能夠儘= 降低，因而使得LED不但能夠維持較佳之發光致率，= 有最佳之導熱散熱效率。 ” 以下將配合圖式進一步說明本發明的實施方式，、 所列舉的實施例係用以闡明本發明，並非用以限定本 之範圍，任何熟習此技藝者，在不脫離本發明之精神^ # 圍内，當可做些許更動與潤飾，因此本發明之保護〜° = 7 1317162 雜附之巾請專利範®所界定者為準。 【實施方式】 "月’、閱第二® ’該圖係本發明實施例之示意圖。本發 “日日式&光—極體封裝結構，包括-LED 50與-導熱 基板60，該LED 50係以覆晶方式封裂於導熱基板6〇上。 LED 50 ’其包括一第一電極51與一第二電極52，第 • 一電極51與第二電極52係位於LED 50表面之同側。該 一包極可利用物理蒸鍍（Physical Vap〇r Dep〇siti〇n，pVD ) 方式鍍上鈦（Τι)、鋁或金（Au)等金屬層，再經金屬融 合所製成。在一般氮化鎵（GaN) lED晶粒上，第一電極 51可與p型氮化鎵（p-GaN)層電性相連結接而為p型電 極，而第二電極52則可與n型氮化鎵（n+GaN)層電性 相連結接而為N型電極’電極設置方式於此僅為例示，並 不限於前述。此外，為配合本發明覆晶接合方式，第一電 • 極51於蒸鍍形成時可擴大其面積並配合厚度之調整，使 將來共晶接合時，第一電極51與第二電極52能夠緊密接 • 合於導熱基板60上，並同時有較大的接觸面積。藉由第 ， 一電極51與第二電極52與電流之導通，即可於LED 50 内產生亮光。 導熱基板60，其係一高導熱係數之鋁板（231 W/m.K)、銅板（385 W/m.K)或氮化鋁（320 W/m.K)板， 但並不僅限於此，其導熱係數於室溫下可達100 W/m.K以 上者為較佳。導熱基板60於本發明覆晶結合方式中，除 8 1317162 • ^導熱散熱功能外，尚須能夠導電，故該導熱基板6〇亦 需―導電性佳之材質，前述數種材質中則以銘板、銅板為 較佳。導熱基板60與LED 50接合前，先於導熱基板60 ，面上與第二電極52相對應之預定定義區域内形成一絕 - 緣層61。絕緣層61可利用二氧化矽（Si〇2)或氮化矽 、 （Sl3N4)以化學氣相沈積（Chemical Vapor Deposition, CVD)沈積於導熱基板6〇表面，而沈積所利用之材質與 • 方式並不僅限於前述。而後，再於絕緣層61表面形成一 =屬材質的銲墊62，作為與第二電極52電性相連接之介 質層。由於第一電極51已與具導電性之導熱基板6〇電性 相連接，故無須進行打線，而第二電極52則可藉由與銲 墊62之電性連接，打線於銲墊62上，而形成電流導通之 ' 狀態。 ^ LED 5〇以覆晶方式接合於導熱基板60時，第二電極
52可與銲墊62電性相連接，而第一電極51則與導熱基板 φ 相對應表面間同時共晶接合有一共晶層63。因此，LED 5〇所產生之南熱可經由第一電極51並透過共晶層63直接 傳導至具高導熱係數之導熱基板60上，迅速將熱量加以 散逸，而能夠維持LED 50適當的溫度。相較於習知技術， 利用覆晶方式封裝除可使LED 50有較大發光面積外，最 重要的是可將LED 50發光層所產生之熱量直接由較接近 之共晶層63導出，而無庸再如習知透過導熱係數較差之 藍寶石層53，故能明顯提升其導熱性。另一方面，透過大 面積共晶層之接觸傳導，亦能增加導熱速率，而大幅改善 9 *1317162 ， 金屬凸塊導熱速率不足之缺點。 接人二Β曰層30形成之方式請參閱第四圖與第五圖。共晶 則可先於導熱基板60上該第一電極η相對應處鐘上 -此又金層631，再與該第—電極51於適當溫度處理下進 晶接合。此外，其亦可於導熱基板60上該第-電極 、 —相對應處與該第一電極51間夾設一金片632 (請參閱 第五圖），再於適當溫度處理下進行共晶接合。當第一電 • 極51具鋼金屬層時’則可形成一銅/金或銅/金/鋁之共晶層 63 °共晶接合所使用之金屬與方法，並不限於前述，但以 導熱係數較高之金屬為較佳。 【圖式簡單說明】 第一圖係習知LED封裝結構之示意圖。 第二圖係習知覆晶式LED封裝結構之示意圖。 ^ 第三圖係本發明實施例之示意圖。 第四圖係本發明封裝方法實施例之示意圖。 第五圖係本發明另一封裝方法實施例之示意圖。 【主要元件符號說明】
10 LED 11 第一電極 12 第二電極 13 藍寶石層 1317162 20 鋁基板 21 絕緣層 22 銲墊 23 導接線 30 共晶層 40 印刷電路板 41 銲墊 42 導接線 43 金屬凸塊 50 LED 51 第一電植 52 第二電極 53 藍寶石層 60 導熱基板 61 絕緣層 62 銲墊 63 共晶層 631 鑛金層 632 金片

Claims (1)

1317162 、申請專利範圍： 、一種覆晶式發光二極體封裝結構’包括 一金屬導熱基板，該金屬導熱基板表面於一預定區 域内形成有一絕緣層，該絕緣層表面並形成有一銲 墊；以及 一 LED，該LED係呈覆晶方式接合於該金屬導熱 基板上’該LED包括有一第一電極與一第二電 極’該第一電極與該金属導熱基板間共晶結合有一 以至少含有銅/金共晶之共晶層而電性相連接，而 該第二電極則與該銲墊電性相連接。 2、 如申請專利範圍第1項所述之覆晶式發光二極體封 裝結構’其中該金屬導熱基板係一鋁板。 3、 如申請專利範圍第1項所述之覆晶式發光二極體封 裝結構’其中該金屬導熱基板係一銅板。 4、 如申請專利範圍第1、2或3項所述之覆晶式發光 二極體封裝結構，其中該絕緣層係一二氧化矽層。 5如申5月專利範圍第i項所述之覆晶式發光二極體 封裝結構，其中該共晶層亦可為銅/金/铭共晶。 12
TW095102097A 2006-01-19 2006-01-19 Package structure of flip chip light emitting diode and the package method thereof TW200729438A (en)

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TW095102097A TW200729438A (en) 2006-01-19 2006-01-19 Package structure of flip chip light emitting diode and the package method thereof

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Application Number Priority Date Filing Date Title
TW095102097A TW200729438A (en) 2006-01-19 2006-01-19 Package structure of flip chip light emitting diode and the package method thereof

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TW200729438A TW200729438A (en) 2007-08-01
TWI317162B true TWI317162B (zh) 2009-11-11

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478319B (zh) * 2010-07-20 2015-03-21 Epistar Corp 整合式發光裝置及其製造方法
TWI495160B (zh) * 2011-12-15 2015-08-01 Ritedia Corp 覆晶式發光二極體及其製法與應用

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473299B (zh) * 2011-12-15 2015-02-11 Ritedia Corp 覆晶式發光二極體及其製法與應用

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478319B (zh) * 2010-07-20 2015-03-21 Epistar Corp 整合式發光裝置及其製造方法
TWI495160B (zh) * 2011-12-15 2015-08-01 Ritedia Corp 覆晶式發光二極體及其製法與應用

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