TWI250834B - Method for fabricating electrical connections of circuit board - Google Patents

Method for fabricating electrical connections of circuit board Download PDF

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Publication number
TWI250834B
TWI250834B TW093133433A TW93133433A TWI250834B TW I250834 B TWI250834 B TW I250834B TW 093133433 A TW093133433 A TW 093133433A TW 93133433 A TW93133433 A TW 93133433A TW I250834 B TWI250834 B TW I250834B
Authority
TW
Taiwan
Prior art keywords
layer
circuit board
electrical connection
metal
connection end
Prior art date
Application number
TW093133433A
Other languages
English (en)
Other versions
TW200616519A (en
Inventor
Shih-Ping Hsu
Sao-Hsia Tang
Chao-Wen Shih
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093133433A priority Critical patent/TWI250834B/zh
Priority to US11/060,497 priority patent/US7174630B2/en
Application granted granted Critical
Publication of TWI250834B publication Critical patent/TWI250834B/zh
Publication of TW200616519A publication Critical patent/TW200616519A/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0391—Using different types of conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0574—Stacked resist layers used for different processes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

1250834 九、發明說明： 【發明所屬之技術領域】 户2 θ係有關於—種電路板之電性連接端之製法，尤 高度及尺寸之全屬、卓H 連 同時形成不同
Ji屬連接材料的製作方法。 【先前技術】 r ρπλ Γ來冑'己型電腦、行動電話、個人數位助理 數位相機等電子產品的體積越來越小，工 亦要求越來越快’這些曰新 、: 小型化、由於越來越多的產品設計趨向於 不=大功能，因此，覆晶技術的應用範圍將 -電子穿置的晶片封褒技術。同時為提升該 二：之电性品質，即需於其中設置有例如電阻、電 奋、电感等被動元件，而該些被動 黏著技術_丁）而接置於電路板上，導;^木用表面 面黏著型金屬連接元件並存於電路板>上致 銲錫材料高度及尺寸並不相同。 1兩者所形成之 如第1圖所示，覆晶技術係將複數個金屬凸塊 成於晶片13之電極銲墊12上，以及數 y 預銲錫凸塊14形成於電路板]6> 、干料所4成的 〜风於私路板16之電性連接墊丨5 足以使該預鐸錫凸塊14溶融之迴銲溫 預= 凸塊:4迴鲜至相對應之金屬凸塊11，從而形二 =後復使用底部填充材料18以實現晶片與電 合’確保晶片13與電路板16兩者之電性連接的完=與 17934 6 1250834 可靠性。 其中該預銲錫凸塊係提供半導體積體電路晶片與電 路板之間的機械接合、電性連接的作用，同時於同一電路 板上，亦可能會同時電性連接不同之表面黏著半導體元 件，例如被動元件，藉以提供電子裝置較佳電性品質。然 而對應該不同之表面黏著半導體元件，電路板上之電性連 接墊需要鍍上不同高度及尺寸之銲錫，從而形成不同高度 之電性連接端，以與該具有不同類型之表面黏著半導體元 件之相配合電性導接。 目前常用於電路板之電性連接墊上形成銲錫材料的 製作方法為模板印刷技術。如第2圖所示，其係於一完成 電路佈線之電路板20上形成一防銲層21，並外露出多數 電性連接墊22，以令一具有複數個開口 23a之模板23置 於該電路板20之防銲層21上，透過該些開口 23a以在電 性連接墊22上形成銲錫堆（未圖示）。其可採用滚輪24 或喷灑方式，使銲料在開口 23 a内堆積，於該模板23移除 後，形成銲錫堆。復進行迴銲製程，使電性連接墊22上之 銲錫堆固化形成銲錫元件。 再者，後續將該電路板與半導體晶片及被動元件等進 行封裝製程時，為提供該電路板得以與外界電子裝置電性 連接，必須於該電路板底面植設複數銲球，而為提供銲球 有效接置其於電路板上，即須於該供接置銲球之電路板電 性連接墊上預先形成供接置銲球之銲錫材料。 然而，半導體晶片之微型化發展趨勢使得半導體之封 7 17934 1250834 裝技術亦隨之改變，以滿足不斷減小的晶片具有更多輸入 輪出端。惟前述變化將縮小晶片承載件之面積，而增加晶 片承載件上電性連接墊之数量，唯有縮小電性連接墊之尺 寸人間距，才能適應晶片發展之需求。然電性連接墊之減 J使传杈板之開口必須隨之減小，如此，不僅因模板開發 不易而造成该模板之製造成本增加，更將因模板之開口细 1而導致銲錫材料難以穿過，造成製程上之瓶頸。再者， 吁錫材料之生成精度除了要求模板印刷技術中之模板尺寸 確外’尚須確認模板印刷之次數與清潔問題。因為 Τ 7料具有黏度（Vlscosity)，而當印刷次數愈多，殘留 :::孔壁内之銲錫材料即相對愈多，導致 =之銲錫材料數量及形狀與設計規格不合，因此 ^ 栻清潔，否㈣、Λ 後即必須進行模板之擦 * μ㈣產生銲錫材料之形狀、尺 w成製程之不便與可靠度之降低。 年w 為角牛决上述弊端，遂有命 銲錫材料之技術。士也、木用甩鍍方式於電路板上形成 ^ ；L 口我國公告編號第508987號所揭^ 有機電路板上進行r日如 現所揭不之於 有電性連接墊之有機：鑛广錫之方法」’其主要係於-包含 以 形成有開口以顯露出電路板广又編緣保護層，並 路板上形成—薄金❹，、—，電性連接墊，接著在該電 之電錢阻層，以外^ j於該薄金屬層上形成具有開口 便電鑛形成鋒錫材料 電性連接墊上之薄金屬層， —般電鍍銲錫材料必 且 /、4過電鑛阻層之開口形成， 17934 1250834 其高度係藉由電鍍阻層 接墊上植設預缚錫凸# 由於在電性連 置之銲錫元件：者之=錫=黏著型鲜錫元件與供銲球接 習知技術中需4=::?度及尺寸要求不相同，因此， 惟分別形成高度及尸h n 的知錫材科。 0± π « ., 寸不同之銲錫材料時，存在增加製 日才間及成本之弊端， 衣柱 層及導電層，可能致传/1设、移除電鑛阻 路板之良率。此外之銲錫材料鬆動，降低電 程中的常W㈣;:料導體積體電路製 左右，因此需要採用心^ 光阻層的厚度在25_1 要知用黏稠度大的光阻膠體、 以及波長較長的暖古她^ 竹沐的q知機 铲m , 枝’導致製程成本提高。故，分別電 鍍形成電性連接端不僅拎刀刎电 時亦會降低電路板良率。衣私"間’提面製程成本，同 馨於前述習知技術之弊 連接端尺寸之限制以及鲁^一极板印刷技術形成電性 連接端所產生降低良率、辦加制_^刀-人电鍵形成電性 缺失，日义τ干 日加衣耘日守間、提高製程成本等痛 法種能夠形成微型電性連接端的製作方β 法，同時在t路板均 /作方 ，間、“電路板良率、降低製程成本。 【發明内容】
鑒於以上所述習知技術之缺點，本發明之主 於提供-種電路板之W 之上、下表面形成電性連接^而之衣法，俾件以在電路板 本發明之再—目的係提供一種電路板之電性連接端 17934 9 1250834 之製法，俾可同時於電路板上形 連接端。 尺寸不同之電性 本發明之又-目的係提供一種電路板之電性 避免習知電鑛形成電性連接端多次敷設、移二 =層及導電層所導致良率降低及製程步驟與成本增加; ^明之另-目的係提供—種電路板之電性連接端 1’=習知模板印刷技術形成電性連接端尺寸之限 制費用提鬲及製程技術上之瓶頸。 神、查^成上揭及其他目的，本發明揭露—種電路板之带 連接端之製法，主要係包括提供 电 電性連接墊之電路板；於表㈣成有後數 &^$路板上形成-絕緣層，且兮 、、、巴、、彖層具有複數個開口以外露出該些電性連 ^ 緣層及對應該開口處表面形成一導，；&絕 成第一阻層，且該第—阻層料電層上形 該些電性連接墊上之導電層:、：=°以外露出對應 連接墊上形成筮人瓸备曰 丁电鍍衣耘，在該些電性 ，墊為成卜金屬連接層；於該第_阻層及 口處表面形成第-阳展 q # — 八ί應開 第二阻層具有複數個開口， 1::Γ分:性連接塾上之第一金屬連接層；以及進行 电鍍製程，以在外霞於兮筮—阳昆 _ ^ 点筮入严* 。弟一阻層之弟—金屬連接層上形 成U連接層。其後復可移除該第：阻層 及未為該金屬連接層所覆蓋之導兩 ^層 籽制立 各 ^复皿之¥电層。之後，復可進行迴 :衣程以在該電輯接墊上形成金屬 者之金屬連接元件以及供接置鲜球之金屬連接元件表面勒 17934 10 1250834 要係ΧΓΤ揭露之電路板之電性連接端之製法主 於兮第二之私11連接塾上先形成第一圖案化阻層，以 、口义乐阻層之開口電鑛形成褚6丄士 層，亦即先在電路板之電性連接==的第—金屬連接 低的金屬連接材料；然後，形成第形成相對高度較 外露出部分之第一八严、φ拉成弟一圖案化阻層，並選擇 之全屬凸❸射/蜀連接層（例如後續供覆晶電極銲墊 料之高度要高於供表面黏著之金屬=於:些:屬連接材 之金屬連接元件，因此需再透過第70及供接置鮮球 金屬連接材料，待移除阻層之後，:阻層=開口繼續電鎮< 迴銲，藉以形成言卢 行5亥金屬連接材料之 可避免羽4 4又5之书性連接端。藉此，本發明亦 义免白知琶鍍技術先後形成電性 亦 除阻層及導電層對電性連接端 接4口夕二人敷設、移 以及製程步驟與成本增加等、二’降低電路板之良率 印刷技術形成電性連接端尺寸之限可避免習知模板 術上之瓶頸。 、費用提南及製程技 【實施方式】 痛 以下係猎由特定的呈A y丨Α、， 式，熟習此技藝之人士可由:ϋ =明本發明之實施方 暸解本發明之其它優點與功效:曰/斤揭示之内容輕易地 的具體實施例加以施行或應用，本其他不同 可基於不同觀點與應用’在不t孛離本發;二;=節亦 種修飾與變更。 A月之精神下進行各 請參閲第3輪’輪發明之電路㈣性連接 17934 11 1250834 端=製法流程示意圖，同時配合第从至41圖之製程剖面 不思圖，藉以説明本發明之實施態樣。 干於步驟S卜首先提供表面形成有複數電性連接塾彻 之，路板401 (如第4A圖所示）。該電性連㈣4〇3可例 =括有供與覆晶電極鮮墊之金屬凸塊相接的金屬連接凸 球^墊、用於與被動元件連接的表面黏著鲜塾以及用於植 墊之#敗& , , ^ 下表面均具有琶性連接 用之電路板之電性連接端之製法亦可 另’該電路板4G1表面及内部可 :;有複數導電線路(未圖示)，關於電路板形成導電線路 ^電性連㈣之製程技術Μ，乃業相周=路 :再明之重點，為避免模构本發明之技術特徵故 於步驟S2’接著在該形成有電性連接塾彻之電 上形成—圖案化絕緣層405 (如第4β圖所示）。㈣ 、，彖層405可採用印刷、旋塗或貼 405 ^ 手万式形成，且於該絕 = 405中形成m數個開口術，以外露出該 < =其成中該些開，可透過曝光、顯編射= 寺技術形成。另該絕緣層彻可為拒銲材料 决 =阻止後續製程之金屬連接材料黏附於電路板4〇1=性 、，接：403外’導致導電線路短路而降低 二 =猎由開口限制金屬連接材料僅形成於電性連接塾^之 於步驟S3,在該絕緣層405及其對應開口 407處表面 17934 12 Ϊ250834 形成一導電層409 (如第4c圖所示） 鋼、錫、鎳、鉻、鈦、铜·鉻合金並^^層彻可由 程實際需要，形成兩層以上之金 冓成，可根據製 分子材料，而該導電層4Q9主要作“==導】性高 電路傳導路徑。 、书鍍衣私所需之 於步驟S4,在該電路板4〇1之導電芦 化之第一阻層4H (如第4D圖所示）。兮曰 形成圖案 採用印刷、旋塗或貼合等方切 "弟—阻層川可 等光阻材料，以便、雨j 吏用乾膜或液態光阻 予九阻材枓’以便通過曝光、顯影等 ==開口 413外露出該電路板4〇1覆蓋有=〇: 之Γ置塾403 ’限制後續電鑛製程形成金屬連接曰材料 於步驟S 5，進行雷辦制避士 彻之電性連接塾403上;:第八在/些覆蓋有導電層 疋设上形成弟一金屬連接 ==電:前形成之導電層_作為電 連接材料。;二 並古疮、去心回度由繞緣層405控制， 〃同X彳相對高度要求較低之表面黏著銲墊和銲 二之i屬連接材料高度的要求。該金屬連接材料可選自 二二、銀、銅、鉍、銻、鋅、鎳、錯、鎂、銦、碲、金 以叙所構成之組群之元素的混合物所構成之合金。 卜开/^驟S6’復於該第一阻層411及其對應開口 413處 、…：二阻層417,且第二阻層417具有複數個開口 419 1路出部分電性連接墊403之第一金屬連接層415(如第 17934 13 1250834 :F圖：示)。該第二阻層417係可為乾膜或 =料，並採用印刷、旋塗或貼合等方式形成 曝先、顯影等方式形成開口 419。該第二阻層417之開口 工=於例如後續將與覆晶電極銲塾之金屬凸塊相接 後::電性連接墊，以便透過該開口 可供 金屬連㈣料，滿足金㈣接 晷、… 層覆盍住金屬連接材料高度 要求較低之例如表面組裝銲墊及銲球墊之第—阻層開口 I:止後續製程繼續增高該些已達到高度要求:金屬連 於步驟S7，進行電鍍製程，在該些 川之電性連接墊彻之第—金屬連接層化上^阻層 第二金屬連接層421(如第4G円 电鍍形成 开…道。 弟圖所不）。電鍍製程藉由先前 門：:=409作為電流傳導路徑，在第二阻㈣之
、内$鏟心金屬連接材料。電鑛所需之電 路#可通過先前形成之導電 /；，L 形成另-導電層，本實施例通過或者於/驟％之前再 …際製程可依據需要增加導電層 ： 417控制第二金屬連接層421之高 座：弟-阻屬 性連接端高度不同之趨勢。 & 、應電路板上電 於步驟S8，移除該第一阻層4n、 所覆蓋之導電層彻(移除 「阻層417及其 本實施例在電路板4〇1上具有则所示）。 而實際製程可依據實際需 ：電性連接端’然 把據笔性連接端之高度需 17934 14 1250834 再通過增加阻層從而逐步增高電性連接端之高度。 #刹?^驟S9 ’右該金屬連接材料為銲錫時，則可進行迴 二:程杜形成金屬連接凸塊423、表面黏著銲墊上之金屬 -425與*球墊上之金屬連接元件427(如第41圖所 屬連接材料熔融溫度條件 ^^層Μ5〆21之金 材料經遊銲而在該: = 程’使金屬連接 屬連接元件。—^生連接墊彻上固化形成所需之金 因此’本發明所揭霖帝 要係在電路板之電性連 =上：=，之… -阻層，俾於第一圖宰化阻：广緣層及圖案化之第 第-金屬連接層，其形成“=二電鑛形成預定高度的 及大小控制;然後，=:Γ::由:絕緣層厚度 接墊上之第—全屬連接s 1擇外露部分形成於電性連 孟屬連接層，以透過第二阻層 屬連接师卿分第-金屬連接層上形成第::】 - 門同日^由弟—阻層覆蓋無需增高金屬連接材料之第着 ， 其餘弟一金屬連接層，在移除阻声德， 進订迴銲便可在電路板之電性連接墊 11層後’ 同之金屬連接元件，從而，^及尺寸不 高度不同的電性連接端，有效縮』成 =避：習知電鑛技術先後形成電性連接端因多次敷ί發 =除阻層及導電層對電性連接端之損傷，降低電^二 以及製程步驟與成本增加等問題，亦可避免f知模㈣ 17934 15 1250834 費用提高及製程技術 刷技術形成電性連接端尺寸之限制 上之瓶頸。 上述實施例僅為例示性爷 崎^ 「玍况明本發明之原理及其功 .^ ^ ^ 任何熱習此項技藝之人士均可 在不延背本發明之精神及笳_ 勺了 盥變化。^ + 對上述實_進行修傅 〆、化 口此’本發明之權利你1々々闰 ^ 奎4：丨》 隹不J保護摩巳圍，應如後述之申士主 專利範圍所列。 、心〒％ 【圖式簡單説明】 第1圖係-種習知覆晶^件之剖面示意圖； 模板印刷技術在基板之電性連接塾 ，尤積金屬連接材料之剖面示意圖； 第3圖係本發明之電路板之電性連接端之製法之流程 不意圖；以及 者第4A至41圖係本發明之電路板之電性連接端之製法 只知例之剖面圖。 【主 要元件符號說明 11 金屬凸塊 12 電極鲜塾 13 晶片 14 銲錫凸塊 15 電性連接墊 16 電路板 17 銲錫接 18 底部填充材料 17934 16 1250834 20 電路板 21 防銲層 23 模板 23a 開口 24 滚輪 S1，S2，S3，S4，S5，S6，S7，S8，S9 401 電路板 403 電性連接墊 405 絕緣層 407 絕緣層開口 409 導電層 411 第一阻層 413 第一阻層開口 415 第一金屬連接層 417 第二阻層 419 第二阻層開口 421 第二金屬連接層 423 金屬連接凸塊 425 金屬連接元件 427 金屬連接元件 步驟 17 17934

Claims (1)

1250834 十、申請專利範圍： h 一種電路板之電性連接端之製法，係包括： 提供表面具有複數電性連接墊之電路板，且該電路 反上形成有具複數個_ 口以夕卜露出該電性連接墊之絕 緣層； 於該絕緣層及其對應開口處表面形成導電層； 於該導電層上形成第一阻層，該第一阻層具有複數 個開口以外露出該電性連接墊上之導電層； —進行電鑛製程，在該些電性連接塾之導電層上形成 弟一金屬連接層； 入"於該第一阻層及其對應開口處上形成第二阻層，並 亥弟二阻層形成有複數個開口，以外露出部分電性連 接墊上之第一金屬連接層；以及 進行電鍍製程，以在該些外露於該第二阻層之第一 金屬連接層上形成第二金屬連接層。 2.=請專利範圍第丨項之電路板之電性連接端之製法， ^包括移除該第-、第二阻層及為該第一、第二阻層所《 復盖之導電層。 々申明專利範圍第2項之電路板之電性 該第-、第二金屬連接層進行迴銲該 电生連接墊上形成金屬連接元件。 4.=請專利範圍第3項之電路板之電性連接端之製法， ς，/金屬連接元件係可供接置半導體晶片、被動元 件及焊球。 17934 18 125〇834 6 2請專利範圍第1項之電路板之電性連接端之製法， ^ ，及電性連接墊僅形成於電路板之一表面。 其I二專利乾圍第1項之電路板之電性連接端之製法， 7·如口亥包性連接墊係同時形成於電路板之上、下表面。 ^請專利範圍第i項之電路板之電性連接端之製法， 導電層主要作為後續製程形成金屬連接層所需 8 \电流傳導路徑。 其I清專利範圍第1項之電路板之電性連接端之製法， ’違導電層為金屬、合金及導電性高分子材料之其 ^ ^ ° ’、 ’=請專·圍第丨歡t路板之電性連接端， 1〇〜中，該阻層為乾膜及液態光阻之其中一者。 申：：利範圍第i項之電路板之電性連接端之製 1 /、中，該絕緣層為防銲層。 法申利乾圍第1項之電路板之電性連接端之製 屬材料第—金屬連接層、第二金屬連接層採用金 t申:中專：，第1項之電路板之電性連接端之製 13.如申1專广緣層之開口係用曝光、顯影的方式形成。 n利_第〗項之電路板之電性連接端 成:其中，該第-阻層之開口係用曝光、顯影的;式形 14·Γ:專利範圍第1項之電路板之電性連接端” /、中’该弟二阻層之開口係用曝光、顯影的方式形成。 17934 19
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