TWI245400B - Apparatus for connecting an IC terminal to a reference potential - Google Patents

Apparatus for connecting an IC terminal to a reference potential Download PDF

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TWI245400B
TWI245400B TW092101647A TW92101647A TWI245400B TW I245400 B TWI245400 B TW I245400B TW 092101647 A TW092101647 A TW 092101647A TW 92101647 A TW92101647 A TW 92101647A TW I245400 B TWI245400 B TW I245400B
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terminal
semiconductor material
substrate
patent application
scope
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TW092101647A
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TW200416991A (en
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Johann-Peter Forstner
Stephen Weber
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)

Description

1245400 五、發明說明（1) 本發明係關於連接I c終端至一參考電位之裝置，尤指一 種適合連接1C終端至接地電位之裝置。 於複數中積體電路中（integrated circuits， 1C) ’例 如電子放大器級，其性能通常依主動元件（active element) 之地連接而定。例如，在電子放大器級之經常被使_•和的射極 (emitter)電路中，射極至地的高組抗連接導致增益及效率 的損失。 在習知技術中，已知有將1C晶片之接點（pad)連接至外 部參考電位之複數種技術。 一種經常被使用之已知技術為連接IC晶片之接地接點至 基板上之導電區域，其中該1(：晶片藉由使用連接線（b〇nding wj re)而被設置於該基板上，而該導電區域定義一接地電 壓。圖2 a表示一個此種連接之範例，其中一積體電路晶片 (I C晶片）1 〇被設置於基板上，該基板為，例如，一多層板。 1C晶片之一接地端14藉由使用一連接線16電性導電連接至美 板接地區域1 8。 & 然而，連接線具有相當高的電感，因此一接地連接，如 圖2a所示，導致不良的高頻特性。為電感的降低，連接數個 平行之連接線是可能的，然而，隨後增加了區域的需 另-種依據習知技藝所使用之連接晶片1〇之接點14盥一 基板接地區域之技術被表示於圖2b。此為—晶片饋通、 (feedthrough)，亦即，一金屬晶片孔2〇，穿 表接地終端14與基板接地區域18之間的直接金Ba 並代 而，晶片孔的產生大大增加製造過程的複 牲接。然 的歿雜度，特別是關於
1245400 五、發明說明（2) 薄拋光（pol i shi ng)，蝕刻或鑽孔的需求。基於以上所述， 在此種晶片孔的產生期間有破損的風險。 最後’習知技術中已知有高度掺雜（d〇pe )砍接觸的使 用，其被稱為沉井（sinker)，以取代金屬穿孔的使用。此種 沉井22 ’其連接IC晶片10之接地終端14至一基板接地區域 1 8，此技術被表示於圖2c。為產生此種高度摻雜矽之穿透連 接，所需之製程步驟少於產生金屬晶片孔所需之步驟。缺 ，，高度摻雜矽的連接具有相當高的阻抗，其降低，例如功 ί:大以率。然而’二種穿孔型態，亦即金屬或高度摻 雜夕，以電感而言，大約比使用連接線之接地連接在大小上 好一級，如同以上參照圖23所解釋。 之裝ί發：：二目的在於提供一種連接κ終端至-參考電位 之裝置，其使1C之操作行為之改良為可能。 據申請專利範圍第1項之裝置而被達成。 -外部參考電位之裝置，其中片電路之-終端至 路以及一摻雜之半導體材料。 ^ 一連接線之平行電 该推雜之半導體材料可被形成 · 即一摻雜之半導體材料之穿 並型jslnker的形狀，亦 至卜1『^，且尤其可在1〇19cm^至的範圍幻〇%-3 中。 主1 · 1 (P cnr3的範圍 本發明之知識係基於在許多的應 非最適合，因為另一方面， ς中已知的接地連接並 果電感干擾大幅增加 1245400
==電阻損失而不適合。依據本發明，有損失的沉井至連接 平行連接消除了先前所述之二種型態的連接，而不需讓 ^更為複雜。於 >儿井及連接線之平行電路中，高頻電流主 =過沉井，而低頻電流及，尤其是直流，則流過一連接線 或夕連接線。 本發明之較佳實施例將於下文參照圖一而被解釋 細節。 於圖中，一1 C晶片1 0被設置於一基板1 2之上。此IC晶片1 〇 包括—接地終端14，其可為設置於IC晶片1〇上之一金屬接 點。此外，電路晶片10包括主動區域（active area)16，其 一般被形成於晶片10面對遠離基板12之區域中。 1C晶片10更包括一沉井（sinker) 12，其電性導電連接 =終端14至-基板接地區域26。此外，基板接地區域26經 由連接線16被電性導電連接至Ic晶片1〇之接地中端14。 沉井22可被形成於其它區域為較低㈣晶片纟板中之較 兩摻雜區域。此為一種摻雜型態之被摻雜半導體材料，其被 分佈於1C晶片之接地端與基板接地區域之間，因此於其間無 PN轉換（PN transition)。典型的摻雜高度可於i〇i8cm3至4 • up w的範圍之間’而較佳之摻雜高度則在i〇i9cm3幻 •1〇2。W的範圍中。預定的摻雜範圍是有益的，因為在較 洛：體缺陷及所需的處理時間增加，而在較低摻 雜中導電度降低。
1245400 五、發明說明（4) -- 曰曰 於本發明之較佳實施例中，高度摻雜石夕之沉井不 過全部基板，其可具有大約100至300"m的厚度，但只延 過約3至1 0 // m的區域，因為，否則製程時間將變得太長，、 高摻雜中可能發生晶體缺陷。此路徑之其它部份，亦即，； 片上之接地終端與基板接地區域之間的距離係由均勻的（在E 整個晶圓上）高度摻雜石夕基板所形成，其可具有业型的1 1 〇m Ω · cm導電度。僅於該處需要接地終端，然^，一沉井 有選擇性地被產生，以便以大約3至10 "ni厚度實施穿透&較低 摻雜基半區域之連接。 一 另一種方式，全部基板除了沉井22之處可分別為無摻雜 或相當低的摻雜然而，使用一全部高度摻雜晶片基板也是可 能的，其中，隨後，必須於主動區域16與晶片基板之間提供 適合的電隔離，例如，藉由相對的pN接面或隔離層。 ’、 沉井22及連接線16被連接至相同的基板接地^域。另一 式，沉井22及連接線16可被連接至不同的基板接點，只 要其係位於相同的參考電位。 藉由本發明在一晶片終端與一外部接點，其為一參考電 ^ 之間之摻雜半導體材料及連接線之平行電路，一”寬頻” ^接被產生，因為高頻電流主要可流過摻雜半導體材料，而 1 7 : ^寺別是直流，可流過-連接線或多連接線，如果 曰曰片〜端與外部接點之間被提供數個連接線。 地早^ 裝置對於產生電子放大器級之主動元件至外部接 用地連接特別有用。尤其是，本發明可有效地被利 书之射極電路中之一射極與一外部接地之接地連接
1^· 1245400 五、發明說明（5) 為可能。以外部大區域，一大區域被平均，其非為I C晶片本 身之部份。因此，電子放大器級之增益及效率損失可分別被 降低及避免，尤其是在高頻中。

Claims (1)

1245400
ι· 一種用於一電路晶片（1〇)之一 (26)之一電性導電連接之裝置， 接線與一摻雜之半導體材料（22) 2·如申請專利範圍第1項之裝置， 係>5夕。 終端（1 4 )至一外部參考電位 其特徵在於該裝置具有一連 之平行連接。 其中該摻雜之半導體材料 二：；：：圍第1項之裝置’其中該摻雜之半導體材料 Γϋ:摻雜型態之摻雜區域位於該電路晶片(“)之終鴻 與該t考電位(26)之間’其延伸穿過該電路晶片（1〇)。
器：凊專利範圍第1項之裝置，其中該電路晶片係-放大 \如申請專利範圍第4項之裝置，其中該終端（14)係該放大 器級之一射極終端。 6 ·如申凊專利範圍第1項之裝置，其中該參考電位（2 6 )係由 一基板（22)上之一導電區域所形成。 7·如申請專利範圍第1項之裝置，其中該摻雜之半導體材料 (22)具有一沉井（sinker)。 8·如申請專利範圍第1項之裝置，其中該參考電位（26)係一 接地電位。
9·如申請專利範圍第1項之裝置，其中該摻雜之半導體材料 (2 2 )係一電路晶片（1 〇 )之一基板中之一區域（2 2 )，其被摻雜 之程度大於該電路晶片（1 0)之該基板之其它部份。
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TW092101647A 2002-02-04 2003-01-24 Apparatus for connecting an IC terminal to a reference potential TWI245400B (en)

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DE10204403A DE10204403A1 (de) 2002-02-04 2002-02-04 Vorrichtung zur Verbindung eines IC-Anschlusses mit einem Bezugspotential

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EP (1) EP1472732B1 (zh)
JP (1) JP4151790B2 (zh)
KR (1) KR100645655B1 (zh)
CN (1) CN100358139C (zh)
AU (1) AU2003244491A1 (zh)
DE (2) DE10204403A1 (zh)
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US8055412B2 (en) * 2007-05-29 2011-11-08 Bayerische Motoren Werke Aktiengesellschaft System and method for displaying control information to the vehicle operator
TWI731257B (zh) * 2018-08-22 2021-06-21 緯創資通股份有限公司 電子秤及其控制方法
CN114334875A (zh) * 2020-09-30 2022-04-12 华为技术有限公司 封装结构及电子器件
CN115831935B (zh) * 2023-02-15 2023-05-23 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法

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JPH0734457B2 (ja) * 1988-04-05 1995-04-12 株式会社東芝 半導体装置
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EP1472732B1 (de) 2006-11-15
EP1472732A1 (de) 2004-11-03
KR100645655B1 (ko) 2006-11-14
DE10204403A1 (de) 2003-08-21
KR20040081173A (ko) 2004-09-20
CN1628384A (zh) 2005-06-15
US20050067697A1 (en) 2005-03-31
TW200416991A (en) 2004-09-01
JP2005517298A (ja) 2005-06-09
US7057271B2 (en) 2006-06-06
DE50305679D1 (de) 2006-12-28
WO2003067659A1 (de) 2003-08-14
CN100358139C (zh) 2007-12-26
JP4151790B2 (ja) 2008-09-17
AU2003244491A1 (en) 2003-09-02

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