CN1628384A - 连接ic终端至参考电位之装置 - Google Patents

连接ic终端至参考电位之装置 Download PDF

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CN1628384A
CN1628384A CNA038032740A CN03803274A CN1628384A CN 1628384 A CN1628384 A CN 1628384A CN A038032740 A CNA038032740 A CN A038032740A CN 03803274 A CN03803274 A CN 03803274A CN 1628384 A CN1628384 A CN 1628384A
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J·-P·福斯特纳
S·韦伯
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Abstract

一种用于将一电路芯片(10)之一终端(14)导电连接至一外部参考电位(26)的装置，其系包括一结合接线(16)以及一已掺杂半导体材料(22)的一并联电路。

Description

连接IC终端至参考电位之装置
发明叙述
本发明系相关于一种将一IC终端连接至一参考电位之装置，以及，特别是适合于将一IC终端连接至一接地终端的一如此的装置。
在复数个集成电路(IC)中，例如，电子放大器级(electronic amplifierstages)，执行效能系通常取决于主动组件之接地连接，此系特别为高频率的例子，举例而言，在一电子放大器级之一频繁使用的射极电路中，该射极至接地之一高阻抗连接系会导致增益以及效率的损失。
在习知技术中，复数种技术系已知用于将一IC芯片之衬垫连接至一外部参考电位。
一个频繁使用之已知技术系为，将一IC芯片之该接地衬垫连接至在该IC芯片藉由使用结合接线而放置于上之一基板上之导电区域，其中，该导电区域系会定义一接地电位，一个如此之连接的例子系显示于第2A图中，其中，一集成电路芯片(IC芯片)10系放置于一基板上，而该基板，举例而言，系可以为一多层板，至于该IC芯片之一接电终端14，则是藉由使用一结合接线16而被电连接至一基板接地区域18。
然而，结合接线系具有相对而言较高的阻抗，因此，如第2A图中所示的一接地连接系会造成不好的高频特质，而为了降低电感，则是可以将数个结合接线并联连接，只是，所需要的区域也会随之增加。
根据习知技术之用于将一芯片10之一衬垫14与一基板接地区域18进行连接的一另一技术系显示于第2B图中，此系为一芯片馈通(feedthrough)，亦即，一金属之芯片通孔20系贯穿该芯片10，并代表该接地终端14以及该基板接地区域18之间的一直接金属连接，然而，该芯片通孔之产生系会大大地增加生产制程之复杂度，尤其是关于一必需的薄研磨、蚀刻或钻孔制程，除此之外，在如此之一芯片通孔产生期间，亦具有断裂的风险。
最后，根据习知技术，其系使用已知之高度掺杂硅接触，其系称为下沉体(sinker)，以取代金属贯穿接触。如此之将一IC芯片10之一接地终端14连接至一基板接地区域18的一下沉体22，系显示于第2C图之中，而为了产生如此之高度硅掺杂之一穿透连接所需要之程序步骤系较产生一金属芯片通孔为少，然而，该高度硅掺杂之连接系具有相当高之会降低效率的阻抗，举例而言，伴随着功率放大器，但是，关于电感，两种通孔型态，亦即，金属或是高度硅掺杂者，则系皆大约较使用一结合接线的接地连接好上一个等级的程度，正如已经于之前以第2A图做为参考所解释的一样。
本发明之目的即是在于提供一种用于将一IC终端连接至一参考电位的装置，而其系能使该IC之操作性能获得改善。
而此目的则是藉由根据权利要求第1项之装置而加以达成。
本发明系提供一种用于将电路芯片之一终端导电连接至一外部参考电位的装置，其中该装置系包括一结合接线以及一已掺杂半导体材料的一并联电路。
该已掺杂半导体材料系可以被形成为习知下沉体的形状，亦即，一已掺杂半导体材料的穿透连接，典型的掺杂系介于1018cm-3至4·1020cm-3之区域，且特别是介于1019cm-3至1020cm-3的范围之间。
本发明系以已知接地连接于许多应用中并非理想的认知作为基础，这是因为一方面，该结合接线之电感干扰相当多，以及另一方面，甚至高度掺杂之半导体材料，例如硅，的下沉体系由于欧姆损失而并非理想。根据本发明，该损失之下沉体与该结合接线的并联连接系可以在不让生产制程更复杂的情形下，消除两个刚刚所提及之连接型态的缺点。在下沉体以及结合接线的并联电路中，在一高频电流系大部分会流经该下沉体的同时，一低频电流以及特别是一直流电系会流经该结合接线或该等结合接线。
本发明之一较佳实施例系将于之后以第1图做为参考而有更详尽之解释，其系显示：
第1图：其系为根据本发明之装置的一实施例的示意代表图。
在第1图中，一IC芯片10系被配置于一基板12之上，而该IC芯片10则是包括一接地终端14，且该接地终端14系可以是在该IC芯片10上的一金属衬垫，再者，该电路芯片10系包括主动区域16，且该等主动区域16系通常被形成于该电路芯片10面向远离该基板12的区域之中。
而该IC芯片10系更进一步包括一下沉体(sinker)22，其系将该接地终端14导电连接至一基板接地区域26，除了上述之外，该基板接地区域26乃是经由一结合接线16而被导电连接至该IC芯片10之该接电终端14。
该下沉体22系可以藉由在一不同之较低掺杂芯片基板中的高度掺杂硅而加以形成，而此系为一掺杂型态之一已掺杂半导体材料，位在该IC芯片之该接地终端与该基板接地区域之间，因此，并没有PN过渡位于其间。典型的掺杂高度系可以介于1018cm-3至4·1020cm-3之间的范围，而较佳的掺杂高度则是介于1019cm-3至1020cm-3的范围之间，在此所给予之掺杂范围系为较具优势者，因为在较高之掺杂中，结晶缺陷以及必要之处理时间会增加，而在较低之掺杂中，导电性会减少。
在本发明之较佳实施例中，高度掺杂硅之该下沉体系并无法延伸穿透整个可具有大约100μm至300μm之厚度的基板，但仅能延伸穿过大约3至10μm的区域，这是因为不然的话，该制程时间将会变得太长，并且，在高掺杂中，会发生结晶缺陷。至于该路径剩余的部分，亦即，在该芯片上之该接地终端以及该基板接地区域间之距离，乃是藉由一均匀(覆盖整个晶圆)之高度掺杂硅基板而加以形成，其系可以具有一典型的1…10Ωm·cm的导电度。而仅有当需要一接地终端时，则一下沉体才会被选择性地加以产生，以执行穿透该低掺杂基板区域大约3至10μm厚度之该连接。
再者，除了该下沉体22之外，该整个芯片基板系可以分别是未掺杂或是相当低的掺杂，然而，其系亦有可能使用一足够高的掺杂芯片基板，然后，在该主动区域16以及该芯片基板之间则必须要，举例而言，藉由相对应之PN接面或隔离层，而提供适当的电隔离。
该下沉体22以及该结合接线6系被连接至相同的基板接地区域26，或者，该下沉体22以及该结合接线16也可以被连接至不同的基板衬垫，只要它们位在相同的参考电位即可。
一“宽频”连接系可以藉由根据本发明之在一芯片终端以及一外部衬垫间，已掺杂半导体材料以及结合接线之处于一参考电位的并联电路而加以产生，因为若是数个结合接线系被提供在芯片终端以及外部衬垫之间时，则在一高频电流可以大部分地流过该已掺杂半导体材料的同时，一低频电流以及特别是一直流电系可以流过该结合接线或该等结合接线。
本发明之装置系特别的有利于产生电子放大器级之该主动组件到一外部接地平面的一接地连接，特别地是，本发明系可以较具优势地被用于在频繁使用之射极电路中，以使得一射极与一外部接地区域之一接电连接成为可能，伴随着外部的大量区域，并非该IC芯片本身之一部份的一大量区域系会被使用，因此，电子放大器级之增益以及效率损失系可以被分别降低以及避免，特别是在高频时。

Claims (9)

1.一种用于将一电路芯片(10)之一终端(14)导电连接至一外部参考电位(26)的装置，其特征在于，该装置系具有一结合接线以及一已掺杂半导体材料(22)的一并联连接。
2.根据权利要求第1项所述之装置，其中该已掺杂半导体材料系为硅。
3.根据权利要求第1或第2项所述之装置，其中该已掺杂半导体材料(22)系具有一掺杂型态的一已掺杂区域，位于该电路芯片(14)之终端以及该参考电位(26)之间，且系延伸穿透该电路芯片(10)。
4.根据权利要求第1至第3项其中之一所述之装置，其中该电路芯片系为一放大器级(amplifier stage)。
5.根据权利要求第4项所述之装置，其中该终端(14)系为该放大器级之一射极终端。
6.根据权利要求第1至第5项其中之一所述之装置，其中该参考电位(26)系藉由在一基板(12)上之一导电区域而加以形成。
7.根据权利要求第1至第6项其中之一所述之装置，其中该已掺杂半导体材料(22)系具有一下沉体(sinker)。
8.根据权利要求第1至第7项其中之一所述之装置，其中该参考电位(26)系为一接地电位。
9.根据权利要求第1至第8项所述之装置，其中该已掺杂半导体材料(22)系为在一电路芯片(10)之一基板中的一区域(22)，而该区域(22)系比该电路芯片(10)之该基板的其它部分有更高之掺杂。
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US7057271B2 (en) 2006-06-06
KR20040081173A (ko) 2004-09-20
EP1472732B1 (de) 2006-11-15
AU2003244491A1 (en) 2003-09-02
DE10204403A1 (de) 2003-08-21
TW200416991A (en) 2004-09-01
DE50305679D1 (de) 2006-12-28
EP1472732A1 (de) 2004-11-03
CN100358139C (zh) 2007-12-26
TWI245400B (en) 2005-12-11
US20050067697A1 (en) 2005-03-31
JP2005517298A (ja) 2005-06-09
WO2003067659A1 (de) 2003-08-14

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