TWI245392B - Leadless semiconductor package and method for manufacturing the same - Google Patents
Leadless semiconductor package and method for manufacturing the same Download PDFInfo
- Publication number
- TWI245392B TWI245392B TW093119076A TW93119076A TWI245392B TW I245392 B TWI245392 B TW I245392B TW 093119076 A TW093119076 A TW 093119076A TW 93119076 A TW93119076 A TW 93119076A TW I245392 B TWI245392 B TW I245392B
- Authority
- TW
- Taiwan
- Prior art keywords
- inner guide
- lead
- guide pins
- semiconductor package
- wafer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title description 8
- 238000004519 manufacturing process Methods 0.000 title description 6
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 claims description 26
- 239000000565 sealant Substances 0.000 claims description 7
- 230000008901 benefit Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 87
- 239000002184 metal Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- WZZBNLYBHUDSHF-DHLKQENFSA-N 1-[(3s,4s)-4-[8-(2-chloro-4-pyrimidin-2-yloxyphenyl)-7-fluoro-2-methylimidazo[4,5-c]quinolin-1-yl]-3-fluoropiperidin-1-yl]-2-hydroxyethanone Chemical compound CC1=NC2=CN=C3C=C(F)C(C=4C(=CC(OC=5N=CC=CN=5)=CC=4)Cl)=CC3=C2N1[C@H]1CCN(C(=O)CO)C[C@@H]1F WZZBNLYBHUDSHF-DHLKQENFSA-N 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- YSUIQYOGTINQIN-UZFYAQMZSA-N 2-amino-9-[(1S,6R,8R,9S,10R,15R,17R,18R)-8-(6-aminopurin-9-yl)-9,18-difluoro-3,12-dihydroxy-3,12-bis(sulfanylidene)-2,4,7,11,13,16-hexaoxa-3lambda5,12lambda5-diphosphatricyclo[13.2.1.06,10]octadecan-17-yl]-1H-purin-6-one Chemical compound NC1=NC2=C(N=CN2[C@@H]2O[C@@H]3COP(S)(=O)O[C@@H]4[C@@H](COP(S)(=O)O[C@@H]2[C@@H]3F)O[C@H]([C@H]4F)N2C=NC3=C2N=CN=C3N)C(=O)N1 YSUIQYOGTINQIN-UZFYAQMZSA-N 0.000 description 1
- 241001622925 Acacia coriacea Species 0.000 description 1
- WSNMPAVSZJSIMT-UHFFFAOYSA-N COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 Chemical compound COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 WSNMPAVSZJSIMT-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 235000014347 soups Nutrition 0.000 description 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
1245392
五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於使用無外引腳導狀 彳:方:別係有關於-種無外引腳式半導;:= 【先前技術】 =半導體封裝係以一晶片載體來承載與電性連接一 Η Ϊ如電路基板與導線架,其中以無外引腳導線 木作為日日片載體可同時兼顧到低成本與小尺寸之優點, ίΪ後之導線架内導腳之排列與數量將受限於無外引腳導 線#之製程與設計,無法廣泛使用。 、请/參閱第1及2圖,一種習知之無外引腳式半導體封裝 構造1係包含有由構成於一無外引腳導線架之一晶片承座 ^與複數個内導腳12、一半導體晶片2〇以及一封膠體3〇 ; 請參閱第2圖,該些内導腳12係形成於該晶片承座丨丨之外 周邊,該晶片承座11係以複數個支撐條13(tie bar)連接 至遺導線架;請參閱第1圖,,該半導體晶片2 〇之一背面 22係以一黏著劑24設於該晶片承座i 上,該晶片2〇之一主 動面2 1係具有複數個銲墊2 3,以複數個銲線2 5連接該晶片 20之該些銲墊23至該些内導腳12,並以該封膠體3〇密封該 晶片20及該些銲線25。由於習知該封膠體3〇係以壓模 (mo Id i ng)形成,為了阻止該封膠體3〇之殘膠因擠壓擴散 而污染至該些内導腳1 2與該晶片承座11之下表面,習知會 在壓模前,預先黏貼一外置膠片40來全面遮蓋該些内導腳 1 2與該晶片承座11之下表面(如第1圖所示),以避免該封
第8頁 1245392
且在形成該封膠體30之後,再移除該外置膠片4〇,因此, 膠體30之污染至該些内導腳12與該晶片承座丨丨之下表面, 該外置膠片40係為不可存在於該無外引腳式半導體封裝構 造1〜内部之製程消耗材,且因貼設及移除該外置膠片4〇而 使得製程步驟增多。此外,該晶片承座丨丨係必須以複數個 支撐條13連接,通常該些支撐條13係對應於該封膠體“之 四邊角隅,並且該些内導腳12應具有相當的寬度,以提供 足夠的結構強度來連接至該導線架之框條,使得該晶片承 座11,該些内導腳1 2之排列位置受限於導線架之製程能力 無法高密度地任意配置。 【發明内容】 ❶ 本發明之主要目的係在於提供一種無外引腳式半導體 ,衷構造,其係包含有構成於一導線架之一晶片承座與 數個内導腳’纟該些内導腳之間以及在該晶片承座與該些 ίί腳ί間係形成有—非導電油*,該非導電油墨係結i 二二内導腳與該晶片承座,以取代習知之聯結條,以利該 二内導腳之配置,另在封膠體之壓模過程中,可不需 =貼附在導線架下表面之外置膠片,#可達到防止該封膠 體之殘膠污染至該些内導腳與該晶片承座之下表面之功 本發明之次一目的係在於提供一種無外引腳式半導體 二、構造,一非導電油墨係形成於該些内導腳之間並結合 内導腳與該晶片承座,+需要習知在封膠體角隅之; 、、口条連接該晶片承座,故該些内導腳係可以形成於該封膠
1245392
排之周邊排列,增 1封裝之運用範圍( 弓丨腳式半導體封裝 數個内導腳與至少 晶片以及一封膠體 導腳之間並結合該 係設於該晶片承座 係形成於該些内導 體晶片,較佳地, 體之角隅或是為多 係可以更高密度排 可為多晶片封裝或 發明說明(3) 體之角隅或可以是多 架在高密度I/O半導負 依本發明之無外 構成於一導線架之複 導電油墨、一半導體 油墨係形成於該些内 承座,該半導體晶片 些内導腳,該封膠體 上,用以密封該半導 係可以形成於該封膠 外,由於該些内導腳 式半導體封裝構造係 件0 加了無外引腳導線 構造’主要包含有 一晶片承座、一亦 ,其中,該非導電 些内導腳與該晶片 上並電性連接至該 腳與該非導電油墨 部偷之該些内導腳 排周邊排列,此 列,故該無外引腳 另包含有一被動元 【實施方式】 參閱所附圖式,本發明將列舉以下之實施例說明。 依據本發明之第一具體實施例,請參閱第3、4及5 圖,一種無外引腳式半導體封裝構造丨〇 〇係主要包含有構 成於導線木之至少一晶片承座111與複數個内導腳11 2、 11 3、1 1 4、一非導電油墨1 2 0、一半導體晶片j 3 〇以及一封 膠體1 4 0,在本實施例中,請參閱第4圖,該些内導腳 112、113、114係區分為複數個第一内導腳η?、複數個第 二内導腳113及至少一第三内導腳114,該晶片承座π i係 形成於該導線架之中央區域,該非導電油墨1 2 0係形成於 該些第一内導腳112、該些第二内導腳Π3與該第三内導腳
第10頁 1245392 五、發明說明(4) 11 4之間,較佳地,該非導電油墨〗2 0亦形成於該晶片承座 111與該些内導腳1 1 2、1 1 3、11 4之間,並結合該些第一内 導腳11 2、該些第二内導腳1 13、該第三内導腳1 14與該晶 片承座111,因此,該晶片承座1 11係可以不需要以習知之 支撐條(tie bar )連接至導線架,使得該晶片承座1 11係為 無支揮條而與該些内導腳112、113、114連接固定,其中 該些第一内導腳11 2係較遠離該晶片承座1 1 1,該些第二内 導腳11 3係較接近該晶片承座111,且該些第一内導腳丨】2 與該些第二内導腳1 1 3係為多排周邊排列於該晶片承座丨u 外周圍,此外,該第三内導腳11 4係設於該封膠體1 40之角 隅。在本實施例中,請參閱第3圖,該非導電油墨1 2 〇係形 成於該些第一内導腳112之上表面11 2a與下表面112b之 間’且該非導電油墨1 2 0之厚度以小於該些第一内導腳11 2 之厚度為較佳,另有關本案之該包含有非導電油墨1 2 〇之 無外引腳導線架之製造方法容後詳述。 此外,該半導體晶片1 3 0係設於該晶片承座111上,該 晶片1 3 0係具有一主動面1 3 1及一對應之背面1 3 2,複數個 鮮塾1 3 3係設於該主動面1 31上,以一黏著劑1 34黏貼該晶 片130之背面132與該晶片承座11 1之上表面llla,並以複 數個杯線1 3 5將該晶片1 3 0之該些鲜塾1 3 3連接至對應之該 些第一内導腳112之上表面112a、該些第二内導腳113之上 表面11 3a與該第三内導腳11 4之上表面114a,以電性連接 該晶片1 3 0至該些内導腳11 2、11 3、11 4。 該封膠體140係形成於該些第一内導腳112、該些第二
第11頁 1245392 五、發明說明,(5)
内導腳1 13、該第三内導腳1 14與該非導電油墨1 20上,用 以农封該半導體晶片1 3 0,在本實施例中,該些第一内導 腳112之下表面U2b、該些第二内導腳113之下表面u3b、 該第三内導腳11 4之下表面1 1 4b與該晶片承座111之下表面 111 b係顯露出該非導電油墨1 2 〇。通常該封膠體1 4 〇係以壓 模(mol ding)方式形成,由於在該些第一内導腳112、該些 第二内導腳1 1 3、該第三内導腳1 1 4與該晶片承座11 i之間 空隙係已被該非導電油墨1 2 0填實密封,故該封膠體丨4 〇在 壓模形成過程中,係不會污染至該些第一内導腳丨丨2之下 表面112b、該些第二内導腳113之下表面丨丨扑、該第三内 導腳114之下表面114b與該晶片承座in之下表面1111;),以 供外部電性導接與對外導熱,減少了習知在無外引腳之封 裝過程中所需要之外置膠片。此外,在較内排該些第二内 導腳11 3可被該非導電油墨1 2〇機械性連接固定,在封裳製 程中’不需要連接至該導線架之框條,在設計上更可緊密 排列,也就是說,在封裝後,該些第二内導腳丨丨3係不需 要延伸至該封膠體1 4 0之側邊而能任意獨立設置。
因此’在上述之無外引腳式半導體封裝構造1〇〇中, 該晶片承座1 11、該些第一内導腳丨丨2、該些第二内導腳 11 3、該第三内導腳11 4係以該非導電油墨丨2〇機械性連接 固定,並不需要以習知在封膠體角隅之支撐條加以連接, 故該晶片承座11 1之數量與位置可為任意設計,該封膠體 140之角隅係可再排列上更多之第三内導腳114,此外,呈 多排排列之該些第一内導腳112與該些第二内導腳113亦被 1245392 五、發明說明(6) 非導電油墨1 2 0所連接固定,因此在製程中該些在較阿排 之第二内導腳1 1 3能以極細的導腳寬度通過該些第一内導 腳11 2而連接至該無外引腳導線架,或者以半/全蝕刻方式 而完全不需要連接至該無外引腳導線架。 關於用以製造上述無外引腳式半導體封裝構造1〇〇之 無外引腳導線架製程係說明如后,請參閱第6A圖,首先提 供有一金屬板50,該金屬板50係具有一上表面51及一下表 面5 2 ’该金屬板5 〇係定義有至少一用以形成該晶片承座 111之區域與用以形成該些内導腳、ι13、ιΐ4之區域, 並且一第一乾膜6〇(first dry film)係貼附於該金屬板5〇 之下表面52 ;接下來,請參閱第6B圖,對該第一乾膜6〇進 行曝光顯影,以圖案化該第一乾膜6〇,並使該第一乾膜6〇 係形成有複數個開口 61,該些開口 6丨係顯露該金屬板5 〇除 了用以形成該晶片承座丨丨i區域與用以形成該些内導腳 11 2、1 1 3、1 1 4區域以外之該下表面52其它區域,以供該 下表面52之半蝕刻;接著,請參閱第6C圖,藉由該第一乾 膜60之該些開口 61半蝕刻該金屬板5〇之下表面52,使得該 下表面52形成有複數個鏤空區53,但該些鏤空區53應不貫 通至該金屬板50之上表面51為較佳;之後,請參閱第6d 圖,在移除該第一乾膜6 〇之後,將可顯露出該些第一内 腳112之下表面U2b與該晶片承座lu之下表面丨丨“,而該 些第二内導腳113之下表面113b、該第三内導腳114之下表 面114b亦同時可被顯露出(圖未繪出);請參閱第⑽圖,將 上述之該非導電性油墨丨20以網版印刷或其它可能之填 1245392
五、發明說明(7) 方式形成於該金屬板50之該些鏤空區53,此時,該 性〉由墨120係不會流佈至該金屬板50之上表面51,該 電性油墨1 2 0係具有熱固化或光固化之特性,填充後並 該非導電性油墨1 2 0經適當固化或半固化;接下來,請來 閱第6F圖,研磨該金屬板50與該非導電性油墨i 2〇,^ & 該非導電性油墨120係不覆蓋至該些第一内導腳112之下于 面11 2b與該晶片承座ill之下表面U lb,並使該非導電性 油墨120與該些第一内導腳11 2之下表面1121)與該晶片承座 ill之下表面liib (即該金屬板50之下表面52)為同平面為 較佳。接著,請參閱第6G圖,在該金屬板5〇之上表面51貼 附一第二乾膜70 ;之後,請參閱第6丨丨圖,對該第二乾膜μ 曝光,影,以圖案化該第二乾膜7〇,使得該第二乾膜7〇形 成有複數個開口71,該些開口71係顯露該金屬板5〇除了用 以形成該晶片承座111區域與用以形成該些内導腳丨12、 113、114區域以外之該上表面51其它區域;接下來,請參 閱第61圖,圖案化蝕刻該金屬板5〇之上表面51,以形成^ - 述之該晶片承座11 1與該些第一内導腳i J 2,且該晶片承座 111與該些第一内導腳U 2係被該非導電油墨12〇所連接固 定’此外在本步驟中該些第二内導腳丨丨3與該第三内導腳 11 4亦已同時形成且被該非導電油墨丨2 〇所連接固定(圖未· 繪出)’因此’該晶片承座丨u並不需要支撐條連接,且較 内排之第二内導腳丨丨3亦不再需要習知寬度之連接導腳 部’使得多排之第一内導腳丨丨2與第二内導腳1 1 3可以更加 密集地緊密排列。
第14頁 1245392 五、發明說明(8) 依據本發明之第二具體實施例,請參閱第7及8圖,,由 於本發明之内導腳可以密集地排列而達到高密度外接端, 一種無外引腳式半導體封裝構造200係為具有多晶片封裝 之型態’其係包含有構成於一導線架之一第一晶片承座 211、一第二晶片承座212、複數個第一内導腳213、複數 個第二内導腳2 1 4、複數個第三内導腳2 1 5以及至少一中繼 導腳2 1 6,該些第一内導腳2 1 3係為較外排而較遠離該第一 晶片承座2 1 1與該第二晶片承座2 1 2,該些第二内導腳2 1 4 係為較内排而更加接近該第一晶片承座2 u與該第二晶片 承座21 2 (如第8圖所不)’該些第三内導腳21 6係排列於該 導線架之封裝單元角隅處,在該第一晶片承座2 π、該第 二晶片承座212、該些第一内導腳213、該些第二内導腳 21 4、該些第三内導腳21 5與該中繼導腳21 6之間之間係形 成有一非導電油墨220,且該第一晶片承座2Π、該第二晶 片承座212、該些第一内導腳213、該些第二内導腳214、 該些第三内導腳2 1 5與該中繼導腳2 1 6係被該非導電油墨 220結合固定,因此該第一晶片承座211、該第二晶片承座 212與該中繼導腳2 16係可不需要連接任何金屬支撐條來支 持固定,以增進該些晶片承座21 1、21 2與該些導腳21 3、 214、215、216之設計彈性;一第一半導體晶片230係設於 該第一晶片承座211之上表面211a,一第二半導體晶片240 係没於或第二晶片承座2 1 2之上表面21 2 a,並以複數個焊 線250將該第一半導體晶片230與該第二半導體晶片240電 性連接至對應之第一内導腳21 3或第二内導腳2 1 4,或有直
第15頁 1245392 五、發明說明(9) 接電性傳導之困難時,則利用該中繼導腳2丨6將至少一鲜 線250連接該第一半導體晶片230或該第二半導體晶片24〇 至5亥中繼導腳2 1 6 ’再以另一鲜線2 5 0連接該中繼導腳2 1 5 至對應之第一内導腳2 1 3或第二内導腳2 1 4,一封膠體2 6 0 係形成於該些第一内導腳213、第二内導腳214、該些第三 内導腳215、該中繼導腳216與該非導電油墨220上,以密 封該第一半導體晶片2 3 0與該第二半導體晶片2 4 〇,此外, 該些第三内導腳215係可以形成於該封膠體26〇之角隅,以 增加該些内導腳之高密度排列。 依據本發明之第三具體實施例,請參閱第9圖,一種 無外引腳式半導體封裝構造係主要包含有構成於一無外引 腳導線架之一晶片承座311、複數個第一内導腳31 2、複數 個第二内導腳31 3與複數個第三内導腳314、一非導電油墨 320、一半導體晶片330及一封膠體340,其中,該些第二 内導腳313係對應於該些第一内導腳312之位置而更加接近 該晶片承座3 1 1 ’其係為較内排排列之内導腳,而該些第 三内導腳314係形成於該封膠體340之角隅,該非導電油墨 320係形成於該些第一内導腳312、該些第二内導腳31 3與 該些第三内導腳31 4之間並結合該些内導腳31 2、31 3、31 4 與該晶片承座31 1,該半導體晶片33 0係設於該晶片承座 3 11上,此外,該晶片承座3 11係可被該非導電油墨3 2 0取 代’即將該半導體晶片3 3 0設於該非導電油墨3 2 0上,該非 導電油墨3 2 0係能取代習知之聯結條或該晶片承座3 11,並 以複數個銲線35 0電性連接至對應之該些第一内導腳31 2與
第16頁 1245392 五、發明說明(ίο) 該些第二内導腳31 3,而該封膠體340係形成於該些内導腳 3 1 2、3 1 3、3 1 4與該非導電油墨3 2 0上,用以密封該半導體 晶片330。此外,例如電容、電阻或電感之一被動元件36〇 係設於該些第三内導腳3 1 4上,且至少一銲線3 5 0係電性連 接该半導體晶片330至其中一第三内導腳3 1 4,以增進該無 外引腳式半導體封裝構造之電性功能。 本發明之保護範圍當視後附之申請專利範圍所界a 為準任何热知此項技藝者,在不脫離本發明之精細 # 圍内所作之任何變化盘你 珅和範 7 $化與修改,均屬於本發明之保蠖範圍。
明】 習知無外引腳式半導體 習知無外引腳式半導體 丨式簡單說明 圖式簡單說 第 1 圖: 第 2 圖: 上視圖; 第 3 圖: 腳式半導體封 第 4 圖: 式半導體封裝 第 5 圖: 式半導體封裝 第6A至61圖: 外引腳式半導 之截面示意圖 第 7 圖: 腳式半導體封 第 8 圖: 式半導體封裝 第9 圖: 腳式半導體封 封裝構造之截面圖; 封裝構造在封膠前之 依據本發明之第 装構造之載面圖 依據本發明之第 構造在封膠前之 依據本發明之第 構造之下視圖; 依據本發明之第一具體 體封裝構造之無外引腳 具體實施例,一種無外引 一具體實施例,該無外引腳 上視圖; 一具體實施例,該無外引腳 實施例’適用於該無 導線架在製造過程中 依據本發明之第 裝構造之截面圖 依據本發明之第 構造在封膠前之 依據本發明之第 裝構造在封膠前 二具體實施例 種無外引 二具體 上視圖 三具體 之上視 實施例,該無外引腳 ;及 實施例, 圖0 種無外引 元件符號簡單說明: I 無外引腳式半導體封裝構造 II 晶片承座 12 内導腳 2〇 半導體晶片 21 主動面 13 支撐條 22 背面
第18頁 1245392 圖式簡單說明 23 銲 墊 24 黏 著 劑 25 銲 線 30 封 膠 體 40 外 置 膠片 50 金 屬 板 51 上 表 面 52 下 表 面 53 鏤 空 區 60 第 一 乾 膜 61 開 π 70 第 -- 乾 膜 71 開 a 100 無 外 引 腳式半 導體 封 裝 構 造 111 晶 片 承 座 111 a 上 表 面 111b 下 表 面 112 第 一 内 導腳 112 a 上 表 面 112b 下 表 面 113 第 二 内 導腳 113 a 上 表 面 113b 下 表 面 114 第 内 導腳 114 a 上 表 面 114b 下 表 面 120 非 導 電 油墨 130 半 導 體 晶片 131 主 動 面 132 背 面 133 銲 墊 134 黏 著 劑 135 銲 線 140 封膠體 200 無外引腳式半導體封裝構造 211 第一晶片承座211a上表面 211b下表面 212 第二晶片承座212a上表面 212b下表面 213 第一内導腳 214 第二内導腳 215 第三内導腳 216 中繼導腳 220 非導電油墨 230 第一半導體晶片 240 第二半導體晶 片 250 銲線 260 封膠體 311 晶片承座 312 第一内導腳 313 第二内導腳
第19頁 1245392___ 圖式簡單說明 314 第三内導腳 320 非導電油墨 330 半導體晶片 340 封膠體 350 銲線 360 被動元件 〇 Ι·ϋ 第20頁
Claims (1)
1245392 六、申請專利範圍 【申請專利範 1、一種無外 複數個内 一非導電 些内導腳與該 一半導體 該些内導腳; 圍】 引腳式半導體封裝構造,其包含 上,用 2、 如 構造’ 下表面 3、 如 構造’ 4、 如 構造, 5、 如 構造 竣内導 6、 士口 構造, 電油墨 γ、如 媾透, 封膠體 以密封 申請專 其中該 之間。 申請專 其中該 申請專 其中至 申請專 其中該 腳。 申請專 其另包 所固定 申請專 其另包 導腳與至少 油墨,其係 晶片承座; 晶片’其係 及 ,其係形成 該半導體晶 利範圍第1 非導電油墨 利範圍第1 些内導腳係 利範圍第1 形 晶片承座; 成於該些内導腳之間並結合 該 設於該晶片承座上並電性連接至 於該些内導腳與該非導電油墨 片。 & 項所述之無外引腳式半導體封裝 係形成於該些内導腳之上表面與 項所述之無外引腳式半導體封裝 為多排周邊排列。 項所述之無外引腳式半導體封裝 少一内導腳係設於該封膠體之角隅。 項所述之無外引腳式半導體封裝 係藉由複數個銲線電性連接至該 利範圍第1 半導體晶片 利範圍第1 含有至少- 〇 利範圍第1項所述之無外引腳式半導體封裝 含有一被動元件,其係設於部份該些内導腳 項所述之無外引腳式半導體封裝 獨立之中繼導腳,其係被該非導
第21頁 1245392 六、申請專利範圍 上。 8、一種無外 複數個内 一非導電 一半導體 内導腳 封膠體 以密封 申請專 其中該 之間。 申請專 其中該 申請專 其中至 申請專 其中該 腳。 申請專 其另包 所固定 申請專 其另包 至該些 上,用 9、如 構造, 下表面 10、 如 構造, 11、 如 構造, 12、 如 構造, 些内導 13、 如 構造, 電油墨 14、 如 構造, 上〇 引腳式半導體封裝構造,其包含: 導腳; 油墨’其係形成於該些内導腳之間; 晶片,其係設於該非導電油墨上並電性連接 ;及 ’其係形成於該些内導腳與該非導電油墨 該半導體晶片。 利範圍第8項所述之無外引腳式半導體封裝 非導電油墨係形成於該些内導腳之上表面與 利範圍第8項所述之無外引腳式半導體封裝 些内導腳係為多排周邊排列。 ^ 利範圍第8項所述之無外引腳式半導體封裝 少一内導腳係設於該封膠體之角隅。 t 利範圍第8項所述之無外引腳式半導體封裝 半導體晶片係藉由複數個銲線電性連接至該 =範圍第8項所述之無外引腳式半導體封裝 含有至少—獨立之中繼導腳,其係被該非導 〇 =範圍第8項所述之無外引腳式半導體封裝 含有一被動元件,其係設於部份該些内導腳
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US7777626B2 (en) * | 2005-10-13 | 2010-08-17 | BAE Systems Information and Electronic Systems, Integration, Inc. | RFID tag incorporating at least two integrated circuits |
US8163604B2 (en) * | 2005-10-13 | 2012-04-24 | Stats Chippac Ltd. | Integrated circuit package system using etched leadframe |
US7834435B2 (en) * | 2006-12-27 | 2010-11-16 | Mediatek Inc. | Leadframe with extended pad segments between leads and die pad, and leadframe package using the same |
US8124461B2 (en) * | 2006-12-27 | 2012-02-28 | Mediatek Inc. | Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product |
CN101211794A (zh) * | 2006-12-27 | 2008-07-02 | 联发科技股份有限公司 | 封装半导体元件方法、制作引线框架方法及半导体封装产品 |
CN100539054C (zh) * | 2007-03-13 | 2009-09-09 | 百慕达南茂科技股份有限公司 | 芯片封装结构及其制作方法 |
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US6629880B1 (en) * | 2000-12-14 | 2003-10-07 | National Semiconductor Corporation | Rotary mechanical buffing method for deflashing of molded integrated circuit packages |
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TWI236721B (en) * | 2004-06-29 | 2005-07-21 | Advanced Semiconductor Eng | Leadframe for leadless flip-chip package and method for manufacturing the same |
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