TWI245381B - Electrical package and process thereof - Google Patents
Electrical package and process thereof Download PDFInfo
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- TWI245381B TWI245381B TW092122342A TW92122342A TWI245381B TW I245381 B TWI245381 B TW I245381B TW 092122342 A TW092122342 A TW 092122342A TW 92122342 A TW92122342 A TW 92122342A TW I245381 B TWI245381 B TW I245381B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H—ELECTRICITY
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- H01L2224/05573—Single external layer
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
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Description
J2451SJ___ 五、發明說明(1) 【發明所屬之技術領域】 本發明是有關於一種的電氣封裝體及其製程,且特別 是有關於一種應用由導電材質所製成之支撐基板 (support substrate )之電氣封裝體及其製程。 【先前技術】 覆晶連線技術(F 1 i p C h i p I n t e r c ο η n e c t T e c h η o 1 o g y ,簡稱F C )是一種將晶片(d i e )電性連接至 承載器(c a r r i e r )的封裝方法。覆晶連線技術主要是利 用面陣列(area array)的方式,將多個晶片墊(die pad)配置於晶片f主動表面(active surface)上,並 在晶片墊上形成凸塊(b u m p ),接著將晶片翻覆(f 1 i p ) 之後,再利用這些凸塊來分別電性耳結構性連接晶片之晶φ 片塾至承載器上的凸塊塾(buinp pad ),使得晶片可經由 這些凸塊而電性連接至承載器,並經由承載器之内部線路 而電性連接至外界之電子裝置。值得注意的是,由於覆晶 連線技術(F C )可適用於高腳數(H i g h P i n C 〇 u n t )之晶 片封裝體,並同時具有縮小晶片封裝面積及縮短訊號傳輸 路徑等諸多優點,所以覆晶連線技術目前已廣泛地應用於 晶片封裝領域,常見應用覆晶接合技術之晶片封裝結構例 如有覆晶球格陣列型(F 1 i p C h i p / B a 1 1 G r i d A r r a y ’ FC/BGA )及覆晶針格陣列型(F 1 i p Ch i p / P i n G r i d Array ,FC/PGA )等型態之晶片封裝結構。 請參考第1圖,其繪示習知之一種覆晶球格陣列型之 4 電氣封裝體的剖面示意圖。電氣封裝體1 0 0包括基板
11530rwf.prd 第6頁 1-245381--- 五、發明說明(2) (substrate ) 110 、多個凸塊1 2 0、晶片1 3 0及多個銲球 140。其中,基板11〇具有一頂面112及對應之一底面114 , 且基板110更具有多個凸塊墊(bump pad) 116a及多個銲 球墊(b a 1 1 p a d ) 1 1 6 b。此外,晶片1 3 0具有一主動表面 (active surface )132及對應之一背面134 ,其中晶片 1 3 0之主動表面1 1 2係泛指晶片1 3 0之具有主動元件 (active device)(未繪示)的一面,並且晶片130更具 有多個晶片墊136 ,其配置於晶片130之主動表面132 ,用 以作為晶片1 3 0之訊號輸出入的媒介,而這些凸塊墊1 1 6 a 之位置係分別對應於這些晶片墊1 3 6之位置。另外,這些 凸塊1 2 0則分別電性及結構性連接這些晶片墊1 3 6之一至其 所對應之這些凸塊墊1 1 6 a之一。並且,這些銲球1 4 0則分 _ 別配置於這些銲球墊1 1 6 b上,用以電性及結構性連接至外·_ 界之電子裝置。 請同樣參考第1圖,習知之電氣封裝製程乃是在完成 基板1 1 0之内部線路及接點1 1 6 a、1 1 6 b之後,再將晶片1 3 0 組裝於基板1 1 0之表面上,接著將一底膠(u n d e r f i 1 1 ) 150填充於基板110之頂面112及晶片130之主動表面132所 圍成的空間,用以保護這些凸塊墊1 1 6 a、這些晶片墊1 3 6 及這些凸塊1 2 0 ,並同時緩衝基板1 1 0與晶片1 3 0之間在受 熱時所產生熱應變(thermal strain)之不匹配的現象。 因此,晶片1 3 0之晶片墊1 3 6將可經由凸塊1 2 0而電性及結 構性連接至基板1 1 0之凸塊墊1 1 6 a,再經由基板1 1 0之内部φ 線路而向下繞線(r 〇 u t i n g )至基板1 1 0之底面1 1 4的銲球
11530rwf.prd 第7頁 1245381___ 五、發明說明(3) 墊1 1 6 b,最後經由銲球墊1 1 6 b上之銲球1 4 0而電性及結構 性連接至外界之電子裝置。 就高密度線路佈線之基板的製程而言,習知通常是利 用增層法(build up)在一介電芯層(dielectric core )之兩面分別同時形成一線路層,並且利用鍍通孔道 (Plated Through Hole,PTH)來電性連接兩線路層。然 而,由於使用厚度較薄之介電芯層的基板很容易受熱而發 生翹曲(w a r p )的現象,所以基板之介電芯層必須具有足 夠的厚度,如此才能相對提供足夠的結構強度,但這也導 致介電芯層之厚度無法進一步地降低。 除此之外,為了在介電芯層上製作導電孔道(PT Η ),習知通常是利用雷射鑽孑L (laser drilling)的方 式,在介電芯層上形成微細尺寸的貫孔,接著電鍵一金屬® 層於貫孔之内壁,用以電性連接位於介電芯層之兩面的線 路層。然而,由於習知之錢通孔道(P T Η )的製程通常是 利用雷射鑽孔來形成微細尺寸的貫孔,如此將導致基板之 整體製作成本的提高。此外,習知之鍍通孔道(Ρ Τ Η )的 製程已無法有效降低導電孔道(ΡΤΗ )之外徑,使得習知 之導電孔道(Ρ Τ Η )儼然成為目前高密度線路佈線之基板 的設計瓶頸。 【發明内容】 有鑑於此,本發明的目的就是在提供一種電氣封裝體 及其製程,用以提供高密度接合墊及微細線路的多層内連g丨 線結構,並可有效地降低電氣封裝體之製作成本及顯著地
11530rwf.ptd 第8頁 1245381___ 五、發明說明(4) 提升電氣封裝體之電性效能。 為達本發明之上述目的,本發明提出一種電氣封裝 體,此電氣封裝體包括一多層内連線結構(in u 1 t i - 1 a y e r interconnection structure )、至少一電子元件及一支 撑基板。首先,此多層内連線結構具有一頂面及對應之一 底面,且此多層内連線結構更具有一内部線路(i η n e r circuit ),其具有多個接合墊,而這些接合墊係位於此 多層内連線結構之底面。此外,電子元件係配置於此多層 内連線結構之頂面,並電性連接於此多層内連線結構之内 部線路。另外,支撐基板之材質係為導電材質,且此夂撐 基板係配置於此多層内連線結構之底面,而此支撐基板更 具有多個開口 ,其分別暴露出其所對應之這些接合墊之 | -— 〇 為達本發明之上述目的,本發明又提出一種電氣封裝 製程。首先,提供一支撐基板,其材質係為導電材質。接 著,形成一多層内連線結構於此支撑基板之上,且此多層 内連線結構具有一内部線路,而此内部線路更具有多個接 合塾,其位於此多層内連線結構之接近此支#基板之一 面。形成多個開口於支撐基板上,而這些開口係分別暴露 出其所對應之這些接合塾之一。配置至少一電子元件於此 多層内連線結構之遠離此支撑基板之一面,且此電子元件 係電性連接於此多層内連線結構之内部線路。 基於上述,本發明係採用一具有硬質性、可導電性、4 低熱膨脹係數(CTE )及高熱導性之支撐基板作為製程之 III 81 II 1 1 11530twf.ptd 第9頁 4245SS4---- 五、發明說明(5) 初始層,接著形成一多層内連線結構於支掉基板之上,之 後在支撐基板上形成多個開口 ,用以分別暴露出多層内連 線結構之底面的多個接合墊,然後配置一電子元件至多層 内連線結構之上,並且分別形成一接點於這些位於開口之 内的接合墊上。因此,本發明將可有效地提升電氣封裝體 之電性效能及散熱效能,並可降低電氣封裝體之厚度,以 符合電氣封裝體之小型化的需求。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易僅,下文特舉二實施例,並配合所附圖式,作詳細說 明如下: v【實施方式】 [第一實施例] _ 請依序參考第2 A〜2 G圖,其繪示本發明之第一實施例· 之電氣封裝製程的流程示意圖。 如第2A圖所示,提供一支撐基板202 ,其本身具有硬 質性、可導電性、低熱膨脹係數及高熱導性等特性,支撐 基板2 0 2之材質例如鐵、銘、鎳、銅、is、鈦、嫣、錯、 鉻及該等合金,並且支撐基板2 0 2之表面必須具有較高等 級的平坦度(c ο - p 1 a n a r i t y ),以利於後續製程在支#基 板2 0 2之表面製作微細線路。 如第2B圖所示,形成多個阻障層(barrier layer) 2 0 4於支撐基板2 0 2之上,其中阻障層2 0 4之材質係為導電 材質,例如為金,而形成這些阻障層2 0 4之目的將於下文 4 說明。
11 5JOtwf.ptd 第10頁 1245381--- 五、發明說明(6) 如第2 C圖所示,形成一多層内連線結構2 0 6於支撐基 板2 0 2之上,並覆蓋這些阻障層2 0 2。其中,多層内連線結 構206包括圖案化之多個導線層208、至少一介電層210及 多個導電孔道2 1 2 ,其中這些導線層2 0 8係依序重疊於支撐 基板2 0 2之上,而每一介電層2 1 0則配置於兩相鄰之導線層 2 0 8之間,且這些導電孔道2 1 2係分別貫穿這些介電層2 1 0 之一,而電性連接至少二導線層2 0 8 ,且這些導線層2 0 8及 這些導電孔道2 1 2係共同構成一内部線路,其係形成多個 接合墊208a於多層内連線結構206之頂面206a,且在多層 内連線結構2 0 6之底面2 0 6 b亦形成多個接合塾208b,其中 這些接合墊2 0 8 a係可由導線層2 0 8所形成·,或是由導電孔 道210所形成,第2C圖之接合墊2 0 8a係以後者作為代表, 即以導電孔道2 1 0來作為接合墊2 0 8 a。此外,導線層2 0 8之® 材質例如為銅、鋁及該等合金,而介電層2 1 0之材質例如 為氤化石夕(silicon nitride)、氧 4匕石夕(silicon oxide )或環氧樹脂(epoxy resin)等。 同樣如第2 C圖所示,若以電鍍製程來形成多層内連線 結構2 0 6之内部線路時,可直接藉由支撐基板2 0 2來提供習 知之電鍍線的功能,意即連接電源以提供電鍍所需之電 流。 同樣如第2 C圖所示,由於本發明可以利用液晶顯示面 板或積體電路等相關製程技術,來形成此一多層内連線結 構2 0 6於支撐基板2 0 2之上,使得多層内連線結構2 0 6之内_ 部線路的線寬及線距其範圍均可在1〜5 0微米的範圍之
1 1530twf. pt 第11頁 T245S81 五、發明說明(7) 間,且特別是在1〜數微米的範圍之間。因此,相較於習 知之第1圖所示之以有機材料為介電層材質的基板1 1 〇 ,此 處所製作出之多層内連線結構2 0 6將可提供更高密度的接 合墊及更微細的線路。此外,在形成多層内連線結構2 0 6 於支撑基板2 0 2之上的同時,更可配設被動元件(p a s s i v e component )(未繪示)於多層内連線結構206之内部或其 頂面2 0 6 a ,並電性連接於多層内連線結構2 0 6之内部線 路,或者是在多層内連線結構2 0 6之内部線路形成特殊繞 線來形成電容器(capacitor·)及電感器(inductor)等 被動元件。 如第2 D圖所示,例如以餘刻的方式,移除局部之支禮 基板2 0 2 ,即圖案化支撐基板2 0 2 ,用以形成多個開口 2 0 3,而這些開口 2 0 3係分別經由暴露出這些阻障層2 0 4, 而間接地暴露出這些接合墊2 0 8 b。值得注意的是,設置這 些阻障層2 0 4之目的即是在移除局部之支撐基板2 0 2時,即 圖案化支撐基板2 0 2時,預防蝕刻液不當地移除這些阻障 層204之上方的内部線路。此外,在第2F圖之電子元件218 (例如晶片)以覆晶接合的方式配置於多層内連線結構 206之頂面206a以前,尚可預先在這些接合墊208a上分別 形成一預銲塊2 1 4 (或一凸塊),以利於電子元件2 1 8之覆 晶接合製程。 、如第2 E圖所示,分別形成一絕緣層2 1 6於這些開口 203a之内壁上,但不形成絕緣層216於開口203b之内壁,· 且在形成絕緣層2 1 6之過程中,絕緣層2 1 6可位於支撐基板
1 1 530twf .ptil 第12頁 1245381--- 五、發明說明(8) 2 0 2之較遠離多層内連線結構2 0 6的一面,其中絕緣層2 1 6 之材質係可相同於常見之銲罩層(s ο 1 d e r丨n a s k )的材 質。 如第2F圖所示,配置至少一電子元件218於多層内連 線結構2 0 6之頂面2 0 6 a,並且電子元件2 1 8係可電性連接於 多層内連線結構2 0 6之内部線路,其中電子元件2 1 8例如為 晶片、被動元件或另一電氣封裝體,並且電子元件2 1 8之 電性連接至多層内連線結構2 0 6的方式例如為覆晶接合 (flip-chip bonding )、才丁、線接合(wire bonding )或 熱壓接合(thermal compression bonding )等。值得注 意的是,第一實施例僅以覆晶接合的方式,將一晶片電性 連接至多層内連線結構2 0 6來作為代表。 ^ 、如第2 G圖所示,分別形成一接點2 2 0於這些接合墊 2 0 8 b上,其中這些接點2 2 0例如銲球(s ο 1 d e r b a 1 1 )、針 腳(pin)或電極凸塊(electrode block),而完成電氣 封裝體2 0 0。值得注意的是,由於具有導電性之支撐基板 202係可提供作為較大之參考平面(reference plane), 例如電源平面(power plane)或接地平面(ground plane ),故可經由最底層之導線層2 0 8來直接電性連接支 撐基板2 0 2以外,更可經由這些位於開口 2 0 3 b之内的接點 2 2 0 b (僅繪示其一)來直接電性連接支撐基板2 0 2,而其 餘不需電性連接至支撐基板2 0 2的接點2 2 0 a,則分別經由 一絕緣層2 1 6來電性隔絕於支撐基板2 0 2,使得電氣封裝體φ 200具有較大之參考平面,因而相對提升電氣封裝體200之
I _ III ϊ ΙΙϋ I 11530t wf.prd 第13頁 I24^&1--- 五、發明說明(9) 電性效能。 同樣如第2 G圖所示,當這些接點2 2 0係為銲球時,可 將用來形成這些接點2 2 0之材料分別填入這些開口 2 0 2之 内,使得這些接點2 2 0將分別填滿其所對應之開口 2 0 3,並 電性連接至其所對應之接合墊2 0 8 b。此外,尚在分別配置 這些接點2 2 0於這些接合墊2 0 8 b之前或之後來進行切單作 業,用以分割出許多單顆電氣封裝體2 0 0 。 請參考第3圖,其繪示本發明之第一實施例的電氣封 裝體,其採用體積較小之接點的剖面示意圖。當電氣封裝 體2 0 1採用體積較小或針腳型態之接點2 2 0時,為了使這些 接點2 2 0能夠與此一具有導電性之支撐基板2 0 2相電性隔 離,可在分別製作這些接點2 2 0於這些接合墊2 0 8 b上的同 時,設計讓這些接點2 2 0之側緣均分別遠離這些開口 2 0 3之 内壁,或是設計增加這些開口 2 0 3之外徑,使得每一接點 2 2 0之側緣均分別遠離對應之開口 2 0 3的内壁。當然,此處 亦可增加某些接點2 2 0之體積,使得某些接點2 2 0能夠直接 連接至支撐基板2 0 2,即類似第2 G圖之接點2 2 0 b的情況, 但這樣的情況並未繪示於第3圖。 1第二實施例] 第一實施例係先形成一導線層於支摔基板之後,再形 成其餘之多層内連線結構,然而,第二實施例則是在形成 一具介電性之隔絕層以後,始形成其餘之多層内連線結 構。 丨 請依序參考第4 A〜4 Η圖,其繪示本發明之第二實施例
11 530twf. pul 第14頁 1245381--- 五、發明說明(10) 之電氣封裝製程的流程示意圖。 如第4A圖所示,提供一支撐基板302 ,其本身具有硬 質性、可導電性、低熱膨脹係數及高熱導性等特性,支撐 基板3 0 2之材質例如鐵、鈷、鎳、銅、鋁、鈦、鎢、錯、 鉻及該等合金,並且支撐基板302之表面必須具有較高等 級的平坦度,以利於後續製程在支撐基板3 0 2之表面製作 微細線路。 如第4 B圖所示,接著形成一隔絕層3 2 2於支撐基板3 0 2 上,並在隔絕層3 2 2上形成多個開口 3 2 2 a。其中,隔絕層 3 2 2之材質係為介電材質。 如第4 C圖所示,·同時形成多個阻障層3 0 4 a及多個導電 孔道3 0 4 b於支撐基板3 0 2之上,其中這些阻障層3 0 4 a係配 置於隔絕層3 2 2上,而這些導電孔道3 0 4 b則分別位於這些 開口 3 2 2 a之内。此外,阻障層3 0 4 a及導電孔道3 0 4 b之材質 係為導電材質,例如金。 如第4 D圖所示,形成一多層内連線結構3 0 6於支撐基 板3 0 2之上。由於多層内連線結構3 0 6之組成結構已說明於 第一實施例,於此不再重複贅述。同樣地,多層内連線結 構3 0 6之頂面3 0 6 a係形成多個接合墊3 0 8 a,且在多層内連 線結構3 0 6之底面3 0 6 b亦形成多個接合墊3 0 8 b。值得注意 的是,若以電鍍製程來形成多層内連線結構3 0 6之内部導 電線路時,可直接藉由支撐基板302及這些導電孔道304b 來提供習知之電鍍線的功能,意即連接電源以提供電鍍所 需之電流。 .
i1530rwf.prd 第15頁 I2453S1___ 五、發明說明(11) 如第4 E圖所示,移除局部之支撐基板3 0 2 ,即圖案化 支撐基板3 0 2 ,用以形成多個開口 3 0 3 ,其中例如以超音波 穿孔、雷射燒孔或蝕刻等方式來形成多個開口 3 2 3於隔絕 層322上,而這些開口 323分別連通於這些開口 303 ,並分 別經由暴露出這些阻障層304a及這些導電孔道304b,而間 接地暴露出這些接合墊308b。同樣地,在第4G圖之電子元 件3 1 8 (例如晶片)係以覆晶接合的方式,配置於多層内 連線結構3 0 6之頂面3 0 6 a以前,尚可預先在這些接合墊 3 0 8 a上分別形成一預銲塊3 1 4 (或一凸塊),以利於電子 元件3 1 8之覆晶接合製程。值得注意的是,可利用具有導 電性之支撐基板3 0 2來取代習知之電鍵線(p 1 a t e d 1 i n e ),而在多層内連線結構3 0 6之頂面3 0 6 a的這些接合墊 g 3 0 8 a上形成預銲塊3 1 4等。 如第4 F圖所示,分別形成一絕緣層3 1 6於這些開口 3 0 3 a及開口 3 2 3 a之内壁上,但不形成絕緣層3 1 6於開口 303b及開口323b之内壁,且在形成絕緣層316之過程中, 絕緣層3 1 6可位於支撐基板3 0 2之較遠離多層内連線結構 3 0 6的一面,其中絕緣層3 1 6之材質係可相同於常見之銲罩 層(solder mask)的材質。 如第4G圖所示,配置至少一電子元件318於多層内連 線結構3 0 6之頂面3 0 6 a,並且電子元件3 1 8係可電性連接於 多層内連線結構3 0 6之内部線路,其中電子元件3 1 8例如為 晶片、被動元件或另一電氣封裝體,並且電子元件3 1 8其g丨 電性連接至多層内連線結構3 0 6的方式例如為覆晶接合、
11530rwf.ptd 第16頁 J24S3S4--- 五、發明說明(12) 打線接合或熱壓接合等。同樣地,第二實施例仍僅以覆晶 接合的方式,將一晶片電性連接至多層内連線結構3 0 6來 作為代表。 如第4 Η圖所示,分別形成一接點3 2 0於這些接合墊 3 0 8 b上,其申這些接點3 2 0例如銲球、針腳或電極凸塊, 而完成電氣封裝體3 0 0。同樣地,由於具有導電性之支撐 基板3 0 2係可提供作為較大之參考平面,例如電源平面或 接地平面,故可經由這些位於開口 3 0 3 b之内的接點3 2 0 b (僅繪示其一)來直接電性連接支撐基板3 0 2,而其餘不 需電性連接至支撐基板3 0 2的接點3 2 0 a,則分別經由一絕 緣層316來電性隔絕於支撐基板3 0 2,使得電氣封裝體300 具有較大之參考平面,因而相對提升電氣封裝體3 0 0之電 性效能。 同樣如第4 Η圖所示,當這些接點3 2 0係為銲球時,可 將用來形成這些接點3 2 0之材料分別填入這些開口 3 0 2之 内,使得這些接點3 2 0將分別填滿其所對應之開口 3 0 3,並 電性連接至其所對應之接合墊3 0 8 b。此外,尚可在分別配 置這些接點320於這些接合墊308b之前或之後,來進行切 單作業,用以分割出許多單顆電氣封裝體3 0 0 。 在本發明之第一實施例及第二實施例中,本發明之電 氣封裝體除可封裝單個電子元件以外,亦可封裝多個電子 元件,並可經由上述之多層内連線結構之内部線路而相互 電性連接,所以電氣封裝體亦可應用於多重晶片模組 t (Multiple Chip Module ,MCM)及系統於單一封裝
11530twf.ptd 第17頁 124-5381--- 五、發明說明(13) (System In Package ,SIP)。 綜上所述,本發明之電氣封裝體及其製程至少具有下 列優點: (1 )本發明乃是利用一具有硬質性、低熱膨脹係數 及具有導電性之支撐基板來作為製程之初始層,故可減少 電氣封裝體之翹曲現象。 (2 )本發明乃是利用一具有導電性之支撐基板來作 為電氣封裝體之電源平面或接地平面,並可直接利用接點 來連接支撐基板,故可提升電氣封裝體之電性效能。 (3 )相較於習知之介電芯層,本發明乃是利用一具 有相對高熱導性(thermal conductive)之支樓基板來作 為電氣封裝體之主要結構,故可提升電氣封裝體之散熱效 能。 ❸ (4 )相較於習知之基板的介電芯層,本發明不需要 在介電芯層上形成細微的貫孔來製作鍍通孔道(P T Η ), 故可相對提升支撐基板上之多層内連線結構的佈線密度, 因而相對提升電氣封裝體之電性效能。 (5 )在本發明之第二實施例中,本發明係可利用具 有導電性之支撐基板來取代習知之電鍍線(ρ 1 a t e d 1 i n e ),並經由支撐基板,而在多層内連線結構之頂面的這些 接合塾上形成電鍵層、預銲塊(pre-solder)或凸塊 (bump )等。 雖然本發明已以二較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精
115 301 w f. p r d 第18頁
11530twf.pt d 第19頁 I2453&1_-_ 圖式簡單說明 第1圖繪示習知之一種覆晶球格陣列型之電氣封裝體 的剖面示意圖。 第2 A〜2 G圖繪示本發明之第一實施例之電氣封裝製程 的流程不意圖。 第3圖繪示本發明之第一實施例的電氣封裝體,其採 用體積較小之接點的剖面示意圖。 第4 A〜4 Η圖繪示本發明之第二實施例之電氣封裝製程 的流程示意圖。 【圖式標示說明】 1 0 0 :電氣封裝體 1 1 0 :基板 1 1 2 ·•頂面 1 1 4 :底面 1 1 6 a :凸塊塾 1 1 6 b :銲球墊 1 2 0 :凸塊 130 :晶片 1 32 :主動表面 134 :背面 136 :晶片墊 140 :銲球 1 5 0 :底膠 2 0 0、2 0 1 :電氣封裝體 _ 2 0 2 :支撐基板
11530twf.ptd 第20頁 I24S3B1 圖式簡單說明 2 0 3、 2 0 4 : 2 0 6 ·· 2 0 6 a 2 0 6 b 2 0 8 ·· 2 0 8 a 2 0 8 b 2 10 21 2 2 14 2 16 2 18 2 2 0 ^ 3 0 0 : 3 0 2 : 3 0 3 ^ 3 0 4 a 3 0 4 b 3 0 6 : 3 0 6 a 3 0 6 b 3 0 8 a 3 0 8 b 203a '203b :開口 阻障層 多層内連線結構 :頂面 :底面 導線層 :接合墊 :接合墊 介電層 導電孔道 預銲塊 絕緣層 電子元件 2 2 0 a、2 2 0 b :接點 電氣封裝體 支樓基板 3 0 3 a、3 0 3 b :開口 :阻障層 :導電孔道 多層内連線結構 頂面 底面 接合墊 接合墊 _
11530rwf.ptd 第21頁 Ι2453»ί- 圖式簡單說明 3 1 4 :預銲塊 3 1 6 :絕緣層 3 1 8 :電子元件 3 2 2 :隔絕層 322a :開口 323、 323a、 323b:開口 3 2 0 :接點
第22頁
Claims (1)
- J2453-81___ 六、申請專利範圍 1 . 一種電氣封裝體,至少包括: 一多層内連線結構,具有一頂面及對應之一底面,且 該多層内連線結構更具有一内部線路,而該内部線路更具 有複數個接合墊,其位於該多層内連線結構之該底面; 至少一電子元件,配置於該多層内連線結構之該頂 面,並電性連接於該多層内連線結構之該内部線路;以及 一支撐基板,其材質係為導電材質,且該支撐基板係 配置於該多層内連線結構之該底面,而該支撐基板更具有 多個第一開口 ,其分別暴露出其所對應之該些接合墊之 --- ^ .如申請專利範圍第1項所述之電氣封裝體,更包括 一隔絕層,其材質係為絕緣材質,其中該隔絕層係配置介 於該多層内連線結構及該支撐底板之間,且該隔絕層更具 有複數個第二開口 ,其分別暴露出其所對應之該些接合墊 '— ° '3 .如申請專利範圍第1項所述之電氣封裝體,其中該 些接合塾分別具有一阻障層,其分別配置介於該些接合塾 之表面,且該些第一開口更分別暴露出該些阻障層。 4.如申請專利範圍第1項所述之電氣封裝體,其中該 電子元件係為一晶片、一被動元件及另一電氣封裝體其中 — ° 5 .如申請專利範圍第1項所述之電氣封裝體,其中該 支撐基板之材質係為金屬及合金其中之一。 6 .如申請專利範圍第1項所述之電氣封裝體,更包括1153〇twf.pfd 第23頁 ,-124.538-1____ 六、申請專利範圍 複數個接點,其分別經由其所對應之該些第一開口 ,而連 接至其所對應之該些接合墊之一。 7.如申請專利範圍第6項所述之電氣封裝體,其中該 些接點之型態係為銲球、針腳及電極凸塊其中之一。 8 ·如申請專利範圍第6項所述之電氣封裝體,其中該 些接點之至少一係填滿其所對應之該些第一開口之一,而 電性連接至該支撐基板。 9.如申請專利範圍第6項所述之電氣封裝體,其中該 些接點係分別填滿其所對應之該些第一開口 ,而該支撐基 板更具有至少一絕緣層,其.配置於該接點之一及其所對應 該開口之間。 10.如申請專利範圍第1項所述之電氣封裝體,其中該 電子元件係以覆晶接合、打線接合及熱壓接合其中之一的 方式,電性連接於該多層内連線結構之該内部線路。 l· 1 . 一種電氣封裝製程,至少包括下列步驟: 提供一支撐基板,其材質係為導電材質; 形成一多層内連線結構於該支撐基板之上,且該多層 内連線結構具有一内部線路,而該内部線路更具有複數個 接合墊,其位於該多層内連線結構之接近該支撐基板之一 面; 形成複數個第一開口於該支撐基板上,而該些第一開 口係分別暴露出其所對應之該些接合墊之一;以及 配置至少一電子元件於該多層内連線結構之遠離該支4 撐基板之一面,且該電子元件係電性連接於該多層内連線11530twf.pt d 第24頁 1245381___ 六、申請專利範圍 結構之該内部線路。 1 2 ·如申請專利範圍第1 1項所述之電氣封裝製程,其中 該支撐基板之材質係為金屬及合金其中之一。 1 3 ·如申請專利範圍第1 1項所述之電氣封裝製程,其中 在形成多層内連線結構之時,更包括在每一該些接合墊及 該支撐基板之間形成一阻障層。 1.4,如申請專利範圍第1 1項所述之電氣封裝製程,其中 該電子元件係為一晶片、一被動元件及另一電氣封裝體其 中 -— 〇 I 5 ·如申請專利範圍第1 1項所述之電氣封裝製程,更包 括分別形成一接點於該些接合墊,且該些接點係分別位於 該支撐基板之該些第一開口中。 _ 1 6 .如申請專利範圍第1 5項所述之電氣封裝製程,其中Μ 該些接點之型態係採用銲球、針腳及電極凸塊其47之一。 1 7.如申請專利範圍第1 5項所述之電氣封裝製程,其中 該些接點之至少一係填滿其所對應之該些第一開口之一, 而電性連接至該支撐基板。 1 8.如申請專利範圍第1 5項所述之電氣封裝製程,其中 更包括先形成至少一絕緣層於該些開口之一的内壁,且對 應之該接點係填滿該開口 ,並經由該絕緣層而與該支撐基 板相電性隔離。 1 9.如申請專利範圍第1 1項所述之電氣封裝製程,更包 括形成一隔絕層於該支撐底板之上,且該多層内連線結構4 係形成於該隔絕層之上,接著更包括形成複數個第二開口11 5 301 w f. p t d 第25頁 124^1- 六、申請專利範圍 於該隔絕層上,且該些第二開口係分別連通於其所對應之 該些第一開口之一,而分別暴露出其所對應之該些接合墊 --- 0 2 0 ·如申請專利範圍第1 1項所述之電氣封裝製程,其中 在配置該電子元件於該多層内連線結構之遠離該支撐基板 之該面時,該電子元件係以覆晶接合、打線接合及熱壓接 合其中之一的方式,而電性連接於該多層内連線結構之該 内部線路。11530twt'. pt d 第26頁
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JP4787559B2 (ja) | 2005-07-26 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2007109825A (ja) * | 2005-10-12 | 2007-04-26 | Nec Corp | 多層配線基板、多層配線基板を用いた半導体装置及びそれらの製造方法 |
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-
2003
- 2003-08-14 TW TW092122342A patent/TWI245381B/zh not_active IP Right Cessation
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2004
- 2004-06-09 US US10/709,954 patent/US7071569B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102844861A (zh) * | 2010-04-29 | 2012-12-26 | 德州仪器公司 | 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 |
CN102844861B (zh) * | 2010-04-29 | 2016-01-13 | 德州仪器公司 | 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 |
Also Published As
Publication number | Publication date |
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US7071569B2 (en) | 2006-07-04 |
US20050035464A1 (en) | 2005-02-17 |
TW200507204A (en) | 2005-02-16 |
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