TWI244713B - Electric circuit device - Google Patents

Electric circuit device Download PDF

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Publication number
TWI244713B
TWI244713B TW093124778A TW93124778A TWI244713B TW I244713 B TWI244713 B TW I244713B TW 093124778 A TW093124778 A TW 093124778A TW 93124778 A TW93124778 A TW 93124778A TW I244713 B TWI244713 B TW I244713B
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TW
Taiwan
Prior art keywords
conductive pattern
pattern
circuit
circuit device
conductive
Prior art date
Application number
TW093124778A
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English (en)
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TW200512855A (en
Inventor
Atsushi Kato
Atsushi Nakano
Original Assignee
Sanyo Electric Co
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Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200512855A publication Critical patent/TW200512855A/zh
Application granted granted Critical
Publication of TWI244713B publication Critical patent/TWI244713B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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Description

1244713 九、發明說明: 【發明所屬之技術領域】 本發明係有關一種電路裝置,尤其是具有可抑制導電 圖案間之漏洩電流(leakage current)之構造的電路果置 【先前技術】 " 參照第6圖說明習知型之半導體裝置1〇〇之構成。身 6圖(A)為半導體裝置100之俯視圖,第6圖(b)為其= 圖(參照專利文獻1)。 ^ σ
參照第6圖⑷,在半導體⑽之中央部係形成有由導 電材料所成之陸地(land) 102,而在陸地1〇2周圍近接有多 數個導線ΗΠ之-端。導線1〇1之一端係透過金屬細線^ 與半導體元件HM作電性連接,另—端從封裝樹脂1〇3中 露出。封裝樹脂103係具有將半導體元件1〇4、陸地⑽ 及導線101封裝而一體地支撐的作用。 專利文獻1 ··曰本專利特開平u_34〇257號公報
但是,於上述半導體裝置1〇〇中,當電位差大之導線 101彼此接近時,兩者間有發生漏浅電流之虞。尤盆是合 一方之導線101的阻抗較高時,此_流流入阻抗較; 之導線101,以致有使構成於震置内部的電路 變之問題。 知土又 【發明内容】 本电明係叛於上述問題而開發者,主要目的為提供― 種具有可抑制圖案間之漏@電流之構造的電路裝置。 本么月之毛路裝置係於具有電路元件及導電圖案之電 316192 5 1244713 路I置中,具備:第1導電圖幸 之高阻抗之輸入端子;第2導_;連接:上述電路元件 1導電圖案;以及保護導電圖宰^ =於接近上述第 圖案與上述第2導電圖案之間:係延伸於上述第1導電 路裝置係採用電位最接近於 圖案之上述導電圖案作為上述保護導電圖案。 h 本發明之電路裝置係由 1導電圖案。 4保邊泠包圖案圍繞上述第 再者,本發明之電路裝置係具有 ( 配線層所成之多厗献括a 弟1配線層及弟2 第2配構造,於上述第1配線層或上述 弟配線層形成上述保護導電圖案。 面本發明之電路裝置係露出上述導電圖案之背
:裝而错由料樹脂將上述電路㈣及上述導電圖案予I 於之電路裝置之上述第1導電圖案係連接 於UP放大益之輪入端子。 地電2連ί發明之電路裝置之上述保護導電圖案係舆接11 (發明之效果) 伸有保確2月之電路裝置,在電位不同之導電圖案間延 θ可改^電圖案’由此可抑制裝置内部之漏沒電流。如 ^ϋ 置中所内建之電路的特性。而且,在安裝基 圖案略漏茂電流對策之構成’故可簡化安裝基板之 316192 6 1244713 【實施方式】 iO之構成。第1 圖(B)及第1圖(C) 參知、第1圖說明本形態之電路裝置 圖(A)為電路裝置1〇A之俯視圖,第1 為其剖視圖。 路元:二弟1圖⑷’本形態之電路農置10係形成具有1 ::件U及預期導電圖案12’且樹脂成型成一體之構成 第導^備:與電路Μ13之高阻抗之輸人端子相連 電圖案12Α;以及設於接近^導電圖案12
2導電圖案12Β。此外,且備在篦1这给。* 卑 ,、甭在弟1及弟2導電圖案間延 伸之保護導電圖案12C,而形成可防+筮】+ θ也 〜风j防止苐1導電圖案12/ :弟2導電圖案咖間之_流之構成。以下說明各元 件之細節及相關構成。 導電圖案12A、第2導電圖案12B及保護導電圖 二12C係由銅等金屬所構成。而此等導電圖案η係藉由 真充於以姓刻所形成之分離溝19的封㈣㈣予以分離。 電路元件13在此係由半導體元件UA及晶片元件UB 所構成。而且,可採用LSI(Large Scale _㈣大型 積體電路)晶片、裸電晶體晶片、二極體等主動元件(active element)作為電路元件13。再者,亦可採用晶片電阻、晶 片電谷]或電感等被動元件(passive element)作為電路元件 半導體元件13A係將其背面固接於由導電圖案I]所 ,成之晶粒墊(DiePad)。而且,半導體元件UA之表面的 電極與由導電圖案12所構成之接合焊墊(Bonding Pad)係 透過金屬細線15作電性連接。此外,半導體元件13A亦 316192 7 1244713 封裝樹脂二由= 接於導電圖案12。 形成之敎 ’、糟由射出成型法(injection molding) 形成之熱硬化性樹r所2由轉,主成型雄咖如 整體裳置之作用之外裝:脂18除了具有封農 能。表昭第1 mm、 有機械性支撑整體裝置之功 露出於()’封裝樹脂U係使導電圖案12之背面 案12、。邛’而封裝電路元件13、金屬細線15及導電圖《 形成:二電ΓΓ圖案1⑽ 16 。芸° 17之部位之外,係以由樹脂所成之光阻劑 :=::::7係—料所構成,-成 ^=:12具:本㈣優點亦即可抑制漏 麥知弟1圖⑷之第1領域A1,第1導電圖案i2A# g 透驗屬細線15與半導體元件13A作電性連接。而^糸讀 ::圖案12A與其他導電圖案比較之下,係為阻抗 較冋之導電圖案。舉例而言,第β電圖案i2A : ^〇P^Al(0perati〇nal 兩入j或非反轉輸人部。由此,第i導電圖案12A之阻 非常高’例如為數十萬Ω至數百萬Ω左右。換言之,: ==Γ2Α之電流非常小。具體上,流至連接 輸入端的第1導電圖案以之電流的値,例如 316192 8 1244713 為數微安培左右。在此第!導電圖案12A係連接於為扣 之半導體元件13A,但是,亦可連接於上述之其他電路_ 件13。 兀
第2導電圖案12B係設於接近上述第丨導電圖安 12A。此第2導電圖案12β係電位與上述f i導電圖案pi 不同之導電圖案。例如可採用電位較第!導電圖案12八為 高之圖案’或電位較第i導電圖案12A為低的圖案為第’、2 導電圖案12B。例如可採用施加數十伏特之電壓之 為第2導電圖案12B。 如此,第1導電圖案12Α與第2導電圖案12Β之 不同。因此,由此電位差’會有漏浅電流自第2導電二 12Β流入第!導電圖案12Α之虞。當考慮到ρ ; 12Α之阻抗較高而第2導電圖案UB之電位較高开 時,此問題更為顯著。其理由為因漏洩電流恐引起運曾龙 大器之錯誤動作所致。因此,在本發明中係藉由保護= 圖案12C來解決此問題。 保護導電圖案12C係延伸於第j導電圖案12 導電圖案12Β之間,係為可抑制第】導電圖案以鱼 導電圖案i2B間發生之漏茂電流之導電圖案。於此:伴 導電圖案Μ係直線式延伸於第U_fi2A = 電圖案⑽之間。保護導電圖案12C係採用較第 案㈣更接近於第!導電圖案12A電位之 、。:圖 適當的是,構成電路裝置1〇之導電圖案12之中:、加 用電位最接近第!導電圖案12A之導電圖案η作為保^ 316192 9 1244713 導電圖案Uc。再者, 於裝置之電路元件13作圖案12C亦可採用與内建 電路裝置内::Λ接之導電圖案12。 之導電圖案叫可自4:〜接近第1導電圖案μ 案-之電位。具體自而;路 側的導電路,透過外部電極17 置ig之基板 i2c。於此情形下,保護導電圖幸 電圖案 件13連接。L未必需要與電路元 伸於第1導電时12A=時’保護導電圖案I2C可僅由延 木圖案12A與第2導雷 構成即可。 电圖案12B之間的配線部 12A:::用】ί:大大器之輸入端子作為第1導電圖案 ㈣^ 器之輸入電位設定為較小時,佯護 再風由電位較咼之第2導電圖幸12B内筮、、曾& 通漏_時,其漏力電流係 『電=此外’如上所述,第1導電圖案^與= 浅電流:、 < 電位近似,因此基本上兩者間不會產生漏 二…第1圖(A)之第2領域A2,說明其他用以解決因 漏洩電流引起之問題的構成。於此,以圍繞第i導電圖案 12A ^圍的方式形成保護導電㈣沉。藉由此構成,可 更加—提高防止漏洩電流流入第1導電圖案12A的效果。此 外:第1導電圖案12A被不同電位之第2導電圖案12B圍 繞時,亦可藉由此構成防止漏洩電流流入。於此,環狀保 316192 10 1244713 護導電圖案12C係盥雷敗&杜η此+ 你^、包路兀件13作電性連接 , 如上所=電路裝置之外部引入電位。~ 麥照第1圖(Α)之第3領域Α3,說明 漏洩電流引起之門$沾姐+ /、用以解決因 t之問7ί|的構成。於此,保護 透過配線部12D白八…ο W电圖案12c係 民丨UD自分開的導電圖案12 導電圖案以之導電圖案,會有自第〗='弟1 荦!2C。在I Γ 伸,即可形成保護導電圖 L 在此,亦可使用金屬細線15代替由導電圖宰。 所成之配線部12D。 〒电闺茶12 蒼^第1圖(C) ’在此雷技分生 件UA及晶片元#1^此u #13係採用半導體元 “ 件 此,亦可使多數個電路元件η 内建於電路裝置10Α。 几件13 參照第2圖說明其他形態之電 2圖(Α)為電路梦w ^。弟 J巧电路4置10B之俯視圖,第2圖⑻為 此圖所示之電路妒詈】# 見圖。 ,πΛ 基本構成如同第1圖所示之 主說明之。 電3案12之延伸構造。以此不同處為· 參照第2圖⑷之第4領域Α4, =㈣於作為電路元件13之半導體元件S3 方。位於此領域Α4之電位接近第^電圖案ΐ2Α 圖案12Ε係在平面上位於夹 ^ 电 雕而 >,馀1、曾; 干^體兀件13Α的位置。具 肢而吕,第1導電圖案12Α及電 案12Ε係位於電路裝置】〇jB 口 ae φ ^ ^ 斤相對之周邊部附近。於本發' 明中,透過延伸於半導體开 ^ 干令骽兀件13A下方之配線部12D,可 316192 11 1244713 將保護導電圖案12c盘導带 並非排除配置有電路元件Γ3=12Ε作電性連接。亦即, 電圖案彼此直線連接。 項域而拉入圖案,而可將導 第首2干_之第5領域Α5 ’延伸於第1導電圖安 12Α與弟2導電圖案12β間的保 ^圖木 路元件13作電性連接。亦即 0木120並不與電 延伸為配線部的部分,且透¥電圖案12C係形成. 之外部連接。藉由電極17與電路裝置⑼· 案…即使沒有電位=第在1電導^請内部之導電圖· 12之情开,下h丄 導電圖案12A之導電圖案Φ 之^形下,亦可由外部獲得其電位。 簽照第2圖(Β),說明電路穿
圖案12係由覆蓋樹脂24二置在:之剖面構造。導電 固接半導體元件13Α。藉由此H此覆盘樹脂24之表面 等電路元件u之領域成’在配置半導趙元件13A 配線密度。此外,盥電路元件”於導電圖案’因此可提高 圖宰U上面… 作電性連接之部位的導電 案2上面係由覆蓋樹脂“露出。於此,成為 之領域的導電圖案12上面從覆蓋樹㈣中露出/ 3圖圖說明其他形態之電路農置1〇C之構成。第 圖(A)為電路裝置10C之俯ϋρι ^ 此罔所-々币 圖,弟3圖⑻為其剖視圖。 路路裝置loc之基本構成如同第1圖所示之電 t置,不同處在於具有多數配線層。以此不同處為 王祝明之。 參照第3圖㈧,上層之配線層之第1配線層2〇係以 層配線層之f 2配線層21係以虛線表示。參 316192 12 1244713 照此圖之第6領域A6,第1導電圖案〗2A、第2導電圖案 12B及保護導電圖案12C係由第!配線層2〇形成。如此, 由第1配線層20所成之第i導電圖案12A與第2導電圖 案12B之間發生之漏洩電流,可由相同地由第1配線層2〇 所成之保護導電圖案12C抑制。 艾…、同圖之第7領域A7,於此,第丨導電圖案12八 及第2 ‘包圖案丨2B係由第2配線層別構成,保護導電 圖案12C則由第2 g己線層構成。亦即,參照第3圖⑻,可 由下層之第2配線層21構成之保護導電圖案進行抑 制上層之第1配線層20彼此之漏洩電流。於此之保護導電 圖^12C亦可透過連接部23與第1配線層20及電路元件 ^電性連接。再者,於此處之保護導電圖案12C亦可盘 弟1配線層20及電路元件13不作電性連接。 、 及第之第8領域A8’在此,第1導電圖案以 配線層h構成之Γ绩係由第1配線層2〇構成。而藉由第2 此,電位心 2D拉人保護導電圖案咖。因 *形成二的… 參昭楚/層1之配線部12D來拉入圖案。 之第1 Γ ®(B) ’於此係具有由透過絶緣層32所晶戶 之弟1配線芦^ 曰以所豐層 1配線層20 ^第2西令配秦層21構成的2層配線層。第 接部23而作電1連ΤΙ21係可透過貫穿絶緣層32之連 3層以上之配ΙΓ造其中,配線層之構造亦有可能構成 316192 13 1244713 於上述說明中,係說明用以 彼此之漏祕之構成,t缺亦;I上弟1配線層20 層之第2配線層2"皮此之漏 20形成保護導電圖案12C,藉此可 、弟配線層 此之漏_。再者,於第::二 =错此亦可防止第!配線層2〇彼此之 案 亦有可能於第!配線層20及第又, 様形狀之保護導電圖案12C,因而可;=成同 止效果。 灵加挺阿漏洩電流防 ^照第4圖說明其他形態之電路裝置_之構成。於儀 表不。,J面之電路裝置聰之基本構成係與第:
裝3f:〇C相同’:同處在於具有支撐基板31。此I
土 可使用玻璃環氧基板等之樹脂製基板、陶究A 板、金屬基板等衆知之基板。 "^基 參照第5圖之剖視圖,說明安裝於安裝基板25之電路 、1〇A之構成。於此’係以於第1圖所說明之電路穿置 10A加以說明’但是’以下之構成亦可適用於以圖i 所說明之電路裝置10。 /、他圖式 透過形成於導電圖案12背面之由焊料構成之外部電 ’電路裝置1GA係固接於形成於安裝基板25表面之 導電路j6。第1導電圖案12Λ係透過外部連接電極17, 連接於第1導電路26A。而第2導電圖案12B係透過連接 電極17連接於第2導電路26B。再者,保護導電圖案pc 係透過外部電極17連接於安裝基板25側之保護導電路 316192 14 1244713 26C於此,安裝基板25側之保護導電路26匸未必需要連 接於保護導電圖案12C,而亦可連接於電位近於第i導電 圖案12A之其他部分。 於電路裝置H)A内部設置保護導電圖案12C,藉此可 抑制向第!導電圖案12A流入漏浅電流。再者,於安裝基 板25側亦設置保護導電路26c,故可提高此效果。具體而 吕’即使在有灰㈣附著於㈣路26表面之情形下,亦可 抑制導電路26彼此間發生的漏洩電流。 【圖式簡單說明】 之電路裝置之俯視圖(A)、剖視圖 弟1圖係表示本發明 (B)、剖視圖(〇。
2圖係表示本發明 (B) 〇 之電路裝置之俯視圖(A)、剖視圖 第 (B)。 圖係表示本發明 之電路裝置之俯視圖(A )、剖視圖 第4圖係表示本發明
剖視圖 冰 〃 &乃炙冤路裝置之剖視圖。 弟5圖係表示本發明 咕 知月之甩路裝置之剖視圖。 第6圖係表示習知之雷 又冤路裹置之俯視圖(A) 【主要元件符號說明】 10A 電路裝置 12A 第1導電圖案 12C 保護導電圖案 13A、104半導體元件 12 ' 12E導電圖案 第2導電圖案 12D 配線部 13 B 晶片元件 316192 15 1244713 15 > 105 金屬細線 16 光阻劑 17 外部電極 18、 103 封裝樹脂 19 分離溝 20 第1配線層 21 第2配線層 23 連接部 24 覆蓋樹脂 25 安裝基板 26 導電路 26A 第1導電路 26B 第2導電路 26C 保護導電路 31 支樓基板 32 絕緣層 100 半導體裝置 101 導線 102 陸地 A1 第1領域 A2 第2領域 A3 第3領域 A4 第4領域 A5 第5領域 A6 第6領域 A7 第7領域 A8 第8領域 16 316192

Claims (1)

1244713 十、申請專利範圍·· 1· 一種電路裝置,為具有雷 第1導電圖牵電圖案者,係具備: 輸入端子,· 路兀件之咼阻抗之 係叹於接近上述第j導電圖案;以及 係延伸於上述第1導電圖案與第2 第2導電圖案 保護導電圖案 導電圖案之間。 2. 如申請專利範圍第】項之電路裝置,其中, * 採用電位最接近於上述第1 案’作為上述保護導電圖案。圖案之上述導電圈· 3. 如申請專利範圍第1項之電路裝置,其中, 上述第1導電圖案係由上述保 4·如申請專利範圍第 電圖案所圍繞。 ^ J靶固弟1項之電路裝置,其中, 係具備由第1配線層及第2 声、 層構造, 此踝層構成之多層配線 且於上述第】配線層或上述第2配 護導電圖案。 、9形成上述保 5. 如申:專利範圍第1項之電路裝置,其中, 露出上述導電圖案之背面,而 電路元件及上述導電圖案予以封裝。f相月曰將上述 6. 如申請專利範圍第1項之電路裝置,其中, 上述第1導電圖案係連接於運算放大 7 ·如申請專利銘Ifl楚,s 輪入端子。 τ月寻W靶圍弟1項之電路襞置,其中, 上述保護導電圖案係與接地電位連接。 316192 17
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI404190B (zh) * 2005-04-11 2013-08-01 Stats Chippac Ltd 具有非對稱配置晶粒與模製之堆疊封裝之多重封裝模組

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552639A (en) * 1980-09-01 1996-09-03 Hitachi, Ltd. Resin molded type semiconductor device having a conductor film
JP3172549B2 (ja) * 1991-09-11 2001-06-04 キヤノン株式会社 高圧電源回路基板
JPH0766564A (ja) * 1993-08-25 1995-03-10 Advantest Corp 多層プリント配線基板におけるガード電極の構造
JPH1098291A (ja) * 1996-09-24 1998-04-14 Minolta Co Ltd 微小電流端子を有した集積回路の実装構造
US6420779B1 (en) * 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
JP3822768B2 (ja) * 1999-12-03 2006-09-20 株式会社ルネサステクノロジ Icカードの製造方法
JP2001313363A (ja) * 2000-05-01 2001-11-09 Rohm Co Ltd 樹脂封止型半導体装置
US6548757B1 (en) * 2000-08-28 2003-04-15 Micron Technology, Inc. Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies
US6768386B1 (en) * 2003-04-22 2004-07-27 Lsi Logic Corporation Dual clock package option
US6791177B1 (en) * 2003-05-12 2004-09-14 Lsi Logic Corporation Integrated circuit packaging that uses guard conductors to isolate noise-sensitive signals within the package substrate

Cited By (1)

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TWI404190B (zh) * 2005-04-11 2013-08-01 Stats Chippac Ltd 具有非對稱配置晶粒與模製之堆疊封裝之多重封裝模組

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KR100611298B1 (ko) 2006-08-10
JP4330411B2 (ja) 2009-09-16
CN1602137A (zh) 2005-03-30
CN100417309C (zh) 2008-09-03
KR20050030113A (ko) 2005-03-29
US20050092508A1 (en) 2005-05-05
TW200512855A (en) 2005-04-01

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