TWI281732B - IC package body, its manufacturing method and integrated circuit apparatus - Google Patents

Abstract

The purpose of this invention is used for IC package body to strengthen the electric potential variation endurance of synchronized switch of the IC chip for the power supply or the grounding and improve the heat sink characteristic. The invention is an IC package body. The structure has a substrate for carrying IC chip and a covering portion to cover the said IC chip carried on the substrate. Both the said substrate and the said covering portion or one of them has stack layer with single or plural power supply layer and grounding layer. The inbuilt single or plural capacitors are built by installing oppositely the said power supply layer and the said grounding layer separated with high dielectric body layer. The IC package body has a structure to make the IC chip contacting inside conductor layer and outside conductor layer combined by the heat conducting body (heat conducting hole). It has a structure to shelter the conductor portion.

Description

1281732 IX. DESCRIPTION OF THE INVENTION: I [Technical Field of the Invention] Field of the Invention The present invention relates to a 1C package of an integrated integrated circuit (IC: IC), which is improved by an internal structure thereof. Anti-synchronous switching of 5-hole resistance, electromagnetic interference (Emi: Electromagnetic Intrefaence) prevention, or heat dissipation characteristics 1 (: package, its manufacturing method, and integrated circuit device. 10 BACKGROUND OF THE INVENTION 15 - Generally, in 1C wafer Built in the integrated circuit device of the sealed body, in order to strengthen the power supply or grounding, a capacitor is arranged between the power supply and the ground to reduce the synchronous switching noise. The synchronous noise switching is performed by the internal facial synchronization action of the IC. For example, the synchronous conduction is performed to change the voltage level of the power supply or the ground to cause the circuit to malfunction. In addition, a heat spreader structure is known for the thermal countermeasures of the package. The related technology for the substrate on which the 1C chip is mounted is to reduce the synchronous switching. The noise and the noise have a multilayer board of a built-in capacitor formed by the power layer and the ground layer being disposed opposite to each other through the insulating layer (for example, patent text) 1), the decoupling capacitor composed of the fruit-based electric device is cried and strong; the spliced multi-layer circuit substrate of the mouth is used (for example, Patent Document 2), and the lower electrode is prevented from the + soil substrate region. The dielectric integrated circuit of the board and the upper electrode constitute a semiconductor integrated circuit of Thai + (for example, #电谷器 patent document 3), and has a conductive layer of 20 1281732 = via a dielectric body as a power source. The printing of the capacitor laminate of the layer and the ground layer is reversed, for example, in the patent document. It is a high-level signal, and the multilayer wiring circuit substrate (10) is provided in the power supply layer and the connection layer. The substrate is provided with a capacitor chip, and the battery is used as a printed wiring board (for example, Patent Document 6), and a multilayer printed circuit board in which a ground layer is laminated on the upper and lower sides of the power supply layer via an insulating material layer (for example, Patent Document 7), etc. Further, a related art of a package in which a 1C chip is built is a device in which a ground wiring and a power supply full-surface wiring pattern are disposed to face each other via a dielectric member (for example, Patent Document 10). Patent publication 2 Japanese Patent Laid-Open No. Hei 7-22757 (paragraph No. 0016, FIG. 1) 15 [Patent Document 3] Japanese Patent Laid-Open Publication No. Hei 5-211284 (paragraph No. 0010, 00H, 〇〇13, 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [0022] [Patent Document 6] Japanese Patent Laid-Open Publication No. 2004-172530 (paragraph No. 0045, Fig. 7) [Patent Document 7] Japanese Patent Laid-Open Publication No. 2001-53449 (paragraph No. 0035, Fig. 1) 6 1281732 [Patent Document 8] Japanese Patent Laid-Open Publication No. Hei No. 3-347496 (paragraph No. 0055) ° L Summary of Invention Invention of the Invention 5 Problem to be Solved by the Invention However, the circuit scale of the 1C chip is increased, When the operating speed is increased, the inductance of the wire from the external terminal of the chip to the wafer is increased, and the Φ chip is enlarged, and the synchronous switching is also increased. Further, the package tends to be small and multi-legged, and the wiring width is small, so that a large number of signals are processed, and on the other hand, the electric resistance component is also increased. Under this circumstance, the conventional countermeasures cannot be fully charged: Synchronous switching measures are effective. In addition, the external power supply terminal requires a large number of capacitors, and the method ensures the package space. Here, referring to Fig. 1 and Fig. 2, an equivalent circuit of an IC package sheet, an integrated circuit device, and an integrated circuit device including the printed wiring board will be described. In the integrated circuit device 2, the IC chip 4 is mounted on the multilayer wiring circuit (the substrate 6 (base)) and is covered by the cladding portion 8. The 1C package 10 is formed by the substrate level ° 卩 8 '. In the substrate 6, each of the conductor layers 6〇2, 6〇4 is used as a signal line, a power supply line or a ground (gnd) to form a circuit pattern or a conductor pad on the conductors 2〇6〇2, 604. Between the conductor layers 602, 604: an insulating layer 6 〇 6 for insulating the two. In the insulating layer formed in each of the through holes, the conductor through holes 6〇8 are formed, and by the respective conductor vias 6〇8, the connection between the power sources between the conductor layers 6〇2 and 604, the connection between the signal paths, and the connection between the grounds can be achieved. In the rush layer 6〇2, the 1C wafer 4 is placed on the top of the base 1271832 board 6 by recording the solder bumps, and the integrated circuit device 2 is disposed under the conductor layer 6〇4. A plurality of solder balls 612 electrically connected to a printed wiring board not shown. In the equivalent circuit 200 (second drawing) when the integrated circuit device 2 is mounted on the printed wiring board 5 (not shown), _ indicates a power supply line, GND indicates a ground line, and the inside of the IC chip 4 is displayed. The substrate 6 and the wiring layer 202 of the printed wiring board. The cell 2〇4 is disposed inside the 1C wafer 4. In the power supply line Vdd, the wiring portion 202 of the printed wiring board has the inductance component L1 and the resistance component R1, and the substrate 6 has the inductance component L2 and the resistance component R2. In the grounding line GND, the wiring portion 2〇2 of the I7 brush wiring board exists. The inductance component B3 and the resistance component & 3, the substrate 6 has an inductance component L4 and a resistance component & In the integrated circuit device 2, a capacitor Cm is externally applied between the power supply line vdd and the ground line GND. Thus, there are conductor vias 6〇8 between the IC chip 4 and the applied capacitor 1Cm, the inductance components L2 and L4 of the wiring portion of the substrate 6, and the resistance components R2 and R4, and the inductance component L1 of the wiring portion 202 of the printed wiring board exists. , L3 and resistance components Ri, R3. The electrical injury Ll L2, L3, L4 is generated by current and magnetic field, combined with the resistance of 1 R2, R3, R4, so that the characteristic impedance of the ic package 1〇 is increased. Therefore, the capacitor Cm is set to The characteristic resistance is caused by its capacitance component. The cow is low to absorb the potential fluctuation of the 20 pen source or ground caused by the synchronous switching of the cell 204 of the 1C wafer 4. Since the size of the integrated circuit device 2 is increased as the size of the integrated circuit device 2 is increased, it is necessary to increase the capacity of the capacitor Cm, and it is necessary to secure a sealing space of the capacitor cm different from the package 1 (the package body 1). In addition, the EMI shielding 1281932 is only based on the multilayer wiring board of Patent Document 1, and the speed and the large branch are increased, and the power consumption is increased. It is also necessary to improve the heat dissipation. 4 丨 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 The first object of the invention is to strengthen the 1C chip for the capacitor in the body of the ic seal mona::, by built-in resistance to change the endurance. ~ or grounding the second purpose of the invention is to 1C package Body, .. is built into the body of the package < political thermal circuit, to remove the thermal resistance of the package. The third object of the present invention is to construct a mosquito-covered structure in the heart of the 1C package. To shield electromagnetic noise. The method to be solved by the invention is The above-described object is the structure of the present invention. In order to achieve the above first object, the structure of the present invention is a C package, and the structure thereof is used for the carrier 1 (: crystal substrate and cladding) a coating portion of the ICW of the substrate, wherein the substrate and the cladding 1 or the first layer or the plurality of power supply layers and the grounding layer are provided, and the power supply layer and the ground layer are separated by a * θ (four) The dielectric layer is disposed opposite to each other, and a single or a plurality of capacitors are built in. With this structure, the power supply layer and the ground layer are disposed opposite to each other via the high dielectric layer to form a high-capacity capacitor. The power supply layer and the high dielectric layer are The sandwich structure of the ground layer constitutes a unit and constitutes a capacitor, and by increasing the number of units of the sandwich structure, a high capacity can be obtained. The IC package can be used to form a multi-capacitor with a degree of V inward, and the capacity can be easily achieved. Built-in 9 1281732 The ic package of this capacitor can reduce the influence of the wiring inductance or resistance of the substrate, and can improve the variation of the power supply or grounding of the synchronous switching of the 1C chip. The built-in capacitor can reduce the electrostatic capacity of the external capacitor, and can easily ensure the packaging space of the external capacitor. It can also be omitted from the external capacitor. The single or multiple capacitor can also be built in the substrate or the cladding. Or built in both the substrate and the cladding portion. If the capacitor is built in the cladding portion, the function of the conventional coating can be exhibited, and the function as a capacitor internal portion can be achieved. Both of them have built-in capacitors, which can increase the number of capacitors 10, and use the electrostatic capacity booster port to strengthen the power supply or grounding. To achieve the above first objective, the 1C package in the first application of the patent scope Further, a plurality of capacitors and an insulating layer may be laminated on one or both of the substrate and the cladding portion, and the capacitor may be separated by the insulating layer. 15 By means of the insulation layer, the built-in complex capacitors can be electrically separated. In order to achieve the above-described second object, the 1C package of the second aspect of the present invention has a structure in which a cladding portion of a 1C wafer mounted on a substrate is coated, and the cladding portion has an inner conductor layer that contacts the 1C wafer and is provided in the foregoing The outermost outer conductor layer of the cladding portion is connected between the inner conductor layer and the outer 20 side conductor layer by a heat conductor. According to this configuration, the heat conducting structure composed of the heat conductor and the outer conductor layer is formed in the covering portion to reduce the thermal resistance of the 1C package. The heat of the 1C wafer is discharged to the outside through the inner conductor layer and the outer conductor layer, and the heat dissipation effect of the 1C wafer can be obtained. 10 1281732 In order to achieve the third object, the 1C package of the third aspect of the present invention includes a substrate on which a 1C wafer is mounted and a cladding portion that covers the 1C wafer mounted on the substrate, and is provided on the substrate and The conductor layer of the cladding portion and a plurality of shielding conductors connecting the conductor layers constitute a fifth shielding conductor portion surrounding the 1C wafer. According to this configuration, in the 1C package, the shielding layer function of the electromagnetic noise can be obtained by forming the conductor layer of the substrate, the conductor layer of the cladding portion, and the shielding conductor portion that surrounds the 1C wafer with the shielding conductors. EMI can be mitigated by the noise-blocking effect of the 1C chip. In order to achieve the above first object, a fourth aspect of the present invention provides a method of manufacturing a 1C package, comprising: a substrate forming step and a coating portion forming step, wherein the substrate forming step forms a substrate, and the substrate has a laminate. a single or a plurality of power supply layers and a ground layer, and the power supply layer and the ground layer are disposed opposite to each other via a high dielectric layer, and a single or a plurality of capacitors are built in; 15 and a cladding portion forming step is carried out by coating The 1C wafer of the aforementioned substrate. With this configuration, a single or a plurality of capacitors can be formed in the 1C package by laminating the power supply layer, the high dielectric layer, and the ground layer in the 1C package. In order to achieve the above first object, a fifth aspect of the present invention is an integrated circuit device comprising the above 1C package. As described above, if the 1C package is used for the built-in capacitor between the power supply layer 20 and the ground layer, the influence of the wiring inductance or the resistance can be lightly reduced, and the variation of the power supply or the grounding of the high switching of the 1C chip can be improved. Further, in the 1C package system, when the cladding portion of the 1C chip is covered so that the inner conductor layer contacting the IC chip is connected to the outer conductor layer by the heat conductor, the heat conduction structure can be constructed, the thermal resistance can be reduced, and the heat dissipation effect can be obtained. . 1281732 When the 1C package is used to form a shielded conductor portion surrounding the Ic chip, the shielding function of electromagnetic noise can be obtained, and EMI can be reduced. Advantageous Effects of Invention According to the present invention, since the capacitor is built in the package body, the noise is switched in the same five steps, and the potential variation resistance of the power source or the ground can be enhanced. According to the present invention, since (4) the coffee body is used Since the shielding conductor portion surrounds the 1C wafer, the electromagnetic shielding effect can be obtained by shielding the conductor portion. According to the present invention, the heat built in the 1C package can be guided by the heat conductor (the heat of the wafer is guided from the inner conductor layer to the outer side). Since the conductor layer can reduce the thermal resistance of the redundant package, the heat dissipation effect of the 1C wafer can be obtained. C Embodiment] I is the best mode for carrying out the invention [First embodiment] 芩 makeup 3rd and 4 is a view showing a third embodiment of the present invention. Fig. 15 is a cross-sectional view showing an example of a circuit device of a ❹ 丨 卿 IC IC package, and Fig. 4 is a diagram showing a symbolization of a capacitor. The package circuit device 2 includes a substrate 4 including a semiconductor element or the like, and a 2-layer substrate 6' as a multilayer wiring circuit substrate (base) of the lap wafer 4. Wrap 1 (: package of wafer 4 and substrate 6) The cover portion 8 is configured by a substrate 6 and a cladding portion 8 on which the 1C wafer 4 is mounted. Here, a bare wafer is used in the wafer 4, and a ball grid array (BGA) is formed in a surface package form. a wafer, a bump-free LGA wafer, or a QFP-form having a wire. Any of the white ray wafers 4 has a semiconductor crystal 121281732 formed of a semiconductor element or the like. Further, the substrate 6 is formed to encapsulate the 1C wafer. A conductor pattern or a conductor 4 of an electronic component such as four. The first signal layer 12 is provided on the uppermost layer of the substrate 6, and the second squall layer 14 is provided on the lowermost layer. The signal layer 12 is a metal layer and serves as a conductor layer. A conductor pattern of 5 is formed, and a plurality of solder bumps 16 of the 1C wafer 4 are disposed on the conductor pattern to be electrically connected. The solder bumps 16 are preferably gold tin and the like having high conductivity and good heat conduction. Further, the signal layer 14 is also used as the same. The conductor layer is a metal wiring layer, and a conductor pattern is formed, and a plurality of solder balls 18 for electrically connecting to an external circuit are disposed on a lower portion thereof. For convenience of explanation, a point where the conductor pad or the conductor pattern constitutes a predetermined circuit pattern is omitted. 15 20 In the substrate 6, the first, second, and third power supply layers 21, 22, and 23 are provided as a complex array of flat power supply layers between the signal layers 12 and 14, and the first, second, and third ground layers 31 are provided. 32 and 33 are used as a plurality of flat-plate grounding layers. The power supply layers 21, 22, and 23 and the grounding layers 31 and 32 and the metal-added wiring layer are configured to serve as a conductor layer, and the heat-conducting heat is high. a material of the genus Meng. The second high dielectric layer a is disposed between the power layer 22 and the ground layer 32 in the power layer η and the ground layer m, and the first high dielectric layer 4 is disposed between the source layer 23 and the ground layer 33. 3 high dielectric layer 43. Each high dielectric layer 41 42 43 is formed of a material having a germanium dielectric ratio ε. Therefore, in this embodiment, in the C-sealing body 10, the substrate layer 6 and the ground layer 31 are sandwiched between the high-band gates and the electric layer 41, and the capacitors are formed. C1.朴^ _ 丨 ^ ^, the wrong power layer 22 and the ground layer 32 across the dielectric layer 42 relative to the distribution of 2 • set 'body brother 2 capacitor cry C2, borrow Thunder μ 23 and ground layer 33 (four) high dielectric error source The layered electrical limb layer 43 is disposed opposite to the sandwich structure, and 13 1281732 constitutes the third capacitor C3. Therefore, a plurality of capacitors C1, C2, and C3 are embedded in the plurality of layers of the substrate 6, and each of the capacitors C1, C2, and C3 can use all areas or partial areas of the substrate 6, so that the capacitors C1 and 匸 can be fully protected. 2. The relative electrode area of C3. Since the capacitance c of the capacitor is proportional to the product of the dielectric constant ε 5 and the area ( (the equation (1) described later), each of the capacitors C1, C2, and c 3 has a high dielectric constant (ε) and an area A. In addition, the second insulating layer 52 is provided between the ground layer 31 and the power source layer 22, and the second insulating layer 52 is provided between the ground layer 31 and the power source layer 22, and the second insulating layer 52 is provided between the ground layer 31 and the power source layer 22. The third insulating layer 53 is provided between the ground layer 32 and the power source layer 33, and the fourth insulating layer 54 is provided between the ground layer 33 and the signal layer 14 of the lowermost layer. With this configuration, the respective capacitors Cl, C2, and C3 are separated by the insulating layers 51, 52, 53, 54 and are independent structures. Therefore, each of the capacitors C1, C2, and C3 can be used individually. The conductive vias 6 15 1 and 62 are formed in the via holes formed in the signal layer 12 and the insulating layer 51, and the via holes 63 are formed in the via holes formed in the south dielectric layer 41, the ground layer 31, and the insulating layer 52. The conductor vias 64 are formed in the via holes of the high dielectric layer 42, the ground layer 32, and the barrier layer 53, and the via holes are formed in the via holes formed in the high dielectric layer 43, the ground layer 33, and the insulating layer 54. . Namely, the conductors 61, 62, 63, 64, and 65 electrically connect the power supply layers 20 21 22 and 23 of the capacitors C1, C2, and C3 to the power supply terminals of the 1C wafer 4, and can be electrically grounded. The conductor vias 61, 62, 63, 64, 1 provided in the substrate 6 (the wafer 4 and the respective power supply layers 21, 22, 23 of the capacitors C1, C2, C3 are directly connected by the solder bumps 16, The distance between the connection structure and the connection is short, and the inductance component for connection can be reduced. 14 1281732 Forming a conductor via hole formed in the signal layer 12, the insulating layer 51, the power supply tray 91, and the through hole of the dielectric layer 4i 71, 72, forming a conductor guide in the through hole formed in the insulating layer & the power supply layer 22 and the high dielectric layer 42: ... ▼, 73, 74, in the form 5 10 in the insulating layer 53, the power layer 23 and high The via holes of the dielectric layer 43 are formed into the via holes 75 and 76, and the vias are formed in the via holes formed in the insulating layer 54.

8 〇 ^ 72 ^ 73 > 74 ^ 75 > 76 ^ 77 . 78^ J

The grounding terminals 31, 32, 33 of Cl, C2, and C3 and the ground terminal of the 1C wafer 4 are electrically turned on, and the same potential can be achieved. By the conductors disposed in the substrate 6: 7b, 72, 73, 74, 75, 76, 77, 78, 1 (: the wafer 4 and the respective grounding layers 31, 32 of each of the electric devices [1, C2, C3, 33 is directly connected by the solder bumps 16, and the connection between the connection structures is short, and the inductance component for connection is also reduced on the ground side. The via holes are formed in the via holes of the substrate 6 formed between the layers 12 and 14 of the 彳§ The via holes 81 82. That is, the conductor via holes 81 and 82 electrically conduct the signal layers 12 and 51. 15 Further, the cladding portion 8 is completely covered with the insulating layers of the substrate layers 6 and 1 (:: the surface layer of the wafer 4) The resin is formed. σ The capacitances of the substrate 6 formed in the integrated circuit device 2 thus constructed are formed as shown in Fig. 4. In the integrated circuit device 2 (Fig. 4), 181, 182 are signal terminals, 183 is a power supply terminal, and f20 is a ground terminal. ^ Capacitors C1, C2 formed by a plurality of stacked power supply layers 21 and ground layer 31, a power supply layer and a ground layer power supply layer 23 and a ground layer 33. C3 exists in parallel. For each capacitor C C2, C3, if the power layer 21 and the ground plane power layer 22 and the ground plane%, the power layer Μ and the ground (4) are opposite The product has a thickness of 15 1281732 A, the thickness of the high dielectric layers 41, 42 and 43 (distance between electrodes) is d, each electrostatic capacitance is C, and the dielectric constant of each of the high dielectric layers 41, 42 and 43 is ε, C =s · A/d ...(1) The combined capacitance of the capacitors C1, C2 and C3 in parallel is C13 is 5 C13=3xs · A/d=3C ...(2) Due to the use of materials with high dielectric constant Therefore, the capacitors C1, C2, and C3 have a high electrostatic capacitance. As in the embodiment, the capacitors C1, C2, and C3 are connected in parallel. Therefore, the combined electrostatic amount C13 can obtain a high electrostatic capacitance corresponding to the number of laminations. The features of the integrated circuit device 2 or the 1C package 10 of this embodiment are as follows. (1) In the integrated circuit device 2 or the 1C package 10, there is a built-in between the power supply terminal 1 83 and the ground terminal 184. Since the electrostatic capacitor C13 composed of the capacitances C1, C2, and C3 in the 1C package 10 is synthesized, the electrostatic capacitor can be synthesized, and the characteristic impedance can be reduced, and the fluctuation resistance of the power source and the ground can be enhanced. Even if the 1C chip 4 generates synchronous switching, the potential of the power supply and the grounding does not change, but the letter that contributes to the operation (2) The capacitance of the capacitors C1 to C3 is set according to the sizes of the high dielectric layers 41 to 43 and the substrate 6, and the number of static capacitances 20 can be realized by stacking the number N. (3) Since 1C The wafer 4 is directly connected to the power supply layers 21 to 23 and the ground layers 31 to 33 by the solder bumps 16 through the conductor vias 61 to 65, 71 to 78, so that the distance between the connections can be shortened and the inductance component can be reduced.

(4) Therefore, by embedding the capacitors C1 to C 16 1281732 in the substrate 6 of the 1C package 10, the influence of the wiring inductance or the resistance of the substrate 6 can be reduced, and the variation of the power supply and the grounding of the π-wafer can be enhanced. . It is possible to reduce the capacitance of the integrated circuit device 2 and reduce the package space. Next, the equivalent circuit of the integrated circuit device 2 will be described with reference to Fig. 5. Fig. 5 is an equivalent circuit diagram showing the case where the integrated circuit device is mounted on a printed wiring board. 'This equivalent circuit 3 is as described above (Fig. 2), Vdd is the power supply line, gnd is not grounded, and shows the inside of the wafer 4, the substrate 6, and the wiring portion 302 of the printed wiring board. 1C chip The internal unit of 4 is set to unit cell 3〇4. In the power supply line, the wiring portion 302 of the printed wiring board has an inductance component L10 and a resistance component & 1 〇, and the substrate 6 has an inductance component L2 〇, el and a resistance component R2 〇, rl, and is printed on the ground g ND. The wiring portion 302 of the wiring board has an inductance component L3 〇, and the resistor is wound R30. The substrate 6 has inductance components L4 〇 and e2 and resistance components R4 〇 and r2. In the integrated circuit device 2 of the embodiment, in the integrated circuit device 2 of the embodiment, the electric field Cn is embedded in the capacitor Cm between the power supply line Vdd and the ground line GND. Therefore, in the equivalent circuit 30Q, the capacitor is centered, and the inductance components el and e2 and the resistance components rl and 〇 are present on the substrate 6, and the inductance components L20 and L40 and the resistance components R20 and R40 are present under the substrate 6. At this time, since the distance between the connection of the 1C wafer 4 to the capacitors C1 to C3 is shortened, 20 can greatly reduce the inductance component and the resistance component, that is, el «L2 〇, e2 <<dL4〇, rl«R20, r2«R40 . In this way, a large-capacity capacitor -cn is embedded in the substrate 6, and when the capacitor Cn is in the first embodiment, Cn:= C13 is the same as the combined capacitance C13, so that the capacitor cn inside the substrate 6 can absorb the 1C wafer 4 The potential of the power supply or the ground of the unit cell 3〇4 17 1281732 is switched synchronously, and stable operation can be expected. Namely, the capacitor Cn is disposed in the vicinity of the cell 3〇4 of the 1C wafer 4, and the action of the cell 304 can be protected from the influence of the power supply and grounding caused by the influence of the synchronous switching. 5 [Second embodiment] Lu 1〇 15 2〇

A second embodiment of the present invention will be described with reference to Figs. 6 and 7. Fig. 6 is a perspective view showing an example of an integrated circuit device using the package of the second embodiment, and Fig. 7 is a view showing a structure of an IC package and an integrated circuit device in which a capacitor is symbolized. In the sixth and seventh drawings, the same portions as those of the integrated circuit device shown in Figs. 3 and 4 are denoted by the same reference numerals. In the integrated circuit device 2 of the embodiment, the fourth and fifth high dielectric germanium layers 44 and 45 are substituted for the second and third '' of the integrated circuit device 2 (Fig. 3) of the first embodiment. And the marginal layers 52, 53 constitute. Each of the high dielectric layers μ is formed of a material having a high dielectric constant ε as described above. According to this configuration, the ground layer 31 and the power source layer 22 are placed between the high dielectric layer 44 and the second dielectric structure to form the fourth capacitor C4. Further, the ground layer 32 and the power source layer 23 are separated by a high dielectric layer. 45 relative setting, by the same structure, constitutes the 5th Emperor Liu cry ^ package ° 〇 ^ 5. The other structure constitutes the capacitors C1 to C3 in accordance with the second embodiment. 2 (Fig. 6 C5m-shaped gamma-structured red-body circuit device structure. The electro-optical suspects 1, C2, C3 form the knot six cries ^ C2, C3, C4, C5 shown in Fig. 7 in the substrate 6 In parallel, the combined electrostatic capacitance C15 of the electric junction CC5 is C15=5C and 18 1281732. In the formula (3), 'C is as shown in the formula (1). That is, the integrated electric device 2 or 1 of the second embodiment. (:: In the package 1A (Fig. 6 and Fig. 7), since the insulating layer and % in the first embodiment are changed to the high dielectric layers 44 and 45, the thickness of the substrate 6 can be changed without changing the thickness of the substrate 6. The electric capacitors C4 and C5 are added. When the combined capacitance C15 when the capacitors C1 to C5 are connected in parallel, the capacitor Ci^Cn=cl5=5 C of the equivalent circuit 300 (Fig. 5) is compared with the above. In the integrated circuit device 2 (Fig. 3), the characteristic impedance can be further reduced, and the variation resistance of the surface 1C wafer 4 to the potential of the power source and the ground 10 can be switched. [Third embodiment] Referring to Fig. 8 And Fig. 9, a third embodiment of the present invention will be described. Fig. 8 is a cross-sectional view showing an example of an integrated circuit device in which the ic package of the third embodiment is not used, and Fig. 9 is a diagram showing In the eighth and ninth drawings, the same portions as those of the integrated circuit device shown in Fig. 6 are denoted by the same reference numerals. In the integrated circuit device 2 of the embodiment, the cladding portion 8 formed on the surface portion of the substrate 6 covers the ICb die 4, and the fourth and fifth power supply layers 24, 25, and the second are alternately disposed thereon. 4 and the fifth ground layers 34 and 35 form a sixth high dielectric layer 46 between the power source layer 24 and the ground layer 34, and form a eighth high dielectric layer 48 between the power source layer 25 and the ground layer %. The layers 24 and 25 and the ground layers 34 and 3曰5 are similarly composed of a metal wiring layer as a conductor layer. Each of the high dielectric layer buckets 6, 47, and 48 has a high dielectric material biting material layer as described above. The cover portion is composed of a stack of the upper speed package/original layer 24, 25, the ground layers 34 and 35 and the high dielectric layer 46, and 4 19 1281732 8 and a coating resin layer 50 composed of an insulating layer. In this embodiment, the covering resin layer 50 covers the side surface portion and the lower surface portion of the coated ic wafer 4. The power source layers 24, 25, the ground layers 34, 35, and the high portion constituting the cladding portion 8 are high. 5 In the laminated portion of the electric layer 46, 47, 48, the sixth capacitor C6' is separated from the ground layer 34 and the power layer 25 by the sandwich structure in which the power layer 24 and the ground layer 34 are disposed opposite to each other via the high dielectric layer 46. The sandwich structure in which the high dielectric layer 47 is opposed to each other constitutes the seventh capacitor C7, and the eighth capacitor 10 C8 is formed by the sandwich structure in which the power supply layer 25 and the ground layer 35 are opposed to each other via the high dielectric layer 47. The via holes of the dielectric layer 46, the ground layer 34, and the high dielectric layer 47 form conductor vias 83, and the via holes 84 are formed in the via holes formed in the high dielectric layer 47, the power supply layer 25, and the high dielectric layer 48. The conductor vias 83 electrically connect the power supply layers 24 and 25 to the same potential, and the conductor vias 84 electrically conduct the ground layers 34 and 35 to achieve the same potential. Further, the plurality of via holes formed in the high dielectric layer 48, the ground layer 35, the cladding resin layer 5, the signal layer 12, and the insulating layer 51 form conductor via holes 85, 86 as a plurality of conductor via holes, which are formed in the package. The plurality of via holes of the resin coating layer 50, the signal layer 12, the insulating layer 51, the power source layer 21, and the high dielectric layer 41 form conductor via holes 80 and 88 as a plurality of conductor via holes. The conductor via holes 85 and 86 electrically connect the power source layers 25 and 21, and the potential is increased. The conductor via holes 87 and 88 electrically conduct the ground layers 35 and 31, and the potential can be increased. Capacitors C1, C7, C8 formed in the cladding 20 /2 are embedded in the capacitors C1, C2, C3, C4, and C5 embedded in the substrate 6 formed in the integrated circuit device 2 (Fig. 8) thus constructed. The structure shown in Fig. 9 is formed, and all are presented. In Fig. 9, the same portions as those in Fig. 7 are denoted by the same reference numerals. The capacitors C6, C7, W and 5 formed by stacking the plurality of power supply layers 24, the ground layer 34, the ground layer 34, and the power source 25 and the ground layer 35 are present. Since the capacitors C6, C7, and C8 are as described above, since the equation (1) is established, the combined capacitance C68 of each of the states C6, C7, and C8 is ', C68 = 3xe. A/d = 3C (4)

10 15

Therefore, when the capacitances of the capacitors C1 to C5 of the substrate 6 and the capacitors c6 to C8 of the cladding portion are C, the combined electrostatic capacitance Cl8 is C18=C15+C68=5C+3C=8C · (5) A combined electrostatic capacitance c 18 exists between the terminal 183 and the ground terminal m, and the combined electrostatic capacitance C18 is composed of respective capacitances of the capacitors C1 to C8 which are increased in capacity by using a high dielectric material, and the capacitors are connected in parallel. The value is Cn=C18=8C and the capacity is increased. According to this configuration, the characteristic impedance of the power supply and the ground is reduced, and the impedance is further enhanced. The synchronous switching of the c-chip 4 changes the resistance to the potential of the power supply and the ground. [Fourth Embodiment] Tea, Fig. 10, and the like, a fourth embodiment of the present invention will be described. First, a cross-sectional view showing an example of a method of manufacturing the IC package and the integrated device of the fourth embodiment in the order of the steps is shown. In Fig. 10, the same portions as those of the WA device 2 shown in Fig. 8 are denoted by the same reference numerals. The clothing comprises (A) a step of forming the substrate 6, (B) a step of forming the IC wafer 4, and (C) a step of forming the cladding portion 4. (A) Forming Step 21 of the Substrate 6 In the step of cutting the substrate 6, as shown in FIG. 1G(A), the signal layers 12, 14, the power supply layers q 4, 22, 23, the ground layers 31, 32 33 uses a conductive material such as aluminum, copper or silver, and the high dielectric layers 41, 42, 43 use a high dielectric material, η is wrong, the power supply layers 21, 22, 23 and the ground layer 31, 32, 3 5 3 are formed by alternately laminating high dielectric germanium layers 41, 42, 43, and a signal layer 12, υ", 4' is formed on the outermost layer portion thereof to form a substrate 6. This is formed by printing and evaporation. Either one can.

In this forming step, as shown in the figure (A), the conductor vias 61, 62 63, 64, 65, 71, 72, 73, 74, 75, 76, 77, 78, 81, 85 86 The position of 88 is formed to form a through hole corresponding to each of the through holes, and the conductor guiding holes 61, 62, 63, 64, 65, 71, 72, 73, ^, y, 81, 82, 85, 86, 87, 88 It is possible to use the above-mentioned conductive material to form a printing method or a steaming mirror. Each of the through holes 1 is formed by drilling a hole. Each conductor guide hole $1, 62, 15 63, 64, 65, 71, 72, 73, 74, 75, 76, 77, 78, 81, 82, 85, 86, 87, 88 is used to carry out the money through the through hole And formed. The signal layer 12 of the substrate 6 is formed with a conductor 对应 corresponding to the mounting surface of the 1C wafer 4 or a guide shape corresponding to a predetermined circuit. Similarly, a conductor pad or conductor pattern is formed at the position where the signal layer Η corresponds to the solder ball 18. 20 (B) The mounting step of the 1C wafer 4; the corpse juice 叩 叩 叩 凸 凸 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 搭载 信号 信号 信号Holes such as holes 7 and 72 can be electrically connected by using a material having a good electrical property of gold and tin. 22 1281732 (c) Step of forming the covering portion 8 + As shown in Fig. 1(C), the surface of the substrate 6 on which the 1C wafer 4 is mounted is covered with the surface of the substrate 6 around the 1C wafer 4 The resin layer is %, and 5 forms a part of the cladding portion 8, and a through hole is formed at a position for providing the conductor via holes 85, 86, 87, 88, and the conductor via holes 85 are provided. which is,

In this step, the side surface portion of the 1C wafer 4 is covered with a coating resin layer 5, and is sealed, and the surface portion of the coating resin layer 50 coincides with the upper surface of the Ic wafer 4. As the coating resin layer 50, a resin having high sealing properties such as polyimine is used. < In the step of forming the coating portion 8, as shown in Fig. 8, the surface layer of the π crystal piece 4 and the surface of the coating resin (4) are covered to form a coating portion. That is, in the cladding portion 8, the power supply layers 24, 25, the ground layer, the high dielectric layers 46, 47, 48 and the cladding resin layer 5 () - the same as the power layer 2 core 25 and the ground layer 34 And 35 are respectively arranged in a three (four) structure by one of the high dielectric layers 郜, 叼, 牝苴, and the power supply layer 24 is disposed on the outermost layer of the cladding portion 8 to contact the IC "4 (10) The ground layer % is disposed to be disposed in the stack. Further, in the step of forming the cladding portion, the hole is formed at the position of the conductor guide holes 83, 84, 85, 86, 87, 88, and (4) is a conductor guide hole. 83, 84, 85, 86, 87, 88. These power supply layers 24, 25, ground plane %, % and conductor guide holes 83 ' 84 ' 85, 86, 87, 88 have good electrical conductivity such as Ming, copper and silver. The conductor material is formed by printing or vapor deposition. The high dielectric layers 46, 47, and 48 are made of a high dielectric material, and the formation method is printing or the like. After the steps are as shown in FIG. It is possible to manufacture a 1-inch package 1 and an integrated circuit device 2. Further, a conductor can be used for the conductor vias 23 1281732 85, 86, 87, 88 provided between the substrate 6 and the cladding portion 8. [5th [Embodiment] The fifth embodiment of the present invention will be described with reference to the drawings and Fig. 12. Fig. 11 shows a fifth embodiment (the sectional view of an example of the integrated circuit device 5 of the package) Fig. 12 is a view showing the structure of a capacitor-formed 1C package and an integrated circuit device. In the first and fourth figures, the same parts as the integrated circuit device shown in Figs. 8 and 9 are attached. In the integrated circuit device 2 (Fig. 11) of the Ic package 1 of the embodiment, the covering portion 8 is laminated on the outermost portion of the 1C package 10 to ground 10 layers 36 and two The ground layer 36 is formed as described above as a conductor layer. The ninth capacitor C9 is formed by the sandwich structure in which the ground layer 36 and the power source layer 24 are opposed to each other via the high dielectric layer 49. That is, this embodiment The cladding portion 8 is embedded in the four sets of capacitors C6, C7, C8, and C9. In this embodiment, the conductor vias 89 are formed in the plurality of via holes formed in the high dielectric layer 46, the ground layer 34, and the high 15 dielectric layer 47. , 90, 91, 92, 93, the power supply layers 24, 25 are connected by a plurality of conductive vias 89, 9, 〇, 91, 92, 93 Electrical connection. By forming the conductor vias 89, 90, 91, 92, 93, four sets of capacitors C6, C7, C8, C9 are connected in parallel, and the capacitors C6, C7, c8, C9 are also built in. Since the capacitors C1 to C5 of the substrate are connected in parallel, the capacitance 20 of the composite 20 at this time is the capacitor Cn=cl9=9c, and the capacity can be increased. Further, the power supply layer 25 and the conductor via holes 85 and 86 can be used. The power supply layer 21 of the substrate 6 is electrically connected. In this embodiment, the conductor via 94 is formed in the via formed in the substrate 6, whereby the conductor via 94 can form the signal layer 12 in the thickness direction of the substrate 6. , 14 signal paths. 24 1281732 then forming a heat conducting hole 101, 1〇2, 1〇3, 104, 105, 1〇6 as a heat conductor in a plurality of through holes formed in the high dielectric layer 49, the power layer 24 and the high dielectric layer 46, The plurality of through holes formed in the high dielectric layer 46, the power source layer 25, and the high dielectric layer 48 form heat conductive holes 111, 112, 113, 114, 115, and 5 116. Since each of the heat transfer holes 101 to i6, 111 to 116 constitutes a heat conductor, it may be formed of a material having high thermal conductivity. That is, the covering portion 8 constitutes the ground layer 36, the heat conducting holes 101, 102, 103, 104, 105, 106, the ground layer 34, the heat conducting holes 111, 112, 113, 114, 115, 116 and the ground layer 35 constitute a heat conducting circuit 12〇 (Fig. 1 2). Thereby, the heat transfer circuit 120 can improve the heat of the heat of the 1C wafer 4 from the cladding portion 8 to the outside, and can cool the 1C wafer 4. The arrow η shows the movement of the heat of the thermal circuit 120. In this embodiment, the conductor via holes 83, 84 and the via hole patterns of the third embodiment are not shown, and the conductor via holes 83, 84 and the via holes may be provided, and the conductor via holes 83 may also be conductor conductive. Holes 89, 90, 91, 92, 93 are used in combination, and 15 conductor hole 84 can also be thermally conductive holes 1〇1, 102, 103, 1〇4, 1〇5, 106, 111, 112, 113, 114, 115. And 116 are used together. Moreover, since the power source layer 25 and the power source layer 21 are connected by the conductor vias 85, 86, etc., and the heat conduction circuit 120 is formed on the substrate 6, the heat of the IC chip 4 can also dissipate heat to the substrate 6, which contributes to the ic wafer 4. cool down. 20, in this embodiment, as shown in Fig. 12, similarly to the third embodiment (Fig. 8), the capacitors C1 to C5 are built in the substrate 6, and the capacitors C6 to C9 are built in the cladding portion 8, Since the capacitors C1 to C9 are connected in parallel, the characteristic impedance of the power source and the ground can be reduced, and the variation resistance of the potential of the power source and the ground can be increased by 1 (:: synchronous switching of the wafer 4). Further, in this embodiment, heat conduction is formed. Electric 25 1281732 Road 120 heat conduction hole 1〇1„, just, H)5, H)6, m, 112 (1), ii4, 115, m have the capacitance (10)~C9, the impurity (four) energy, and the surface __ reduction [different 6 form] - 5 10 Referring to Fig. 13, Fig. 14 and Fig. 15, the Fig. 13 shows the cross section of the κ: 咖衣置-example using the sixth embodiment Fig. 14 is a view showing a shield conductor, and the first schematic structure of the substrate is shown. The same figure is the same as the integrated circuit device 2 shown in Fig. 12 and Fig. 15 and FIG. In the ic-sealing body 10 and the integrated circuit device a of this embodiment, as described above (fifth embodiment: _), at the outermost portion of the covering portion 8 A ground layer 36 composed of a conductor layer is disposed, and a ground layer 33 also composed of a conductor layer is disposed under the substrate 6. That is, the 1C wafer 4 is held by the ground layer 36 disposed on the upper surface 15 of the memory wafer 4 and disposed on Between the ground layer % of the lower surface of the 1C wafer 4. Here, the shielding conductors 131, 132, ..., 13n are provided in a plurality of through holes formed in the cladding portion 8 and the substrate 6 spanning the ground layers 33, 36, The plurality of shielding conductors 131, 132, ..., 13n are connected between the ground layers % and 36, and surround the IC wafer 4. That is, as shown in Fig. 14, by the shielding conductors 13i, 2〇3n and the ground layer 33 36, a cage-shaped shield conductor portion 13 is formed, and a 1C wafer 4 is built in the shield conductor portion 130. The shield conductor portion 13 is electrically grounded and grounded with the ground layers %, 36. With this configuration, the conductor can be shielded. The portion 130 blocks electromagnetic waves radiated from the 1C wafer 4, and blocks the electromagnetic waves from the outside by the shield conductor portion 130, and the 26 1281732 prevents the 1C wafer 4 from being affected by external electromagnetic waves. Then, in this embodiment, Has the same structure as that of the fifth embodiment, and has a shadow The body 13A, as shown in Fig. 15, the capacitors C1 to C5 are built in the substrate 6, and the capacitors C6 to C9 are built in the cladding portion 8. The capacitors C1 to C5 9 are connected in parallel, and the shielding conductor portion 130 is formed around the capacitors C1 to C5. In addition, electromagnetic shielding can be sought, and the electromagnetic shielding effect of the south can be suppressed, and it can be suppressed or reduced]. In this embodiment, the shield conductor through holes 13 132···13η constitute a connection circuit for connecting the ground layers 33 34 35 and 36, which contributes to a reduction in the resistance between the connections. 10 15 20 [Seventh embodiment] Referring to Fig. 16, a taxi will be described in the seventh embodiment of the present invention. Fig. 16 is a cross-sectional view showing an example of a method of manufacturing a 1C package and an integrated circuit device in a step-by-step sequence. In Fig. 16, the same portions as those shown in Fig. 13 are shown with the same reference numerals. The step of carrying the step comprises: (A) forming step of the substrate 6, (B) forming the V (C) covering portion 4 of the IC wafer 4 (8) forming the substrate 6 (4) is 2, 14 , forming a step in the strip Figure 16 (A) shows the 'signal layer 1 bucket source layer 21, 22, 23 silver, etc., the ground layer 31, 32, 33 uses aluminum, copper, [shengjia's conductor dielectric material, _ w dielectric The body layers 41, 42, 43 use high 'It's, Lei Yuanen 3 is separated by high dielectric ~ will be 21, 22, 23 and ground layer 3 32, 3 ^ moon layer 41, 42, 41 set signal The layers 12 and 43 are formed by laminating each other, and the outermost portion of the layer 12 can be formed to form the substrate 6. The formation method is printing, steaming 27 1281732 in this step, as shown in Fig. 16(a), in the conductor via 61,

The conductor vias 131, 132, ..., 13n are formed using the above-described conductor material. This method of formation can be either printing or steaming. A conductor layer corresponding to the mounting surface of the 1C wafer 4 or a conductor pattern corresponding to a predetermined circuit is formed on the signal layer 12 of the substrate 6. Similarly, a conductor pad or conductor pattern is formed at the position where the signal layer 14 corresponds to the 10 tin balls 18. (B) Step of mounting the 1C wafer 4 As shown in Fig. 16(B), the IC wafer 4 is mounted on the signal layer 12 of the substrate 6 via the solder bumps, and electrical connection with the signal layer 12 can be achieved. (C) Step 15 of forming the covering portion 8 As shown in Fig. 16(C), a coating resin layer is provided on the surface of the substrate 6 around the 1C wafer 4 on the substrate 6 on which the 1C wafer 4 is mounted. 5〇, a portion of the cladding portion 8 is formed, and a via hole is formed at a position for providing the conductor via holes 85, 86. The conductor via holes 85, 86 are provided. That is, by this step, the ic wafer 4 is The side surface portion is covered with the coating resin layer 50 and sealed, and the surface portion of the coating resin 20 layer 50 is aligned with the upper surface of the 1C wafer 4. The resin resin layer is made of a resin having a high sealing property such as a polyimide resin. In the step of forming the covering portion 8, as shown in Fig. 13, the surface layer of the buckle wafer 4 and the surface of the covering resin layer 50 are covered to form the remaining portion of the covering portion 8. Port 8 'power layer 24, 25, ground layer 34, 35, 28 1281732 36 and germanium dielectric layers 46, 47, 48 and cladding resin layer 5 〇 _ same with power layer 2 4, 25 and A sandwich structure is formed between the formations 34 and 35 via one of the high dielectric layers 47, 47, and 仙, and the power supply layer 24 ′ is disposed on the outermost layer of the cladding portion 8 to be disposed on the innermost layer of the contact 1C wafer 4 . 35, the stacking is set to 5. In the step of forming the cladding portion, the through holes are formed at the positions where the conductor vias 85, 86, 89 9 93, and the shield conductor vias 13 i, 132 ... 13 n are formed. The conductive vias 85, 86, 89-93, the shield conductor vias 131, 132, ..., 13n are formed. The power supply layers 24, 25, the ground planes 34, 35, and the conductor vias 85, 86, 89-93 The shielding conductor holes 131, 132, . . . , 13n use conductive materials such as aluminum, copper, silver, etc., which are electrically conductive. The forming method is either printing or vapor deposition. The high dielectric layers 46, 47, 48. A high dielectric material is used, and the formation method is printing or the like. By the same steps, as shown in FIG. 13, the 1C package 10 and the integrated circuit device 2 can be obtained, and in the 1C package 10 The shield conductor portion 15 130 is formed inside. Further, the conductor via holes 85, 86 or the shield conductors disposed between the substrate 6 and the cladding portion 8 A wire can be used for the 131, 132, and 13 η. The shielding conductor vias π 1 , 132 , ... 13n can also cover the side surface portion of the 1C package 10 to form a single shielding conductor layer. [Other Embodiments] 20 (1) In each of the above embodiments, the capacitors C1 to C3 or the capacitors C1 to C5 are built in the substrate 6, and the capacitors C6 to C8 may be built only in the cladding portion 8. (2) In the above embodiments, the capacitor C1 is provided. ~C3 (Fig. 3, Fig. 4), C1 to C8 (Fig. 8, Fig. 9), C1 to C9 (Fig. 11, Fig. 12, Fig. 3, Fig. 15) In addition, it is also possible to include a series of capacitors 29 1281732 instead of parallel, so that the capacitors C1 to C9 may be connected in parallel in parallel. (3) In the first or second embodiment, the plurality of capacitors C6 to C8 may be built in the same manner as in the third embodiment (the eighth embodiment), and the built-in capacitors may be built in the same manner as the substrate 6. The structure of the plurality of capacitors in which the insulating layer is separated may also be used. (4) In the sixth embodiment, the covering portion 8 may have a structure without a built-in capacitor. At this time, a ground layer is provided as a first conductor layer at a contact position on the upper surface of the 1C wafer 4, and a ground layer is provided as a second conductor layer at an outermost portion of the cladding portion 8, and the ground layer is connected by a heat conduction hole to constitute a heat conduction. The circuit can also reduce the heat dissipation resistance of the 1C package 10. [10] Next, the 1C package, the method of manufacturing the same, and the integrated circuit device of the present invention described above are based on the description of the scope of the patent application, and the technical ideas selected from the respective embodiments are listed. The technical idea of the present invention can be grasped by various standards or variations from the upper concept to the lower concept, and the appended claims are not limited to the inventors. 15 (Attachment 1) A 1C package having a substrate on which a 1C wafer is mounted and a cladding portion covering the 1C wafer mounted on the substrate, and one or both of the substrate and the cladding portion The single or multiple power supply layers and the grounding layer are stacked such that the power supply layer and the ground layer are disposed opposite each other via a high dielectric layer, and a single or multiple capacitors are built in. (Supplementary Note 2) The package of 1C according to the first aspect, wherein a plurality of capacitors and an insulating layer are laminated on one or both of the substrate and the cladding portion, and the capacitor is separated by the insulating layer. 30 1281732 (Supplementary Note 3) The 1C package according to the first aspect, wherein a plurality of capacitors are built in one or both of the substrate and the cladding portion, and the through holes are provided between the ground layers connecting the capacitors or between the power supply layers The conductor, by the aforementioned conductor, 5 connects the aforementioned capacitors in parallel. (Supplementary Note 4) A 1C package having a cladding portion covering a 1C wafer mounted on a substrate, the cladding portion having an inner conductor layer contacting the 1C wafer and a conductor layer disposed outside the outermost layer of the cladding portion The inner 10 side conductor layer and the outer conductor layer are connected by a heat conductor. (Supplementary Note 5) The package according to 1C of Attachment 4, wherein the conductor layer is a ground layer. (Supplementary Note 6) A 1C package having a substrate on which a 1C wafer is mounted and a cladding portion of the 1C wafer mounted on the substrate, and a conductor layer provided on the substrate and the cladding portion A plurality of shielding conductors connecting the conductor layers constitute a shielding conductor portion surrounding the 1C wafer. (Supplementary Note 7) An integrated circuit device having the above 1C package. 20 (Supplementary Note 8) A method for manufacturing a 1C package, comprising: a substrate forming step of forming a substrate having a single or a plurality of power supply layers and a ground layer laminated, and interposing the power supply layer and the ground layer The high dielectric layer is disposed opposite to each other, and the single or multiple capacitors are built in; and the 31 1281732 cladding portion forming step covers the ic wafer mounted on the substrate. (Attachment 9) A method of manufacturing a 1C package includes the steps of: (1) forming a substrate on which a 1C wafer is mounted; and (5) forming a cladding portion having a stacked single or multiple power supply The layer and the ground layer are disposed such that the power supply layer and the ground layer are disposed opposite to each other via a high dielectric layer, and a single or a plurality of capacitors are built in, and the 1C wafer is covered by the cladding portion. (Supplementary Note 10) 10, wherein the coating portion has a single or a plurality of power supply layers and a ground layer laminated, and the power supply layer and the ground layer are disposed opposite each other via a high dielectric layer A single or plural capacitor is built in and the capacitor is connected in parallel with the aforementioned capacitor of the aforementioned substrate. (Attachment 11) 15 The method for manufacturing a package of the 1C package according to the eighth aspect, wherein the step of forming the substrate on which the plurality of capacitors are built has the following steps: (1) forming a pass across the power supply layer or the ground layer on the substrate And (2) providing a conductor in the through hole to bridge between the power supply layers or the grounding ground 20 by the conductor. (Supplementary Note 12) The method of manufacturing the package of the first embodiment, wherein the step of forming the substrate having the built-in complex capacitor has the following steps: (1) forming a 1271832 pass across the power supply layer or the ground layer on the substrate. And (2) providing a conductor in the through hole to bridge the conductor between the power supply layers or the ground. (Supplementary Note 13) 5 The method of manufacturing the package of the 1C package of claim 10, wherein the step of forming the substrate on which the plurality of capacitors are built has the following steps: (1) forming a pass across the power supply layer or the ground layer on the substrate And (2) providing a conductor in the through hole, such that the power supply layer or the grounding 10 is bridged by the conductor. (Supplementary Note 14) A method of manufacturing a 1C package, comprising: (1) forming a substrate; (2) forming a cladding portion covering a 1C wafer mounted on the substrate; and (3) forming the cladding portion a step of forming a conductor layer contacting the 1C wafer; (4) forming a conductor layer on an outermost layer of the cladding portion; and (5) forming a heat conductor connecting the conductor layer. (Supplementary Note 15) 20 - A method for manufacturing a 1C package, comprising: (1) forming a substrate; (2) forming a cladding portion covering a 1C wafer mounted on the substrate; (3) forming the substrate and forming The step of covering the cladding portion includes the steps of forming a conductor layer for sandwiching the 1C wafer and forming a plurality of conductors connected between the conductor layers 33 1281732 to surround the ic wafer. The preferred embodiments of the present invention have been described above, and the present invention is not limited to the above description. As long as it is described in the scope of the claims or disclosed in the specification, the practitioner can of course carry out various 5 variants or It is needless to say that such variations or modifications are included in the scope of the invention. The present invention is directed to a 1C package that utilizes a capacitor built into the package to improve the resistance of the synchronous switching of the 1C chip to the potential of the power supply or ground. Moreover, the present invention relates to a 1C package, which has a thermal resistance of the package removed by a 10 heat dissipation circuit built into the package. Further, the present invention relates to a 1C package in which a shielding structure is constructed in a package to shield electromagnetic noise. Thus, the present invention can provide an efficient integrated circuit technology. I: BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a conventional 1C package and an integrated circuit device. 15 Figure 2 shows the equivalent circuit of the integrated circuit device. Fig. 3 is a view showing a 1C package and an integrated circuit device according to the first embodiment. Fig. 4 is a view showing a 1C package and an integrated circuit device in which a capacitor is symbolized. 20 Figure 5 shows the equivalent circuit of the integrated circuit device. Fig. 6 is a view showing a 1C package and an integrated circuit device of the second embodiment. Fig. 7 is a view showing a 1C package and an integrated circuit device in which a capacitor is symbolized. 34 1281732 Fig. 8 shows an IC package and an integrated circuit device according to a third embodiment. Fig. 9 is a view showing a 1C package and an integrated circuit device in which a capacitor is symbolized. 5 (A) to (C) are diagrams showing a method of manufacturing a 1C package and an integrated circuit device according to the fourth embodiment. Fig. 11 is a view showing a 1C package and an integrated circuit device of the fifth embodiment. Fig. 12 is a view showing a 1C package and an integrated circuit 10 device in which a capacitor is symbolized. Fig. 13 is a view showing a 1C package and an integrated circuit device of the sixth embodiment. Fig. 14 shows the person who shields the conductor portion. Fig. 15 is a view showing a 1C package and an integrated circuit 15 device for symbolizing a capacitor. The 16th (A) to (C) drawings show the 1C package and the method of manufacturing the integrated circuit device of the seventh embodiment. [Main component symbol description] 14...Second signal layer 16... Solder bump 18.. Tin ball 21.. Power supply layer (conductor layer) 22.. Power supply layer (conductor layer) 23.. Power supply layer ( Conductor layer) 2.. Integral circuit device 4..1.1. Wafer 6...substrate 8... cladding portion 10.. 1C package 12...1st signal layer 35 1281732 24.. Layer (conductor layer) 25.. Power supply layer (conductor layer) 31.. Ground plane (conductor layer) 32.. Ground plane (conductor layer) 33.. Ground plane (conductor layer) 34.. Stratum (conductor layer) 35.. Grounding layer (conductor layer) 36.. Grounding layer (conductor layer) 41.. High dielectric layer 42.. High dielectric layer 43.. High dielectric layer 44 .. . high dielectric layer 45.. high dielectric layer 46.. high dielectric layer 47.. high dielectric layer 48.. south dielectric layer 49.. high dielectric layer 50.. Covered tree·lipid layer 51.. Insulation layer 52.. Insulation layer 53.. Insulation layer 54.. Insulation layer 61.. Conductor via 62... Conductor via 63.. Conductor via 64... Conductor guide hole 65.. Conductor guide hole 71... Conductor guide hole 72... Conductor guide hole 73.. Conductor guide hole 74... Conductor guide hole 75... Conductor guide hole 76... Conductor guide 77... Conductor guide hole 78.. Conductor guide hole 81.. Conductor guide hole 82... Conductor guide hole 83... Conductor guide hole 84... Conductor guide hole 85... Conductor guide hole 86... Conductor guide hole 87.. Conductor guide Hole 88... Conductor guide hole 89.. Conductor guide hole 90... Conductor guide hole 91.. Conductor guide hole 92.. Conductor guide hole 93.. Conductor guide hole 36 1281732

94...conductor via 200...equivalent circuit 101...thermal via (thermal conductor) 202...wiring 102···thermal via (thermal conductor) 204...cell 103···thermal via (thermal 602...conductor layer 104···thermal via (thermal conductor) 604...conductor layer 105···thermal via (thermal conductor) 606...insulation layer 106···thermal via (thermal conductor) 608... Conductor via 111···thermal via (thermal conductor) 610... solder bump 112···thermal via (thermal conductor) 612... solder ball 113···thermal via (thermal conductor) C1... Capacitor 114···thermal via (heat conductor) C2...capacitor 115···thermal via (thermal conductor) C3...capacitor 116···thermal via (thermal conductor) C4...capacitor 120... Thermal conduction circuit C5...capacitor 130...shielding conductor portion C6...capacitors 131, 132...13n...shielding conductor guide hole 37

Claims (1)

1281732 X. Patent Application Range: 1. A 1C package having a substrate for mounting a 1C wafer and a cladding portion covering the 1C wafer mounted on the substrate, and the substrate and the cladding portion or both One of them has a single or multiple power supply layer 5 and a ground layer stacked, and the power supply layer and the ground layer are disposed opposite each other via a high dielectric layer, thereby singulating a single or multiple capacitors. 2. The 1C package of claim 1, wherein a plurality of capacitors and an insulating layer are laminated on one or both of the substrate and the cladding portion, and the capacitor is separated by the insulating layer. A 3C package having a cladding portion that covers a 1C wafer mounted on a substrate, the cladding portion having an inner conductor layer contacting the 1C wafer and an outer conductor disposed on an outermost layer of the cladding portion The layer is connected to the inner conductor layer and the outer conductor layer by a heat conductor. 4. A 1C package having a substrate on which a 1C wafer is mounted and a cladding portion of the 1C wafer on which the cladding 15 is mounted on the substrate, and a conductor layer provided on the substrate and the cladding portion and connected thereto The plurality of shield conductors of the equal conductor layer constitute a shield conductor portion surrounding the 1C chip. 5. A method of manufacturing a 1C package, comprising: a substrate forming step of forming a substrate, wherein the substrate has a stacked 20 single or multiple power supply layers and a ground layer, and the power supply layer and the ground layer are interposed The high dielectric layer is disposed opposite to each other, whereby a single or a plurality of capacitors are built in; and the cladding portion forming step is to form a cladding portion of the 1C wafer mounted on the substrate. 38 1281732 6. The integrated circuit device is the aforementioned 1C package having the first, second, third or fourth aspect of the patent application. 39