CN100417309C - 电路装置 - Google Patents

电路装置 Download PDF

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Publication number
CN100417309C
CN100417309C CNB200410011913XA CN200410011913A CN100417309C CN 100417309 C CN100417309 C CN 100417309C CN B200410011913X A CNB200410011913X A CN B200410011913XA CN 200410011913 A CN200410011913 A CN 200410011913A CN 100417309 C CN100417309 C CN 100417309C
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China
Prior art keywords
conductive pattern
circuit arrangement
protection
wiring layer
circuit
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Expired - Fee Related
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CNB200410011913XA
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English (en)
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CN1602137A (zh
Inventor
加藤敦史
中野敦史
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1602137A publication Critical patent/CN1602137A/zh
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Publication of CN100417309C publication Critical patent/CN100417309C/zh
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Abstract

一种电路装置，其具有抑制图案间的漏电流的结构。本实施方式的电路装置(10)具有电路元件(12)和规定的导电图案(12)，一体地树脂模制而成。还具有与电路元件(13)的高阻抗输入端子连接的第一导电图案(12A)和接近第一导电图案设置的第二导电图案(12B)。还具有在第一及第二导电图案之间延伸设置的保护导电图案(12C)，构成防止第一导电图案(12A)和第二导电图案(12B)之间的漏电流的结构。

Description

电路装置
技术领域
本发明涉及一种电路装置，特别是涉及一种具有抑制导电图案相互之间的漏电流的结构的电路装置。
背景技术
参照图6说明现有型的半导体装置100的结构。图6(A)是半导体装置100的平面图，图6(B)是其剖面图(参照专利文献1)。
参照图6(A)，在半导体装置100的中央部形成有由导电材料构成的接合区102，在接合区102周围接近配置多条引线101的一端。引线101的一端介由金属细线105和半导体元件104电连接，另一端自密封树脂103露出。密封树脂103具有密封半导体元件104、接合区102及引线101且将其一体地支承的作用。
专利文献1
特开平11-340257号公报
但是，在所述的半导体装置100中，当电位相差很大的引线101相互接近时，在两者之间有可能产生漏电流。特别是存在当一个引线101的阻抗高时，由于该漏电流流入阻抗高的引线101，在装置内部构成的电流的特性发生变化的问题。
本发明是着眼于上述的问题点而开发的，本发明的主要目的在于，提供一种具有抑制图案间的漏电流的结构的电路装置。
发明内容
本发明的电路装置，具有电路元件和导电图案，其特征在于，包括：第一导电图案，其和所述电路元件的高阻抗的输入端子连接；第二导电图案，其接近所述第一导电图案而设置；保护导电图案，其延伸设置在所述第一导电图案和所述第二导电图案之间；以及垫片，其由所述导电图案形成并且在上面粘接有半导体元件，其中，所述保护导电图案与所述垫片电连接。
另外，本发明的电路装置具有如下特征，所述保护导电图案采用电位最接近所述第一导电图案的所述导电图案。
另外，本发明的电路装置具有如下特征，利用所述保护导电图案将所述第一导电图案包围。
另外，本发明的电路装置具有如下特征，具有由第一配线层及第二配线层构成的多层配线结构，并在所述第一配线层或第二配线层上形成所述保护导电图案。
另外，本发明的电路装置具有如下特征，露出所述导电图案的背面，利用密封树脂将所述电路元件及所述导电图案密封。
另外，本发明的电路装置具有如下特征，所述第一导电图案被连接在OP放大器的输入端子上。
另外，本发明的电路装置具有如下特征，所述保护导电图案和接地电位连接。
另外，本发明的电路装置具有如下特征，所述保护导电图案与所述垫片一体地形成。
根据本发明的电路装置，可通过在电位不同的导电图案之间延伸设置保护导电导电图案来抑制装置内部的漏电流。由此，可提高内装于装置内的电路的特性。另外，由于可在安装衬底侧形成省去用于防止漏电流的结构，故可简化安装衬底的图案结构。
附图说明
图1是表示本发明电路装置的平面图(A)、剖面图(B)、剖面图(C)；
图2是表示本发明电路装置的平面图(A)、剖面图(B)；
图3是表示本发明电路装置的平面图(A)、剖面图(B)；
图4是表示本发明电路装置的剖面图；
图5是表示本发明电路装置的剖面图；
图6是表示现有的电路装置的平面图(A)、剖面图(B)。
具体实施方式
参照图1说明本实施方式的电路装置10的结构。图1(A)是电路装置10A的平面图，图1(B)及图1(C)是其剖面图。
参照图1(A)，本实施方式的电路装置10具有电路元件13和规定的导电图案12，并一体地树脂模制。另外，具有与电路元件13的高阻抗输入端子连接的第一导电图案12A和接近第一导电图案设置的第二导电图案12B。还具有在第一及第二导电图案之间延伸设置的保护导电图案12C，防止第一导电图案12A和第二导电图案12B之间的漏电流。以下详细地说明各要素及相关结构。
第一导电图案12A、第二导电图案12B及保护导电图案12C由铜等金属构成。并且，这些导电图案12由在利用蚀刻形成的分离槽19内填充的密封树脂18分离。
在此，电路元件13由半导体元件13A及芯片元件13B构成。另外，电路元件13可采用LSI芯片、晶体管裸片、二极管等有源元件。另外，电路元件13还可采用片状电阻、片状电容、或电感元件等无源元件。半导体元件13A的其背面固定粘接在由导电图案12形成的垫片上。并且，介由金属细线15将半导体元件13A的表面电极和由导电图案12构成的焊盘电连接。另外，半导体元件13A也可以利用倒装法连接。片状元件13B其两端电极介由焊锡等焊料固定粘接在导电图案12上。
密封树脂18由采用注入模形成的热塑性树脂或采用传递模形成的热硬性树脂构成。并且，密封树脂18具有密封装置整体的作用，同时，还具有机械地支承装置整体的功能。参照图1(B)，密封树脂18使导电图案12的背面露出外部而密封电路元件13、金属细线15及导电图案12。
另外，导电图案12露出的密封树脂18的下面，除形成外部电极17的位置外，被由树脂构成的抗蚀剂16覆盖。外部电极17由焊锡等焊料构成，形成在导电图案12的背面。
参照图1(A)，具体说明本发明的优点即抑制漏电流的导电图案12的结构。
参照图1(A)的第一区域A1，第一导电图案12A介由金属细线15和半导体元件13A电连接。并且，该第一导电图案12A和其它导电图案比较，是阻抗高的导电图案。例如，第一导电图案12A可连接在OP放大器(Operational Amplifier)的倒相输入部或非倒相输入部。因此，第一导电图案12A的阻抗是例如数百千欧姆至数百万欧姆程度，非常高。换而言之，流经第一导电图案12A的电流非常小。具体地，流经连接于运算放大器的输入端子的第一导电图案12A的电流的值是例如数微安程度。在此，第一导电图案12A连接在作为IC的半导体元件13A上，也可以连接在上述的其它电路元件13上。
第二导电图案12B接近上述的第一导电图案12A而设置。该第二导电图案12B是和上述的第一导电图案12A电位不同的导电图案。例如，第二导电图案12B可采用电位高于第一导电图案12A的图案或电位低于第一导电图案12A的图案。例如，第二导电图案12B采用施加数十伏特电压的图案。
这样，第一导电图案12A和第二导电图案12B的电位不同。由此，有可能由于该电位差自第二导电图案12B向第一导电图案12A流入漏电流。考虑到第一导电图案12A的阻抗高、第二导电图案12B的电位高，该问题是显著的。其理由是有可能因漏电流导致产生运算放大器的误动作。因此，在本申请中，通过保护导电图案12C来解决该问题。
保护导电图案12C延伸设置在第一导电图案12A和第二导电图案12B之间，抑制第一导电图案12A和第二导电图案12B之间产生的漏电流。在此，保护导电图案12C直线型延伸设置在第一导电图案12A和第二导电图案12B之间。保护导电图案12C采用与第二导电图案12B相比电位更接近第一导电图案12A的导电图案。另外最好是，保护导电图案12C也可以采用在构成电路装置10A的导电图案12中电位最接近第一导电图案12A的导电图案12。另外，保护导电图案12C可采用和内装于装置的电路元件13电连接的导电图案12。
在电路装置10A内部没有电位接近第一导电图案12A的导电图案12时，可从电路装置外部引入接近第一导电图案12A的电位。具体地，可介由外部电极17从安装电路装置10A的衬底侧的导电路将电位引至保护导电图案12C上。在这样的情况下，保护导电图案12C不必和电路元件13连接。由此，这时，可仅由延伸设置在第一导电图案12A和第二导电图案12B之间的配线部构成保护导电图案12C。
考虑第一导电图案12A采用运算放大器的输入端子。将运算放大器的输入电位较小地设定时，保护导电图案12C可采用和接地电位连接的导电图案12。通过该结构，即使从电位高的第二导电图案12B向第一导电图案12A侧流入漏电流时，其漏电流也被保护导电图案12C吸收。另外，如上所述，由于第一导电图案12A和保护导电图案12C电位近似，故在两者之间基本不产生漏电流。
参照图1(A)的第二区域A2说明用于解决由漏电流引起的问题的另一结构。在此，包围第一导电图案12A周围形成保护导电图案12C。通过该结构，可进一步提高防止漏电流流入第一导电图案12A的效果。另外，即使在第一导电图案12A被电位不同的第二导电图案12B包围的情况下，也可以通过该结构防止漏电流流入。在此，环状的保护导电图案12C被电连接在电路元件13上，但如上所述，也可以自电路装置10A的外部引入电位。
参照图1(A)的第三区域A3，说明用于解决漏电流引起的问题的其它结构。在此，保护导电图案12C介由配线部12D从分开的导电图案12引入。电位接近第一导电图案12A的导电图案有从第一导电图案12A分开的情况。此时，可通过延伸设置配线部12D形成保护导电图案12C。在此，也可以使用金属细线15来代替由导电图案12构成的配线部12D。
参照图1(C)，在此，电路元件13采用半导体元件13A及片状元件13B。这样，也可以使多个电路元件13内装在电路装置10A内。
参照图2说明另一实施方式的电路装置10B的结构。图2(A)是电路装置10B的平面图，图2(B)是其剖面图。该图所示的电路装置10B的基本结构和图1所示的10A相同，不同点在于导电图案12的延伸结构。以该不同点为中心说明。
参照图2(A)的第四区域A4，本实施方式的保护导电图案12C延伸设置在作为电路元件13的半导体元件13A的下方。电位接近位于该区域A4的第一导电图案12A的导电图案12E位于平面上隔着半导体元件13A的位置。具体地，第一导电图案12A和电位接近该图案的导电图案12E位于电路装置10B的相对的周边部附近。在本申请中，可介由延伸设置在半导体元件13A下方的配线部12D将保护导电图案12C和导电图案12E电连接。即，除配置电路元件13的区域外可不配置图案而直线连接导电图案12之间。
参照图2(A)的第五区域5A，在第一导电图案12A和第二导电图案12B之间延伸设置的保护导电图案12C未和电路元件13电连接。即，保护导电图案12C形成作为配线部延伸设置的部分，介由外部电极17和电路装置10B的外部连接。通过该结构，即使在电路装置10B内部的导电图案12中没有电位与第一导电图案12A近似的导电图案12时，也可以从外部得到该电位。
参照图2(B)，说明电路装置10B的断面结构。导电图案12由覆盖树脂24覆盖，在该覆盖树脂24的表面固定粘接有半导体元件13A。通过该结构，可在配置半导体元件13A等电路元件13的区域的下方配置导电图案12，故可提高配线密度。另外，和电路元件13电连接的位置的导电图案12上面自覆盖树脂24露出。这里，从覆盖树脂24露出构成焊盘的区域的导电图案12的上面。
参照图3说明其它实施方式的电路装置10C的结构。图3(A)是电路装置10C的平面图，图3(B)是其剖面图。该图所示的电路装置10C的基本结构和图1所示的电路装置10A相同，不同点在于具有多个配线层。以该不同点为中心说明。
参照图3(A)，作为上层配线层的第一配线层20由实线表示，作为下层配线层的第二配线层21由虚线表示。参照该图的第六区域A6，第一导电图案12A、第二导电图案12B及保护导电图案12C由第一配线层20形成。这样，同样可利用由第一配线层20构成的保护导电图案12C抑制同样由第一配线层20构成的第一导电图案12A和第二导电图案12B之间发生的漏电流。
参照同图的第七区域A7，在此，第一导电图案12A及第二导电图案12B由第一配线层20构成，保护导电图案12C由第二配线层构成。即，参照图3(B)，可通过由下层的第二配线层21构成的保护导电图案12C来抑制上层的第一配线层20相互之间的漏电流。在此的保护导电图案12C也可以介由连接部23和第一配线层20或电路元件13电连接。另外，在此的保护导电图案12C也可以和第一配线层20或电路元件13电连接。
参照同图的第八区域A8，在此，第一导电图案12A及第二导电图案12B由第一配线层20构成。然后，利用由第二配线层21构成的配线部12D配置保护导电图案12C。因此，即使和第一导电图案12A电位近似的导电图案12位于与第一导电图案12A分开的位置时，也可以利用在第二配线层21上形成的配线部12D来进行图案的配置。
参照图3(B)，在此，具有由介由绝缘层32层积的第一配线层20及第二配线层21构成的双层配线层。第一配线层20和第二配线层21介由贯通绝缘层32的连接部23电连接。另外，配线层的结构也可以构成三层以上的配线结构。
在上述的说明中，说明了用于抑制上层的第一配线层20相互之间的漏电流的结构，但也可以利用同样的结构来抑制下层的第二配线层21相互之间的漏电流。即，可通过在第一配线层20上形成保护导电图案12C，防止第二配线层21相互之间的漏电流。另外，也可通过在第二配线层21上设置保护导电图案12C，防止第一配线层20相互之间的漏电流。另外，也可以在第一配线层20及第二配线层21两层上形成同样形状的保护导电图案12C，进一步通过防止漏电流的效果。
参照图4，说明其它实施方式的电路装置10D的结构。该图剖面表示的电路装置10D的基本结构和图3所示的电路装置10C相同。不同点在于，具有支承衬底31。该支承衬底31可采用玻璃环氧衬底等树脂制衬底、陶瓷衬底、金属衬底等周知的衬底。
参照图5的剖面图说明安装在安装衬底25上的电路装置10A的结构。在此，用图1说明的电路装置10A说明，但以下的结构也可以适用其它图说明的电路装置10。
介由由在导电图案12背面形成的焊料构成的外部电极17将电路装置10A固定粘接在在安装衬底25表面形成的导电路26上。第一导电图案12A介由外部电极17连接在第一导电路26A上。第二导电图案12B介由连接电极17连接在第二导电路26B上。另外介由外部电极17将保护导电图案12C连接到安装衬底25侧的保护导电路26C上。在此，安装衬底25侧的保护导电路26C不必和保护导电图案12C连接，也可以连接到电位接近第一导电图案12A的其它部分。
通过在电路装置10A内部设置保护导电图案12C，可抑制漏电流流入第一导电图案12A。另外，可通过在安装衬底25侧也设置保护导电路26C，提高该效果。具体地，即使在导电路26的表面附着有尘埃等时，也可以抑制导电路26相互之间产生的漏电流。

Claims (8)

1. 一种电路装置，具有电路元件和导电图案，其特征在于，包括：第一导电图案，其和所述电路元件的高阻抗的输入端子连接；第二导电图案，其接近所述第一导电图案而设置；保护导电图案，其延伸设置在所述第一导电图案和所述第二导电图案之间；以及垫片，其由所述导电图案形成并且在上面粘接有半导体元件，
其中，所述保护导电图案与所述垫片电连接。
2. 如权利要求1所述的电路装置，其特征在于，所述保护导电图案采用电位最接近所述第一导电图案的所述导电图案。
3. 如权利要求1所述的电路装置，其特征在于，由所述保护导电图案包围所述第一导电图案。
4. 如权利要求1所述的电路装置，其特征在于，具有由第一配线层及第二配线层构成的多层配线结构，并在所述第一配线层或第二配线层上形成所述保护导电图案。
5. 如权利要求1所述的电路装置，其特征在于，露出所述导电图案的背面，利用密封树脂将所述电路元件及所述导电图案密封。
6. 如权利要求1所述的电路装置，其特征在于，所述第一导电图案被连接在OP放大器的输入端子上。
7. 如权利要求1所述的电路装置，其特征在于，所述保护导电图案和接地电位连接。
8. 如权利要求1所述的电路装置，其特征在于，所述保护导电图案与所述垫片一体地形成。
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