TWI225668B - Substrate processing method - Google Patents
Substrate processing method Download PDFInfo
- Publication number
- TWI225668B TWI225668B TW092107213A TW92107213A TWI225668B TW I225668 B TWI225668 B TW I225668B TW 092107213 A TW092107213 A TW 092107213A TW 92107213 A TW92107213 A TW 92107213A TW I225668 B TWI225668 B TW I225668B
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- Taiwan
- Prior art keywords
- substrate
- processing method
- film
- oxide film
- substrate processing
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 103
- 238000003672 processing method Methods 0.000 title claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 107
- 238000011282 treatment Methods 0.000 claims abstract description 53
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 49
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 27
- 239000001301 oxygen Substances 0.000 claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 11
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 3
- 238000005121 nitriding Methods 0.000 claims description 52
- 239000007789 gas Substances 0.000 claims description 35
- 229910052757 nitrogen Inorganic materials 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 13
- 230000014759 maintenance of location Effects 0.000 claims description 12
- 230000005855 radiation Effects 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000005284 excitation Effects 0.000 claims description 3
- 238000002309 gasification Methods 0.000 claims description 3
- 229910052743 krypton Inorganic materials 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims 1
- 229910052754 neon Inorganic materials 0.000 claims 1
- 238000002360 preparation method Methods 0.000 claims 1
- 229910052724 xenon Inorganic materials 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 57
- 229910052710 silicon Inorganic materials 0.000 description 57
- 239000010703 silicon Substances 0.000 description 57
- 238000006243 chemical reaction Methods 0.000 description 19
- 125000004433 nitrogen atom Chemical group N* 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000009826 distribution Methods 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 12
- 125000004430 oxygen atom Chemical group O* 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000007423 decrease Effects 0.000 description 9
- 230000009467 reduction Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 150000003254 radicals Chemical class 0.000 description 7
- 238000002474 experimental method Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 241001674048 Phthiraptera Species 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- -1 silicon oxide nitride Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
1225668 玖、發明說明: 【技術領域】_ ,特別與在矽基板表面 本發明一般與基板處理方法有關 形成之氧化膜之氮化方法有關。 隨微細化技術之發展,目侖? ^ 1 曰則己漸有可能製造以具有oa //m以下閘極長度之超微細化半導體裝置。 於此種超微細化半導體裝置,侔隋間 | 件1思閘極長度 < 縮短而欲 提升半導體裝置之工作速度時,彡g u夕 ^ T肩要將閘極絕緣膜厚度依 定標法則減少。例如先前使用熱氧化膜為間極絕緣膜時, 須要將閘極絕緣膜厚度減少至先前之1711111以下。但如將 虱化膜厚度如此減少時,因隧道效應使通過氧化膜之閘極 漏洩電流增大。 為此,曾探討以TkO5或Hf〇2' Zr〇2等高電介質膜(即所 謂high-K電介質膜)取代先前之矽氧化膜而使用為閘極絕 緣膜。但此等高電介質膜與半導體技術先前使用之碎氧化 膜之性質大不相同’使用此等鬲電介質膜為閘極絕緣膜時 尚有許多須要解決之課題。 相對於此,矽氮化膜或矽氧氮化膜為先前使用之半導體 處理材料,且具有石夕氧化膜之1 · 5〜2倍之介電常數比,故 當做下一世代高速半導體裝置之閘極絕緣膜為極有希望 之材料。 【先前技術】 向來矽氮化膜通常以電漿CVD法在層間絕緣膜上形 成。但此種CVD氮化膜一般具有多項缺點,且其漏戌電流 84421.doc 1225668 大,故不適合當做閘極絕緣膜。因此從未試用氮化膜為閘 極。 對此,最近有提示在被微波激發之Ar或Kr等稀有氣體之 電漿中導入氮或氮與氫或如NH3氣體之含氮氣體,使發生N 游離基或NH游離基,以氮化矽氧化膜表面而變換為氧氮化 膜之技術。如此形成之氧氮化膜,其熱氧化膜換算膜厚度 小,並具有超越熱氧化膜之漏戌電流特性,故被認為當做 下一世代高速半導體裝置之閘極絕緣膜極有希望。如此形 成之氧氮化膜其化學性安定,在氧氮化膜上形成高電介質 膜時,能夠抑制金屬元素通過上述氧氮化膜中而在高電介 質膜中擴散,及抑制由此種擴散引起高電介質膜與矽基板 間之反應。另外亦有提示將矽基板表面以此種微波電漿直 接氮化之技術。 向來導入氮於氧化膜中之方法,已知有在氮氣氛中進行 熱處理或注入氮離子等,但在此等方法,已知被導入之氮 原子大量集中於矽基板與氧化膜之界面附近。其結果,如 使用此種先前之氧氮化膜為MOS電晶體之閘極絕緣膜 時,會發生因形成界面位準引起之臨限值電壓變動及互導 (mutual conductance)劣化等問題。 同理,在N游離基或NH游離基處理形成之氧氮化膜,如 不適當控制膜中氮原子之分佈,則不僅無法獲得所希望半 導體裝置特性之提升,反而引起特性之劣化。 又使用感應搞合型電漿(ICP、inductively coupled plasma) 等高能量電漿氮化處理氧化膜而形成氧氮化膜時,在氮化
84421.doc 1225668 處理後如不進行熱處理使該膜由電漿之損害回復,則無法 獲知所希望特性之氧氮化膜。但此種熱處理不僅多餘, 並引起氧氮化膜更進一步之氧化及伴隨增加氧氮化膜膜 厚度等問題。 【發明内容】 在此本發明以解決上述課題,提供新穎有用之基板處 理方法為概括目的。 本發月之更具f豆目的為在以微波電漿氮化處理氧化膜 以形成氧氮化膜之基板處理方法中,提供能夠避免被導入 膜中之氮原子偏析於矽基板與氧氮化膜之界面,抑制在上 述界面 < 氧化膜再成長,且氮化處理後無須進行熱回復處 理之基板處理方法。 本發明之其他目的為 於氮化矽基板表面形成之氧化膜為氧氮化膜之基板處 理方法中,提供 包含以微波激發電漿激發氮氣,以其形成之游離基或離 子氮化上述氧化膜之氮化處理步驟, 上述氮化處理步驟在500°C以下基板溫度,上述微波激 發電裝之電子溫度設定為2eV以下,及保持上述被處理基 板之處理空間中之氧滯留時間設定為2秒以下條件實施之 基板處理方法。 依據本發明,因設定微波電漿之電子溫度為2eV以下、 較好leV以下、最好〇.9eV以下,而可抑制導入電漿損害於 氧氮化膜中。又此時設定處理空間中氧滯留時間為2秒以 84421.doc 1225668 下、較好!秒以下、最好_秒 離之氧原子快速由處理空間中去除,=乳化氧氮化膜脫 之而亩桩而可抑制因上述脫離 <乳而直接在錢化膜正下方產生氧化膜 500°C以下溫度進杆翁仆忐w 再成長。又在 又進仃虱化處理,可使導入之 膜與矽基板之界面擴鸯,κ虱原子在乳化 “,抑制形成界面準位等缺陷之問 嗵。另外在此種氮化處理步驟,益 熱回復處理。 」要…化處理後之 本發明之其他課題及特徵,由 、… 寸试J由以下參照圖式之本發明 足評細說明而明瞭。 【實施方式】 [第一實施例] 圖1為本發明使用之電漿基板處理裝置1〇之概路構成。
參照圖1,電漿基板處理裝置10具有區分為由排氣孔11B 排氣之處理空間11A之處理容器u,在上述處理空間UA中 設置保持被處理基板w之基板保持台12。本發明使用之電 漿處理裝置10,上述處理空間11A,具有例如24公升容積。 上述處理容器11之上方形成開口部,與上述基板保持台 12上之被處理基板w相面對,上述開口部由石英、氧化鋁 等低彳貝失電介質組成之盖板13覆蓋。在此蓋板13下方面對 上述被處理基板W形成多數氣體導入路14,此氣體導入路 14對上述被處理基板w形成如軸向對稱性關係。 上述蓋板1 3形成微波窗口,而在上述蓋板13之外側形成 库备射狀線隙縫天線(radial line slot antenna)或號角天線等 微波天線1 5。 84421.doc -9- 工作時則述處理答器11之内部處理空間11A介前述排氣 孔11B排氣而農定為既定處理壓,再由前述氣體導入路14 將Ar或Kr等惰性氣體及氧氣或氮氣同時導入。 其次介前述天線15導入數GHz頻率之微波,在前述處理 容器11中之被處理基板W表面激發高密度微波電漿。以微 波激發電漿之結果,在圖丨之基板處理裝置中電漿之電子 溫度低,故能避免被處理基板冒及處理容器u之内壁受損 咅。再者,所形成之游離基沿被處理基板w表面向徑方向 流動並快速排氣,故能抑制游離基再結合,而使有效率且 極均勻之基板處理在50(rc以下低溫成為可能。 圖2A、2B為由輻射狀線隙缝天線形成之微波天線丨5之概 略構成。其中圖2 A為呈現輻射狀線隙縫天線丨5放射面之平 面圖’而圖2B為輻射狀線隙縫天線15之剖面圖。 參照圖2B之剖面圖,輻射狀線隙縫天線丨5由連接於同軸 導波官15A之外側波導管之平面碟狀天線本體15B與形成 於上述天線本體15B開口部之放射板15(:組成,而如圖2A 所示放射板15C由多數隙缝i5a及與此直交之多數隙缝15b 形成’另於上述天線本體15B與上述放射板15C之間插入由 既定厚度電介質膜形成之滯相板丨5D。 在此種構成之輻射狀線隙缝天線丨5,由上述同軸導波管 15A供電之微波,在上述碟狀天線本體15B與上述放射板 15 C之間’一面向半徑方向擴散一面前進,此時波長受上 述滞相板15D之作用而被壓縮。因此,為對應此種向半徑 方向前進之微波波長,將上述隙缝15a與15b直交並排列成 84421.doc -10- 同心圓狀,即可由上述隙縫15a與15b對上述放射板15C, 實際上以垂直方向放射整體而言具有扁圓形波之平面波。 圖3表示在圖1電漿基板處理裝置之處理壓與電子溫 度之關係及處理壓與電子密度之關係。但圖3中之此種關 係’為供給Ar氣與氮氣於上述處理容器丨丨之處理空間 11A,並由上述輻射狀線隙缝天線/ 電 力岔、度供給頻率2·45GHz之微波於上述處理空間11 a時之 關係。 參照圖3時可知在上述處理空間11A呈現14ev &下之極 低電子溫度,且電子溫度隨處理壓之增加而再減低,例如 於70Pa以上處理壓則電子溫度減低至leV或以下。 又依據圖3可知在上述處理空間11A呈現1 X 1〇u〜i χ 1012cm 3之極高電子密度。尤其設定處理壓為71^時,可呈 現1.4Xl〇12cm-3之電子密度。電子密度亦隨處理壓增加而 減低,但在70Pa以上處理壓則電子密度大約保持3 χ 101 icnT3。 圖4A〜4C為使用圖1基板處理裝置1〇之本發明之一實施 例之基板處理步驟。 參照圖4 A,將矽基板2丨以R C A洗淨後當做前述被處理基 板W導入前述基板處理裝置1〇之處理容器丨丨中,由前述氣 體導入路14導入Kr與氧氣之混合氣體,使其以頻率 2.45GHz微波激發電漿而形成原子狀氧〇*。以此原子狀氧 〇*處理上述矽基板21表面結果,如圖3A所示,在矽基板21 表面形成厚度約1.6nm矽氧化膜22(基底氧化膜)。如此形成 84421.doc -11- 1225668 之矽氧化膜22,雖然在400°C左右之極低基板溫度形成, 但具有與l〇〇O°C以上高溫形成之熱氧化膜相當之漏洩電 流特性。又上述碎氧化膜22亦可為熱氧化膜或以濕式處理 形成之化學氧化膜。 其次於圖4B之步騾,供給At*與氮氣之混合氣體於圖1之 基板處理裝置10之處理容器11中,設定基板溫度為400t利 用供給微波以激發電漿。
於圖4B之步驟,設定處理容器11之内部壓力為7〜 13 0Pa,將Ar氣以例如200〜2000 SCCM流量、氮氣以例如8 〜150 SCCM流量供給,再進行10〜40秒之電漿處理。其結 果,前述矽氧化膜22之表面被氮化,於是矽氧化膜22變換 為矽氧氮化膜22A。 其次於圖4C,在如上述所得矽氧氮化膜22A上形成聚矽 電極23。因此於圖4C,可獲得在矽基板21與聚矽電極23之 間夾有矽氧氮化膜22A之MOS電容器。
圖5及圖6為就如此所得矽氧氮化膜22A求得氧化膜換算 膜厚度EOT與漏洩電流密度之關係,及氧化膜換算膜厚度 EOT與扁帶電壓Vfb之關係。又圖5亦表示基底氧化膜22之 漏洩電流特性以供比較。但於圖5及圖6,其圖4B之氮化處 理步驟,乃設定基板溫度為400 °C、Ar氣流量為1000 SCCM、氮氣流量為40 SCCM,並由上述輻射狀線隙縫天 線15以1.1 W / cm2電力密度供給頻率2.45GHz之微波於上 述處理空間11A中而進行。又於圖5及圖6之實驗,其處理 壓分別設定為7Pa與67Pa。 84421.doc -12 - 1225668 參照圖5,如以7Pa處理壓進行圖4B之氮化處理時,可知 上述矽氧氮化膜22A之氧化膜換算膜厚度EOT,在氮化處 理時間為10秒以下範圍時隨氮化處理時間之減少而減少 之趨勢,但此趨勢在氮化處理時間超過1〇秒到達2〇秒之間 表現變化,而當超過20秒時則氧化膜換算膜厚度Ε〇τ隨氮 化處理時間之增多而轉向增多。 此時以7Pa處理壓進行氮化處理較以67pa處理壓進行氮 化處理,其氧化膜換算膜厚度之減少幅度較大。 其次參照圖6,可知氮化處理時間為1〇秒以下時無論以 7Pa或67Pa進行氮化處理,在圖4C之構造中之扁帶電壓 均幾供變化,但氮化處理時間超過丨〇秒時則扁帶電壓 開始急劇減少。 圖5及圖6之關係暗示依圖丨之基板處理裝置丨〇以前述條 件進行氧化膜之氮化處理時,如氮化處理時間超過1 〇秒, 則在前述矽氧氮化膜22A中產生某種變化。 圖7為如上之矽氧氮化膜22八中氮原子之深度分佈,而圖 8為上述矽氧氮化膜22A中氧原子之深度分佈。但於圖7及 圖8’ _代表以7Pa處理恩進行圖4B之氮化處理2〇秒,◊代 表以7Pa處理壓進行氮化處理4Q秒,而△代表以伽處理 壓進行圖4B之氮化處理2〇秒,〇代表以㈣處理壓進行氮 化處理40秒。 发參照圖7,可知無論任何情形氮原子在厚度約咖之氧 鼠化月吴中,以稍接近表面處之深度俱有♦值之分布圖分 佈故未見在先則〈為氮化或電聚氣化氧化膜時出現氮原 84421.doc -13- 1225668 子濃度集中於氧化膜與矽基板界面之情形。又由圖7,可 知氮化處理時間增加則導入矽氧氮化膜22 A中氮原子之濃 度增多,另外圖7亦表示,減低圖4B氮化處理步·驟之處理 壓時,導入矽氧氮化膜22A中氮原子之濃度亦增多。 另一方面,圖8顯示隨氮化處理之進行氧濃度在矽氧氮 化膜22 A中減少之情形,如以同一處理壓比較時處理時間 較長則較1.6nm深,亦即在相當於矽基板表面部分領域之 氧濃度約略高於短處理時間者,此乃暗示隨氮化處理之進 行矽氧氮化膜22A中之氧原子向矽基板中移動,而在矽氧 氮化膜22A正下方產生氧化膜之再成長。因此隨此種氧化 膜之再成長,而產生圖5、圖6之轉向現象及一度減少之石夕 氧氮化膜22 A之氧化膜換算膜厚度EOT再增加。 圖8亦表示,以較低壓7Pa進行圖4B之氮化處理步驟時, 對抑制矽氧氮化膜22A正下方產生氧化膜之再成長較有 效0
圖9為於圖4B之氮化步驟,改變Αι:氣與氮氣流量以形成 矽氧氮化膜22A時,其漏洩電流與氧化膜換算膜厚度EOT 之關係。但於圖9之實驗,設定基板溫度為400°C、處理壓 為7Pa,並由前述輻射狀線隙缝天線以1.1 W/cm2電力密度 供給頻率2.45GHz之微波於前述處理空間11A中而導入。又 在本實驗中,Ar氣與氮氣之比例固定為25 : 1。 圖9中,△代表設定Αι:氣流量為200SCCM、氮氣流量為 8SCCM,◊代表設定Ar氣流量為500SCCM、氮氣流量為 20SCCM,代表設定Ar*氣流量為1000SCCM、氮氣流量為 84421.doc -14- 1225668 40SCCM。 參照圖9,可知一度減少之氧化膜換算膜厚度EOT轉為再 度增加之轉向點可因導入處理空間11A中之Ar氣與氮氣總 流量而改變,增加上述總流量時可增大氧化膜換算膜厚度 EOT之減少幅度。
於圖9之實驗,獲知導入上述處理空間11A中之氣體總流 量大時氧化膜換算膜厚度EOT之減少幅度大,而氣體總流 量小時減少幅度亦小之事實,如與圖5、圖6之實驗獲知處 理壓低時氧化膜換算膜厚度EOT之減少幅度大而處理壓高 時減少幅度亦小之事實合併考量,則似可推測上述處理空 間11A中之氧原子滯留時間可能決定氧化膜換算膜厚度 EOT之減少幅度。
處理壓低時或氣體總流量大時,上述處理空間11A中之 氧滯留時間短,隨氮化反應由上述矽氧氮化膜22 A排出之 氧原子立即由處理空間11A向外排出。另一方面,處理壓 高時或氣體總流量小時,上述處理空間11A中之氧滯留時 間長,隨氮化反應由上述矽氧氮化膜22 A排出之氧原子在 上述處理空間11A留存於電漿氣氛中,結果由上述矽氧氮 化膜22A向處理空間11A排出氧原子停滯,故矽氧氮化膜 22A中多餘之氧向矽基板21擴散,而在矽氧氮化膜22A與矽 基板21間之界面產生氧化膜之再成長。 圖10A及圖10B為由上述見解引導之本發明之電漿氮化 氧化膜之機制。 參照圖10A,在處理空間11A中,即氧在電漿中滯留時間 84421.doc -15- 丄心668 短時’因氮原子切斷Si - 〇耦合而被排出之氧原子擴散到 達處理空間11A時立即去除,但相對於此,如圖1〇B所示氧 《滯留時間長時,電漿中存在高濃度之活化氧游離基,而 此氧游離基再度回到矽氧氮化膜22A中使矽基板21發生氧 化。
圖11A及圖11B為就分別以7Pa&67Pa處理壓氮化處理之 矽氧氮化膜22 A,求得施加電壓Vg與漏洩電流密度;關係之 結果。於圖11八及圖116中,實線代表圖4八之氧化膜22之漏 或私/瓦特性,代表進行圖4B之氮化處理1 〇秒之矽氧氮化 膜之漏洩電流特性,◊代表進行上述氮化處理2〇秒之矽氧 氮化膜之漏洩電流特性,△代表進行上述氮化處理4〇秒之 矽氧氮化膜之漏洩電流特性。
參照圖11A、圖11B,可知在外施加電壓vg大於一 1 v( < —IV)之高偏壓區各矽氧氮化膜均表現相同漏洩電流特 性,但在外加電壓Vg小於一iv(> — IV)之低偏壓區域,以 7Pa處理壓形成之矽氧氮化膜之漏洩電流值較最初矽氧化 膜22之漏洩電流值約增大1〇倍。相對於此,以67pa處理壓 形成之矽氧氮化膜之漏洩電流則僅增大一些。 低偏壓區域之漏洩電流,已知與界面缺陷或表體缺陷 (bulk trap)相關(參照 Ghetti,A·,et al.,IEDM Tech· Dig. Ρ·731,1999)’圖11A、圖11B之結果,暗示以7Pa低處理壓 形成之矽氧氮化膜中有因電漿處理產生損害之可能性。 圖12為在圖1基板處理裝置10之處理空間11A中所發生 射入被處理基板之離子能量分佈及電子溫度分佈,以處理 84421.doc -16- 1225668 壓之函數表示。 參照圖12,在圖1基板處理裝置10可獲得極低之電子溫 度分佈,但無法避免隨電漿激發而產生離子。例如於約7Pa 處理壓不能避免具有約7 ev能量之離子射入被處理基板。因 此’在氮化厚度約lnm之極薄氧化膜時,這種較低能量離 子亦有可能對氧化膜給予某種程度之損害。 由圖12之關係,可知射入基板之離子能量與電子溫度均 隨處理壓之增加而減少。si_ 〇耦合之耦合能為46eV,故 欲避免因離子衝擊之損害,則由圖12之關係,可將處理壓 增加至llOPa以上、最好130Pa以上,使離子能量減低至上 述4.6eV程度或以下。則如處理壓增加至13〇Pa以上時電子 溫度可減低至〇 · 9 eV或以下。 另一方面,如此增大處理壓時,由先前圖5、6或圖7、8 之結果可知會發生在;?夕氧氮化膜22A正下方容易產生氧化 膜再成長之問題。
於是本發明依據圖9及圖i〇A、10B之見解,增大處理空 間10A中之氣體流量、縮短氧滯留時間,以避免上述問題。 更具體而言,在圖4B之氮化步驟設定處理壓為13〇Pa, 並供給2000SCCM流量Ar氣及150SCCM流量氮氣於上述處 理空間11A。由此,如進行40(rc、1〇秒之氮化處理所得矽 氧氮化膜22A之氧化膜換算膜厚度Ε〇τ,可能減少至約 1.2nm。此時氧在上述處理空間UA之滯留時間為〇 86秒(= 2400 / (2150 * 101325 / 130)* 60)。如此,本發明使用較高 處理壓及增大氣體流量以抑制氧在處理空間之滯留時 84421.doc -17- 1225668 間,在避免矽氧氮化膜損害、抑制矽氧氮化膜正下方之氧 化膜再成長情形下,導入多量氮於石夕氧氮化膜中,乃可能 使氧化膜換算膜厚度減少。 本發明亦可設定上述Αι*氣流量為1700SCCM、氮氣流量 為150SCCM 〇此時上述氧滯留時間為1.0秒。再者如圖9所 示亦可設定Ar氣流量為1000SCCM、氮氣流量為40SCCM。 此時氧在處理空間11A之滯留時間為1.78秒。 一般而言,欲獲得本發明之效果,將氧滯留時間設定為 2秒以下即可,尤其將滯留時間設定為1秒以下更好。 圖13為圖4B之氮化處理步騾之溫度在100〜500°C範圍 内改變時,所得矽氧氮化膜22 A之漏洩電流特性。但圖13 中之縱座標為以矽氧氮化膜22 A為基準之漏洩電流密度低 減率(J Si02 / J SiON ; J為漏洩電流密度)。 參照圖13,可知基板溫度在250〜500°C範圍時漏洩電流 低減率為約10〜11,但將基板溫度再降低時漏洩電流低減 率值亦減少,在1 〇〇°C進行處理時可減少至約5。 此種在低基板溫度時漏洩電流低減率減少之原因未 明,可能為降低基板溫度時,不能充分回復電漿處理時無 法避免或多或少導入膜中之損害所致。 由圖13之關係,吾人可瞭解使用500°C以上高基板溫度 時可再減低漏洩電流密度之可能性,但在電漿氮化處理時 如增大基板溫度至500°C或以上,則如圖14所示,導入矽 氧氮化膜22A中之氮原子擴散至矽氧氮化膜22A與矽基板 2 1之界面,而在此被捕獲形成界面準位之慮。相較於此,
84421.doc -18- 1225668 將基板溫度設定為50(TC以下,例如40(rc時,由適當控制 氮化處理時間t,而可能抑制此種氮原子向界面擴散。 由上述討論,可獲得之結論為在圖4B之矽氧化膜22之氮 化處理步驟,最好在l〇(TC以上500t:H下之基板溫度,尤 其250°C〜400°C範圍進行。 以上就矽基板上形成之氧化膜之電漿氮化,使用被輻射 · 狀線隙缝天線放射之微波激發之低電子溫度電漿進行加 以說明,但本發明亦適用於以其他方法激發之電漿,例如 以感應耦合型電漿(ICP)氮化氧化膜之場合。亦即,在此種 _ 場合亦增大氣體流量使氧滯留時間抑制在2秒以下、最好1 秒以下,則可有效去除由形成之氧氮化膜排出之氧原子, 因而抑制氧氮化膜正下方之氧化膜再成長。 [弟2實施例] 圖15為依據本發明第2實施例之CMOS元件40之構成。 參照圖15, CMOS元件40形成於被元件分隔構造41C區分
成元件區域41A及41B之矽基板41上,而在上述元件區域 41A形成P型井,元件區域41B則形成η型井。 在上述元件區域41Α上介閘極絕緣膜42Α形成聚矽閘極 電極43A ’而在上述元件區域41B上介閘極絕緣膜42B形成 聚石夕閘極電極43B ;又在上述元件區域41A中之上述閘極電 極43八兩側形成η型擴散區域41a及41b,而在上述元件區域 41B中之上述閘極電極43B兩側形成1)型擴散區域41〇及 41d。 再表上述閘極電極43 A兩外側面上形成側壁絕緣膜 84421.doc -19- 1225668 44A,而在上述閘極電極43B兩側壁面上形成側壁絕緣膜 44B ;又在上-述側壁絕緣膜44A外側之上述元件區域41A中 形成n+型擴散區域41e及41f,而在上述側壁絕緣膜44B外 側之上述元件區域41B中形成p+型擴散區域41g及41h。 於本實施例,前述η通道MOS電晶體以閘極長1 nm、閘極 寬15nm形成,而前述p通道MOS電晶體亦以閘極長lnm、閘 極寬1 5nm形成。 於本實施例,上述閘極絕緣膜42A及42B,乃就濕式處理 製成膜厚度為〇.8nm之原矽氧化膜施以前述圖4B說明之電 漿氮化處理而形成。亦即上述閘極絕緣膜42A及42B由氧氮 化膜組成。但於本實施例,上述電漿氮化處理在處理壓 130Pa、Ar氣2000SCCM流量、氮氣150SCCM流量、基板溫 度400°C條件下進行。此時之電力密度設定為1.7W / cm2。 此時如先前說明,電子溫度為0.8eV,處理空間11A中氧之 滯留時間為0.86秒。
圖16A及16B分別表示在形成於圖15元件區域41A之η通 道MOS電晶體及元件區域41Β之ρ通道MOS電晶體之漏洩 電流密度與氧化膜換算膜厚度EOT之關係(參)圖。又圖 中以(實線)代表熱氧化膜之漏洩電流特性,以(□)代 表前述原氧化膜之漏洩電流特性。 參照圖1 6 A及1 6B,可知依據本實施例,可實現氧化膜換 算膜厚度為1.0〜1.2nm之上述閘極絕緣膜42A及42B,同時 此氧化膜換算膜厚度雖然如此小,但與具有相當物理膜厚 度之原氧化膜或熱氧化膜比較時,其漏洩電流密度大幅減 84421.doc -20- 1225668 少 ο 圖17Α及17Β分別表示在形成於圖15元件區域41Α及4 IB 之η通道MOS電晶體及p通道MOS電晶體之導通電流與閘 極絕緣膜氧化膜換算膜厚度之關係。圖中,□代表直接使 用原氧化膜為閘極絕緣膜,•代表使用氮化處理上述初期 氧化膜所得氧氮化膜為上述閘極絕緣膜42 Α及42Β。 參照圖17A及17B,可知於η通道MOS電晶體未見導通電 流減少,而在ρ通道MOS電晶體則導通電流增大。 圖18為如上述所得η通道MOS電晶體及ρ通道MOS電晶 體之移動度之圖。但圖1 8中,□代表使用上述原氧化膜為 閘極絕緣膜42Α及42Β,鲁代表使用上述氧氮化膜。圖19 中,縱座標為互導與氧化膜換算膜厚度之積,與移動度對 應。又橫座標為由施加閘極電壓Vg減臨限值電壓Vth之量。 參照圖1 8,可知在η通道MOS電晶體就算使用電漿氮化 處理形成之氧氮化膜為閘極絕緣膜42 A,其移動度僅約減 少5%。但在ρ通道MOS電晶體,由於使用此種氧氮化膜為 閘極絕緣膜42B,使上述原氧化膜無法測定之移動度大幅 提升。 以上就本發明之較佳實施例加以說明,但本發明不受此 等特定實施例之限制,應可在本發明之要點内做各種改變 或變形。 [產業上利用之可行性] 依據本發明,設定微波電漿電子溫度為2eV以下、較好 leV以下、最好0.9 eV以下,可抑制電漿損害導入氧氮化膜
84421.doc -21 - 1225668 中。又此時設定處理空間中氧之滯留時間為2秒以下、較 好冰以下、最好0.86秒以下,則因氮化氧氮化冑而脫離之 氧原子快速由處理空間去除,而抑制在氧氮化膜正下方因 上述脫離之氧產生氧化膜再成長。再由於5〇〇。〇以下溫度 進行氮化處理,使導入之氮原子在氧化膜與矽基板界面擴 散,抑制發生界面準位等缺陷之問題。 【圖式簡單說明】 圖1為本發明使用之微波電漿處理裝置之構成圖。 圖2A、2B為圖1之微波電漿處理裝置所使用輻射線狀隙 縫天線之構成圖。 圖3為圖1之微波電漿處理裝置中發生之電子溫度分佈 與電子密度分佈圖。 圖4A〜4C為依據本發明第丨實施例之基板處理步驟圖。 圖5為依照本發明之第1實施例,以各種處理壓製得氧氮 化膜<氧化膜換算膜厚度與漏洩電流之關係圖。 圖6為依照本發明之第丨實施例,以各種處理壓製得氧氮 化膜之氧化膜換算膜厚度與扁帶電壓之關係圖。 圖7為依照本發明之第丨實施例,以各種處理壓製得氧氮 化膜中之氮原子之縱深方向分佈圖。 圖8為依照本發明之第丨實施例,以各種處理壓製得氧氮 化膜中之氧原子之縱深方向分饰圖。 圖9為依照本發明之第1實施例,以各種氣體流量條件製 得氧氮化膜之氧化膜換算膜厚度與漏戌電流之關係圖。 圖1〇A、10B表示本發明之機制圖。 84421.doc -22- 1225668 圖11A、11B為依照本發明之第1實施例,以各種處理壓 製得氧氮化膜之外加電壓與漏洩電流之關係圖。 圖12為圖1之基板處理裝置中之離子能量分佈與電子溫 度分佈圖。 圖13為依照本發明之第1實施例形成之氧氮化膜之漏洩 電流與成膜溫度之關係圖。 圖14為依照本發明之第1實施例形成之氧氮化膜中氮原 子之擴散圖。 圖15為依據本發明第2實施例之CMOS元件之構成圖。
圖16A、16B分別表示構成圖15 CMOS元件之η通道MOS 電晶體及Ρ通道MOS電晶體之閘極氧化膜之氧化膜換算膜 厚度與漏洩電流之關係圖.。 圖17Α、17Β分別表示構成圖15 CMOS元件之η通道MOS 電晶體及Ρ通道MOS電晶體之閘極氧化膜之氧化膜換算膜 厚度與沒極(drain)電流之關係圖。 圖18為構成圖15之CMOS元件之η通道MOS電晶體及ρ通 道MOS電晶體移動度之圖。 【圖式代表符號說明】 10 電聚基板處理裝置 11 處理容器 11Α 處理空間 11Β 排氣孔 12 基板保持臺 13 蓋板 84421.doc -23 - 1225668 14 氣體導入路 15 微波天線 W 被處理基板 15 輻射狀線隙缝天線 15A 同軸導波管 15B 天線本體 15a 、 15b 隙縫 15C 放射板 15D 滞相板 21 珍基板 22 矽氧化膜 22A 矽氧氮化膜 23 聚矽電極 40 CMOS元件 41 矽基板 41A、41B 元件區域 41C 元件分隔構造 4 1 a、41 b η型擴散區域 41c 、 41d Ρ型擴散區域 41e 、 41f η+型擴散區域 41g 、 41h Ρ +型擴散區域 42A、42B 閘極絕緣膜 43A、43B 閘極電極 44A、44B 側壁絕緣膜 84421.doc -24-
Claims (1)
- 第092107213號專利申請案 中文申請專利範圍替換本(93年8月) 备、申請專利範園: 種基板處理方法,其係硬基板表面形成之氧化膜為氧 氮化膜者,包含以微波激發電漿以激發氮氣,藉由所形 成之游離基或離子氮化上述氧化膜之氮化處理步驟, 上述氮化處理步騾在未滿5〇(Tc之基板溫度下,上述微 波激發電漿之電子溫度設定為2eV以下,並將上述被處理 基板所保持之處理空間中之氧滞留時間設定為2秒以下 之條件下進行。 2·如申請專利範圍第丨項之基板處理方法,其中上述氮化處 $理步驟在微波激發電漿之電子溫度設定為leV以下進行。 •如申請專利範圍第1項之基板處理方法,其中上述氮化處 理步驟在微波激發電漿之電子溫度設定為〇 9eV以下進 行0 4, 5 如申請專利範圍第i項之基板處理方法,其中上述氮化肩 埋步驟在上述處理空間中之氧滞留時間設定為178料 下進行。 如申請專利範圍第!項之基板處理方法,其中上述氣化肩 理步驟在上述處理空間中之氧滯留時間設定為卬们 進行。 如申請專利範圍第i項之基板處理方法,其中上述氣化肩 埋步驟在上述處理空間中之氧滯留時間設定為〇86秒1 下進行。 如申請專利範圍第1項之基板處理 ™ . 処垤万法,其中上述氮化J v驟在1 〇〇以上之基板溫度進行。 6. 匕如_請專利範圍第1項之基板處理方法,其中上述氮化處 理步驟在基板溫度設定為250〜40(TC範圍進行。 9·如申請專利範圍第1項之基板處理方法,其中上述氮化處 理步驟在約400°C之基板溫度進行。 10·如申請專利範圍第1項之基板處理方法,其中上述處理空 間區分為上述被處理基板與其對向之微波窗口,上述氮 化處理步騾經由上述微波窗口導入微波於上述處理空間 進行,且上述氮化處理步騾以設定上述處理空間中之處 理壓為llOPa以上進行。 11.如申凊專利範圍第1 〇項之基板處理方法,其中上述氮化 處理步驟係設定上述處理壓為約130Pa進行。 12·如申睛專利範圍第1 〇項之基板處理方法,其中上述微波 由連結於上述微波窗口之輻射線狀隙缝天線供應。 13 ·如申清專利範圍第1項之基板處理方法,其中上述微波激 發電漿藉由供給1GHz以上、10GHz以下微波於稀有氣體 與氮氣之混合氣體而形成。 14·如申請專利範圍第13項之基板處理方法,其中上述稀有 氣體係選自由He、Ar、Kr、Ne、Xe組成群。 1 5 ·如申請專利範圍第丨4項之基板處理方法,其中上述稀有 氣體為A r氣。 84421-930806.doc -2 _
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Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI225668B (en) | 2002-05-13 | 2004-12-21 | Tokyo Electron Ltd | Substrate processing method |
AU2003231516A1 (en) * | 2002-05-16 | 2003-12-02 | Tokyo Electron Limited | Method of treating substrate |
JP4485754B2 (ja) * | 2003-04-08 | 2010-06-23 | パナソニック株式会社 | 半導体装置の製造方法 |
TW200511430A (en) * | 2003-05-29 | 2005-03-16 | Tokyo Electron Ltd | Plasma processing apparatus and plasma processing method |
JP4408653B2 (ja) * | 2003-05-30 | 2010-02-03 | 東京エレクトロン株式会社 | 基板処理方法および半導体装置の製造方法 |
KR100956467B1 (ko) * | 2004-03-03 | 2010-05-07 | 도쿄엘렉트론가부시키가이샤 | 플라즈마 처리 방법 |
JP4579637B2 (ja) * | 2004-10-01 | 2010-11-10 | 東京エレクトロン株式会社 | 半導体記憶装置及びその製造方法 |
US20060270066A1 (en) * | 2005-04-25 | 2006-11-30 | Semiconductor Energy Laboratory Co., Ltd. | Organic transistor, manufacturing method of semiconductor device and organic transistor |
JP5386058B2 (ja) * | 2005-04-28 | 2014-01-15 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US7785947B2 (en) * | 2005-04-28 | 2010-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device comprising the step of forming nitride/oxide by high-density plasma |
TWI408734B (zh) | 2005-04-28 | 2013-09-11 | Semiconductor Energy Lab | 半導體裝置及其製造方法 |
JP5052033B2 (ja) * | 2005-04-28 | 2012-10-17 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US7608490B2 (en) | 2005-06-02 | 2009-10-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2007043121A (ja) * | 2005-06-30 | 2007-02-15 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
US7820495B2 (en) * | 2005-06-30 | 2010-10-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
JP5216201B2 (ja) * | 2005-09-27 | 2013-06-19 | 株式会社半導体エネルギー研究所 | 半導体装置、半導体装置の作製方法、液晶表示装置、rfidタグ、発光装置及び電子機器 |
KR100745370B1 (ko) * | 2006-01-20 | 2007-08-02 | 삼성전자주식회사 | 반도체 디바이스의 절연막 제조방법 |
JP5128172B2 (ja) * | 2006-04-28 | 2013-01-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
EP2259294B1 (en) | 2006-04-28 | 2017-10-18 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device and manufacturing method thereof |
JP4864661B2 (ja) * | 2006-11-22 | 2012-02-01 | 東京エレクトロン株式会社 | 太陽電池の製造方法及び太陽電池の製造装置 |
JP5121217B2 (ja) * | 2006-12-05 | 2013-01-16 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
WO2009157479A1 (ja) * | 2008-06-26 | 2009-12-30 | 日本電気株式会社 | スイッチング素子およびスイッチング素子の製造方法 |
US8481433B2 (en) * | 2009-03-31 | 2013-07-09 | Applied Materials, Inc. | Methods and apparatus for forming nitrogen-containing layers |
JP5595481B2 (ja) * | 2009-03-31 | 2014-09-24 | アプライド マテリアルズ インコーポレイテッド | 選択的窒素化の方法 |
US8497196B2 (en) * | 2009-10-04 | 2013-07-30 | Tokyo Electron Limited | Semiconductor device, method for fabricating the same and apparatus for fabricating the same |
WO2011097178A2 (en) * | 2010-02-02 | 2011-08-11 | Applied Materials, Inc. | Methods for nitridation and oxidation |
US9054048B2 (en) | 2011-07-05 | 2015-06-09 | Applied Materials, Inc. | NH3 containing plasma nitridation of a layer on a substrate |
KR101851199B1 (ko) | 2011-12-28 | 2018-04-25 | 삼성전자주식회사 | 질화된 게이트 절연층을 포함하는 반도체 소자 및 그 제조 방법 |
KR102028779B1 (ko) | 2012-02-13 | 2019-10-04 | 어플라이드 머티어리얼스, 인코포레이티드 | 기판의 선택적 산화를 위한 방법 및 장치 |
GB2499816A (en) | 2012-02-29 | 2013-09-04 | Oxford Instr Nanotechnology Tools Ltd | Controlling deposition and etching in a chamber with fine time control of parameters and gas flow |
CN106984815A (zh) * | 2017-04-19 | 2017-07-28 | 宁波合创快速制造技术有限公司 | 一种把3d打印金属件与基板分离的处理方法 |
CN112376024B (zh) * | 2020-10-26 | 2022-08-16 | 北京北方华创微电子装备有限公司 | 一种氧化物薄膜的制备方法 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6136654A (en) * | 1996-06-07 | 2000-10-24 | Texas Instruments Incorporated | Method of forming thin silicon nitride or silicon oxynitride gate dielectrics |
US5993594A (en) * | 1996-09-30 | 1999-11-30 | Lam Research Corporation | Particle controlling method and apparatus for a plasma processing chamber |
US5821168A (en) * | 1997-07-16 | 1998-10-13 | Motorola, Inc. | Process for forming a semiconductor device |
US6087229A (en) * | 1998-03-09 | 2000-07-11 | Lsi Logic Corporation | Composite semiconductor gate dielectrics |
TW419732B (en) * | 1998-07-15 | 2001-01-21 | Texas Instruments Inc | A method for gate-stack formation including a high-k dielectric |
US6197701B1 (en) * | 1998-10-23 | 2001-03-06 | Taiwan Semiconductor Manufacturing Company | Lightly nitridation surface for preparing thin-gate oxides |
US6140187A (en) * | 1998-12-02 | 2000-10-31 | Lucent Technologies Inc. | Process for forming metal oxide semiconductors including an in situ furnace gate stack with varying silicon nitride deposition rate |
EP1265279B1 (en) * | 2000-03-13 | 2009-10-14 | OHMI, Tadahiro | Method of fabricating a flash memory device |
JP3437832B2 (ja) | 2000-03-22 | 2003-08-18 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
US6342437B1 (en) * | 2000-06-01 | 2002-01-29 | Micron Technology, Inc. | Transistor and method of making the same |
JP2002151684A (ja) * | 2000-11-09 | 2002-05-24 | Nec Corp | 半導体装置及びその製造方法 |
JP5068402B2 (ja) * | 2000-12-28 | 2012-11-07 | 公益財団法人国際科学振興財団 | 誘電体膜およびその形成方法、半導体装置、不揮発性半導体メモリ装置、および半導体装置の製造方法 |
KR100837707B1 (ko) | 2001-01-22 | 2008-06-13 | 도쿄엘렉트론가부시키가이샤 | 전자 디바이스 재료의 제조 방법, 플라즈마 처리 방법, 및 산질화막 형성 시스템 |
US6897149B2 (en) | 2001-01-25 | 2005-05-24 | Tokyo Electron Limited | Method of producing electronic device material |
JP2002343792A (ja) * | 2001-05-11 | 2002-11-29 | Applied Materials Inc | 膜形成方法及び装置 |
JP4606737B2 (ja) * | 2001-08-02 | 2011-01-05 | 東京エレクトロン株式会社 | 基材処理方法および電子デバイス用材料 |
JP3746968B2 (ja) * | 2001-08-29 | 2006-02-22 | 東京エレクトロン株式会社 | 絶縁膜の形成方法および形成システム |
JP2003068850A (ja) | 2001-08-29 | 2003-03-07 | Tokyo Electron Ltd | 半導体装置およびその製造方法 |
JP4090225B2 (ja) | 2001-08-29 | 2008-05-28 | 東京エレクトロン株式会社 | 半導体装置の製造方法、及び、基板処理方法 |
US6548422B1 (en) * | 2001-09-27 | 2003-04-15 | Agere Systems, Inc. | Method and structure for oxide/silicon nitride interface substructure improvements |
JP4147017B2 (ja) | 2001-10-19 | 2008-09-10 | 東京エレクトロン株式会社 | マイクロ波プラズマ基板処理装置 |
JP2003142482A (ja) * | 2001-10-31 | 2003-05-16 | Toshiba Corp | 酸窒化膜の製造方法及び半導体装置の製造方法 |
US7517751B2 (en) | 2001-12-18 | 2009-04-14 | Tokyo Electron Limited | Substrate treating method |
AU2002367179A1 (en) | 2001-12-26 | 2003-07-15 | Tokyo Electron Limited | Substrate treating method and production method for semiconductor device |
TWI225668B (en) | 2002-05-13 | 2004-12-21 | Tokyo Electron Ltd | Substrate processing method |
AU2003231516A1 (en) | 2002-05-16 | 2003-12-02 | Tokyo Electron Limited | Method of treating substrate |
JP4694108B2 (ja) | 2003-05-23 | 2011-06-08 | 東京エレクトロン株式会社 | 酸化膜形成方法、酸化膜形成装置および電子デバイス材料 |
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