TW582097B - Power pads for application of high current per bond pad in silicon technology - Google Patents

Power pads for application of high current per bond pad in silicon technology Download PDF

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Publication number
TW582097B
TW582097B TW091114164A TW91114164A TW582097B TW 582097 B TW582097 B TW 582097B TW 091114164 A TW091114164 A TW 091114164A TW 91114164 A TW91114164 A TW 91114164A TW 582097 B TW582097 B TW 582097B
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Taiwan
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layer
wire
area
probe
bonding
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TW091114164A
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Gerald Friese
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Infineon Technologies Corp
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

582097 A7 B7 五、發明説明（1 ) 發明背景 1 .技術範疇 本發明和半導體製造有關，特別是和容許較高電流密度 通過打線墊及促進打線墊有較久可靠度之半導體裝置架構 有關。 2 .相關技術描述 電流流經電阻最小之導電架構。但因電徑之幾何變化及 材料變化，會有較高之電阻及較高之電流密度。這些較高 之電流密度可在不同材料間接面之導電介面間以及導電材 料本身有有害之大量傳送。另外因大量傳送造成之原子混 合，可使導電介面之材料造成介面導電特性劣化。 半導體裝置包含許多導電接面，其中如第一型之金屬可 接於第二型之金屬。可因特定原因選擇設計中之各金屬。 例如實施銅金屬化是因銅導電性高，但銅容易氧化且在氧 氣中很快劣化。而鋁在外表面形成氧化物，卻不會使導電 性大幅劣化。故在許多半導體設計，銅金屬化可包含鋁蓋 以使銅不會氧化。此配置的一個缺點是銅和鋁原子會混合 。當鋁原子進入銅矩陣會使電阻大幅增加。為克服此問題 ，在金屬間沈澱可包含Ta或TaN之擴散障壁，以防止在其 間擴散。此擴散障壁需儘薄以避免流經金屬間之電流電阻 大幅增加。 半導體技術之打線墊電流能力在金屬線利用銅金屬化。 利用打線墊以經由通過如晶片外殼之接腳連接半導體裝置 之金屬線。先前技術之打線墊在用於測試之探針接觸和對 -4 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)
使用相同表面。探針接觸中造成之損害可 成之打線連接。另外打線塾下面之層可能亦 辟害可傳到銘打線塾和下面之銅金屬化間 (擴：障壁’造成上述之原子損害混合。 =1要種*構可提供探針塾進行探針測試，而不損害 &要—種架構可使打線塾在 驅動同許夕之電流，1完全整合於細節距打線墊架 構中。 發明概論 依…本發明於半導體裝置所用之打線墊架構包含金屬層 、由和金屬層相連之介電層形成之互連結，及打線墊具有 在：屬層和互連結上之第一部分及在介電層上之第二部分 。第一部分包括打線用以提供連接用之連結點，及第二部 分包含探針區，用以和探針接觸。 、依…、本發明之半導體裝置所用打線墊另一架構，包含樣 式化以形成至少一金屬線之金屬層，在金屬層上形成並樣 式化以形成對該至少一金屬線之通孔之介電層。形成障壁 層、·二通孔和金屬層接觸，及互連結在通孔形成並經障壁層 和金屬層連接。打線墊包含第一部分在金屬層和互連結上 及第一部分在介電層上。第一部分包含打線區用以提供 銲接線（連結點，及第二部分包含探針區，用以提供和用 於裝置測試之探針接觸。 半導體裝置所用之打線墊另一架構包含樣式化以形成至 少一金屬線之銅層，在銅層上形成並樣式化以形成對至少 -5 - 本紙張尺度適财s ®家科(CNgT4規格(21GX 297公釐) 582097 A7
:金屬線之通孔之介電層、經由通孔和銅層接觸形成之擴 &障壁層’及在通孔中形成並由擴散障壁層和銅層連接之 、.互連〜攻擴散障壁防止銅層和鋁互連結間之原子混合 。打線墊和該互連結整合形纟，並具有第一部分在金屬； 7互連結上，及第二部分在介電層上。第一部分包含打線 ^以提供對銲接線之連結點。第二部分包含探針區，用以 提供和用於裝置測試之探針接觸，使得對該探針區之探針 不會損害擴散障壁層及第一部分。 在替代實施例第一金屬層可包含銅，及打線墊可包含鋁 。障壁層最好放在互連結和金屬、線間防止纟間之^散 裝 。打線塾之厚度可小於約2微米。可在打線墊上形成純化 層以保護打線墊。鈍化層可包含對打線區之第一開孔及對 探針區之第二開孔，鈍化層可包含由打線區和探針區丑用 訂
線 <開孔。打線墊可永久和銲接線連接。障壁層可包本τ TaN。 ’ ^ 本發明這些及其它目的、特性和優點將由以下說明實施 例細述、加上附圖而清楚。 圖式簡沭 由以下較佳實施例描述、參照附圖’將詳細說明本發明 ’顯示依照本發明 ’顯示依照本發明 圖1是沿圖4或5之切線1 - 1之剖面圖 之打線墊探針區； 圖2是沿圖4或5之切線2 - 2之剖面圖 之打線塾打線區； -6 - 顯示依照本發明之打 本發明之打線墊探針 圖3是沿圖5之切線3_3之剖面圖 線墊探針區及打線區； 圖4之說明實施例頂視圖顯示依照 區及打線區； 顯示依照本發明之打線 圖5是另一說明實施例頂視圖 塾探針區及打線區； 圖6之剖面圖顯示依照本發明，探針接觸探針區；及 圖7之剖面圖顯示依照本發明，銲接線和打線區 鼓佳實施你丨細诫 本發明和半導體製造有關，特別是容許較高電流密度通 過打線塾及促進打線^^較久可靠度之半導體裝置架構有 關。本發曰月If低半導體裝置金屬鲜接線連接間距離， 以改良該架構之電流密度能力。另外本發明因提供分開之 探針區或打線區，使探針造成之損害可能降低。 本發明有利地分隔打線區和探針區，在覆蓋下面金屬化 (蓋上放置銲接線。故打線墊電流不再受該蓋之剖面積限 制’及該探針區由如覆蓋厚介電層以防止下面金屬受到任 何4貝害之相同之蓋形成。 現詳細參照圖式，其中相同參考編號表示這些圖式中相 似或相同元件，及圖1顯示半導體裝置1 〇之上部分剖面。 半導體裝置1 0可包含記憶體晶片，如靜態隨機存取記憶體 (SRAM)晶片、動態隨機存取記憶體（Dram)晶片、埋入記 憶體晶片等。半導體裝置1 0可亦包含邏輯或處理器晶片、 特殊功能積體電路（ASIC)晶片或類似者。所示金屬線12用 582097 A7
發明説明 以和線12下之層之通孔及其它金屬線連接（未顯示）。線12 在層階間介電層14上形成。金屬線12最好包含銅、銅合 金或其它高導電材料，如Au、Ag或超導材料。在層14或 金屬線1 2上形成氮化層i 3或其它蝕刻阻擋層，以在形成 如氧化層之介電層1 6 (亦稱為終端通孔層或τ v層）時保護 金屬線1 2。將層1 6樣式化以形成通過其之終端通孔或通 孔17。在通孔17形成障壁層/襯塾18，並可包含Ta、TaN 或其它擴散障壁材料。打線墊2〇由沈澱一層導電材料形成 ’用以保護金屬線1 2及包含於如障壁層！ 8上。此二層最 好一起樣式化。在其它實施例，打線墊2 〇可包含如銅、銅 合金、Au、Ag之導電材料或其它導電材料。打線墊可 包含多層’並最好包含蓋層，以保護下面之材料，尤其是 在使用銅或其合金時。蓋層可包含如Ai。 接著形成鈍化層2 1。鈍化層2 1可包含一或多個介電層 。在所π之實施例，形成氧化層2 2、氮化層2 4及保護層 2 6，並將之樣式化以經由開孔2 8暴露打線墊2 〇。保護層 2 6可包含光敏聚醯亞胺或其它保護層。在一實施例保護層 使用多層。例如保護層26可包含聚醯亞胺25 ,在層26之 其它部分以蝕刻去除後仍存在。亦可使用其它介電層配置 。可變動層數及材料。 好處是用於測試之探針（未顯示），由開孔2 8在探針區3 〇 和打線墊20接觸。導電器徑經打線墊2〇剖面及長延伸到 金屬線1 2。在所示之配置打線塾2 〇對金屬線1 2偏置。因 障壁層1 8很薄，使彳于探針向下之力可損害障壁層1 $，並 -8 - 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公嫠)
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582097 五、發明説明（6 如銅之金屬線12和打線㈣如銘或其它材料之 原子混合°本發明較佳替代地探針（未顯示）由 層16和打線塾2〇接觸’降低對擴散障壁層18之可能損堂。 =探針由孔28插人及由^層16而非金扣和打ς塾 目·打、，泉墊2 0之偏置亦防止在晶圓探針測試中直接 損^屬線。對金屬線之損害可影響金屬線之電流密度^ 可非度’且打線整之損害可導致很難和鲜接線連接或造成 稍後《可靠度問題。依照本發明探針造成之損害已不是問 題，因本發明提供和打線區32 (圖2)分開之偏置區或 區30進行探針接觸。 參照圖2 ’打線整32和探針區3〇 (圖υ分開，並用以細 開孔34和鮮接線連結。好處是打線區32直接在金屬線12 及互連結3 8上，故降低和打線區3 2及金屬線1 2相連之銲 接線（未顯示）間電阻。 參照圖3，再行說明本發明之探針區3 〇及打線區3 2。打 線區32直接在互連結38上，同時探針區3〇在介電層“上 。當探針接觸探針區30，造成之任何損害不會影響打線區 32，因銲接線直接和打線區32連結。打線區^未因探針 而損害，使得和銲接線（未顯示）之連接較佳。另外因此保 持障壁層1 8，而對探針區3 〇所施之力到層丨6。 參照圖4，顯示依照本發明之打線墊2 〇頂視圖。打線墊 20包含如上述為分隔之打線區32及探針區3〇。鈍化層二^ 樣式化以暴露打線區3 2及探針區3 0。所示鈍化層2丨為透 明層，故可看到下面之架構。鈍化層21包含層22、24及 裝 訂 線 -9 582097 A7 _______B7 五、發明説明（7 ) 可能層2 5。將鈍化層2 1樣式化，以在打線區3 2和探針區 3 〇間產生邊線1 9。使用邊線丨9之好處是可防止探針滑到 敏感的打線區3 2。邊線1 9亦可由其它材料形成，如可利 用自打線區或探針區導電材料之提升部分。 互連結3 8直接位於打線區3 2之下，如深灰色區域所示 。另外，金屬線1 2直接位於互連結3 8及打線區3 2之下， 如淺灰色區域所示。探針接觸可在探針區3 〇發生。在一實 施態樣中，位於鈍化層2 1之開孔可包含供打線區3 2之開 孔3 4以及供探針區3 0之第二開孔2 8。另一種情況下，打 線區3 2及探針區3 0亦可能使用同一個開孔（即結合圖五 之開孔2 8及3 4 ) 〇 一個重要的觀點為打線區3 2及打線墊2 〇之測試區或探 針區3 0之分離。依照本發明對〇 25微米或更低之基本規則 设计，功率塾或打線塾可完全整合在細節距打線塾架構中 。功率墊或打線墊20之布局選擇方式為垂直延伸符合傳統 打線墊圖樣。如此依照本發明產生打線墊2 〇所用處理，可 和傳統打線墊所用處理類似^這使本發明較容易和目前處 理程序整合。 參照圖5 ,顯示依照本發明之替代本發明頂視圖。在此 實施例，探針區3 0和打線區3 2連線。這使可用之探針區 較大。利用探針區3 2進;f亍半導體裝置測試，同時利用打線 區3 0連結銲接線和半導體裝置以提供晶片外連接。要知道 探針區及打線區最好和互連結38及金屬線12儘量接近， 以降低探針測試及最終銲接線連接之電阻。 -10 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐） 582097 A7
如圖6所示，探針60說明性地和探针區3〇接觸。如圖7 斤不’銲接線62說明性地顯*由鲜料㈠和打線區32連接。 要知道本發明特別適用於不相容之導電材料或接面。例 如可利用具有紹蓋(如打線整20)之銅金屬線(如金屬線12) 。吓要知道本發明可利用薄鋁蓋或其它金屬。在先前技術 :較厚鋁蓋之使用通常因鋁作用離子蝕刻工具之能力（較 厚層會使RIE工具過熱），而限制為約2微米，但傳統2微 未蓋卻可能無法承受探針而使擴散障壁介面之金屬線（cu) 損害。而依照本發明2微米厚或更薄之蓋層（打線墊）即可 足夠，因打線墊不會受損。本發明之優點是無需大幅變更 處理。 本發明亦提供高電流功率墊。利用降低金屬線和打線墊 間電阻，半導體裝置.可有較高電流。圖4及5之架構只是說 明。本發明亦可使用其它架構。 、，驚人的是，依照本發明可較傳統技術打線墊之電流密度 增加百刀之九百。這一部分和所用之接線架構有關。好處 疋本發月了採用類似於目如打線塾所用，使處理整合簡化 及使附近電路之設計衝擊最小之設計。 在本發明一實施例，打線墊3 2大小可約5 〇乘丨2 〇微米及 探針區3 0可約5 0乘9 0微米。亦可使用其它大小。 在描述於矽技術中高電流打線墊應用之功率墊較佳實施 例後（只做為說明而非限制），要知道精於本技術者由以上 說明可進行改良及變化。故了解可在所附申請專利範圍訂 定之本發明範圍及精神中對本發明特定實施例進行變更。 -11 - ^紙張尺度適用巾®®家料(CNS) A4規格(210X297公爱) 582097 A7 B7 五、發明説明（ 9 ) 在依專利法規定描述本發明細節及特性後 利範圍訂定所申請及要受保護之專利。 圖式元件符號簡單說明 ，由所附申請專 符號 意 義 符號 意義 10 半導體裝置 24 氮化層 1 2 金屬線 25 聚醯亞胺 13 氮化層 26 保護層 14 層階間介電層 28 開孔 .16 介電層 30 探針區 17 通孔 32 打線區 18 障壁層 34 開孔 19 邊線 38 互連結 20, 20， 接合墊 60 探針 21 鈍化層 62 銲接線 22 氧化層 64 銲料 -12 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐)
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Claims (1)

  1. 582097 A8 B8 C8 D8 申請專利範圍 介電層，在金屬層上形成，並樣式化以形成對至 少一金屬線之通孔； 障壁層，由通孔和金屬層接觸形成； 一互連結，於通孔形成，並由障壁層和金屬層連接； ^ 一打線墊，具有第一部分在金屬層和互連結上，及 第二部分在介電層上； 該第一部分包含一打線區，用以提供對打線線之連 結點；以及 孩第二部分包含一探針區，用以提供和用於裝置測 試之探針接觸。 如申請專利範圍第10項之架構，纟中該金屬層包含銅 Ο α如申請專利範圍第10項之架構，其中該打線墊包含铭。 α如申請專利範圍第10項之架構，其中該障壁層包含丁& 或 T aN。 K如申請專利範圍第10項之架構，其中該打線整厚約小 於2微米。 15. 如申請專利範圍第10項之架構，$包含在打線 成之鈍化層。 16. 如申請專利範圍第15項之架構’纟中該純化層包含對 打線區之第一開孔和對探針區之第二開孔。 17. 如申請專利範圍第15項之架構，纟中該鈍化層包含由 打線區和探針區共用之開孔。 18· —種半導體裝置所用打線墊之架構，包本： -2 - 本紙張尺度適財Η Β1家樣準(CNS) Α4規格(210 X 297公嫠） 一 ---------------- 582097 A8 B8 C8
    一銅層，樣式化以形成至少一金屬 八-介電層，在銅層上形成並樣=形成該至少— 至屬線之通孔； 擴玫障壁層，經通孔和鋼層接觸形成； —銘互連結’經通孔形成及由擴散障壁層和銅層連 接二擴散障壁層防止銅層和銘互連結間之原子混合；
    凰：打線墊和互連結整合形成’並具有第-部分在金 屬層和互連結上’及第二部分在介電層上； •該第-部分包含打線墊，用以提供銲接線之連結點 ，以及 、：第二部分包含探針區，用以提供和用於裝置測讀 之探針接觸’使得對探區之探針不會損害擴散障 及第一部分。 19.如申請專利範圍第18項之架構，其中該障壁層包含& 或 TaN。
    20.如申請專利範圍川項之架構，其中該打線I厚約小 於2微米。 2L如申請專利範圍第18項之架構，另包含在打線墊上形 成之鈍化層。 22. 如申請專利範圍第21項之架構，其中該鈍化層包含對 打線區之第一開孔和對探針區之第二開孔。 23. 如申請專利範圍第2 1項之架構，其中該鈍化層包含由 打線區和探針區共用之開孔。 -3 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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WO2003003458A3 (en) 2003-11-20
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DE60202208D1 (de) 2005-01-13
EP1399966B1 (en) 2004-12-08
EP1399966A2 (en) 2004-03-24

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