579663 五、 發明說明 ( 1) 發 明 所 屬 之 技 術 領 域 ： 本 發 明 係 關 於 一 種 製 造 結 線 基 板 之方法 5 尤 指 — 種 製 造 含 有 介 層 孔 導 體 (V i a C0 nd un tor)基板之方法者 〇 先 .Y八 刖 技 術 : 就 傳 統 而 言 含有 介 層 孔 導 體 之 結線基 板 爲 業 界所 知 0 該 種 介 層 孔 導 體 係依 下 述 步 驟 形 成。首 先 製 成 其 內 形 成 有 介 層 孔 (via h ο 1 e)之 ,基 :板， 之 ，後，施 i以 Μ 、> V V :電 ;電 :鍍 (electroless platin g) ，以在。 各介J 罾： FL之壁面上形成一 無電 電 鍍 層 Ο 其 後 將 基 板 沈 浸 於 電 鍍 液中， 接 著 施 以 電 鍍 則 在 各 介 層 孔 之 Μ j\\\ 電 電 鍍 層 上 乃 形成電 鍍 之 導 體 〇 但 在 某 ifeb 狀況 中 > 具 有 預 定 形狀 之介層 孔 導 體 並 不 形 成 在 各 介 層 孔 中 ， 即 使 兀 成 電 鍍 之 後亦然 〇 尤 其 是 ， 在 某 介 層 孔 中 即 使 是 施 行 電 鍍 亦仍無 法 完 全 的 在 壁 面 上 形 成 以 電 鍍 之 導 體 0 特 別 的 是 ，倘擬 予 形 成 之 介 層 孔 導 m Πϋ 非 爲 依 照 所配 合 介 層 孔 之 壁 面形狀 之 杯 形 介 層 孔 導 體 5 而 係 — 種 以 電 鍍 之 導 體 來充 塡介層 孔 所 形 成 之 充 塡 式 介 層 孔 導 體 時 以 電 鍍 所 形 成 之介層 孔 導 體 塡 充 介 層 孔 時 5 通 常 均 難 達 充 滿 之 程 度 〇 上 述 失 敗 之 理 由 可 想 而 知 有 如 下 〇 因 爲 介 層 孔 對 基 板 表 面 而 言 係 成 凹陷， 故 當 基 板 沈 浸 於 電 鍍 液 中 時 5 在 某 jfeb 介 層 孔 中 將 存留有 空 氣 或 某 Itb 介 層 孔 之 壁 面 上 將 附 著 有 氣 泡 0 特 別是， 形 成 充 塡 之 介 層 孔 後 ， 當 電 鍍 之 導 體 在 介 層 孔 中 形成時 各 介 層 孔 之 形 狀 即 改 變 ， 且 依 改 變 之 介 3- 層 孔 形狀， 附 著 於 介 層 孔 579663 五、 發明說明 ( 2) 壁 面 上 之 氣 泡 乃 極 難 去 除 〇 因 該 等 氣 泡 將 阻 止 足 量 之 電 鍍 液 供 應 於 介 層 孔 之 壁 面 5 故 即 難 以 生 成 電 鍍 之 導 m rJS 〇 結 果 在 某 Itb 介 層 孔 之 壁 面 上 乃 Μ J\\\ 法 全 面 的 形 成 電 鍍 之 導 體 〇 發 明 內 容 : 本 發 明 係 鑑 諸 前 述 問 題 5 其 巨 的 乃 係 提 供 —» 種 用 以 製 造 含有 介 層 孔 導 體 之 結 線 基 板 的 改 良 方 法 此 種 方 法 可 確 實 的 形成所希 形狀 之 介 層 孔 導 髀 ， 而 Μ y\\\ 關 於 其 係位在 基 板 中 之 任 何位 置 者 〇 爲 達 成 上 述 巨 的 本 發 明 係 提 供 一 種 製 造 含有 介 層 孔 導 體 基 板 之 製 造 方 法 包 括 之 步 驟 爲 ·· 提 供 一 基 板 y 於 基 板 之 表 面 開 設 有 諸 介 層 孔 9 將 該 基 板倂 同 一 電 極 令 該 基 板 以 垂 直 延 伸 之 方 式 兀 全 的 沈 浸 於 電 鍍 液 中 > 於 基 板 下 方 位 置 產 生 氣 泡 其 方 式 爲 所 產 生 之 氣 泡 係 循 沿 基 板 之 表 面 白 下 丄山 m 至 上 端 上 升 而 其 同 時 可 擊 打 該 表 面 9 及 迫 使 電 流 流 通 於 電 鍍 與 基 板 之 間 乃 使 介 層 孔 導 體 形 成在介 層 孔 之 內 〇 通 常 當 擬 製 造 具 有 介 層 孔 導 體 之 結 線 基 板 時 5 係 先 脩 以 具 有 介 層 孔 之 基 板 接 著 遂 行 電 鍍 俾在 其 上 形 成 介 層 孔 導 體 0 惟 依 本 發 明 J 電 鍍 之 實 現 並 非 僅 經 基 板 在 電 鍍 液 中 之 沈 浸 而 已 更 確 切 而 言 係 將 基 板 之 表 面 成 爲 平 行 於 垂 直 方 向 ， 而 將 基 板 沿 垂 直 之 方 向 伸 入 並 沈 浸 於 電 鍍 液 中 〇 又 者 對 於 氣 泡 之 處 理 方 式 則 爲 氣 泡 係在 基 板 之 下 方 產 生 並 沿 著 基 板 4- 上 升 > 同 時 不 均 勻 的 擊 579663 五、發明說明（3) 打整個基板表面而作電鍍，氣泡乃由下端上升至上端， 繼而上升至基板以上之位置。 當以起泡（bubbling)方式施行電鍍時，氣泡係擊打基 板表面，因之，存留於沈浸基板介層孔中之氣泡，乃隨 著起泡裝置所產生之氣泡而一倂移除。再者，即使是沈 浸後，基板之介層孔附著有氣泡時，所附著之氣泡仍將 倂同所產生之氣泡被移除。結果，每一介層孔之整個壁 面均可全面的供施以電鍍液，則所形成之電鍍的導體乃 可覆蓋各介層孔之整個壁面。因之，依本發明乃確可形 成所希形狀介層孔導體者。 又者，在本發明中，因爲產生之氣泡係由下端往上端連 續的擊打整個基板表面’故在各介層孔中均可形成所希形 狀之介層孔導體，而與係位在基板之何處位置並無關聯。 當形成介層孔導體之後，即可藉習知之方法作結線層 之形成暨其他相關之製程’俾作成完整之結線基板。 氣泡之產生可如下述方式。在基板下方置設以具有大 量孔洞之管子；並將例如空氣等之氣體饋送於該管內， 如是，該管子即可產生氣泡。 當基板Z兩面均已形成介層孔後，起泡（bubbling，亦 即，利用氣泡產生作用）即作用，擊打基板之兩對向表面 ，在此一狀況中，可設置二支適當分開之管子而分別產生 氣泡，其中一支管子所產生之氣泡係用以擊打基板之一面 ’而另一支管子所產生之氣泡則用以擊打基板之另一面。 較佳者爲’依本發明之製造方法係用以製造&介層孔 579663 五、發明說明（4) 導體爲一種充塡之介層孔形式的結線基板者。 在該種狀況中，經由電鍍所形成之介層孔導體非爲-種杯形介層孔導體，而其形狀係配合各相關介層孔之壁 面形狀者，亦即，此種介層孔導體係一種充塡之介層孔 ，其係藉電鍍充塡於介層孔中而形成者，此或有施行電 鍍時經常發生無法形成所希形狀之介層孔導體，亦即， 無法在介層孔中施以足夠程度充塡之顧慮。因各介層孔 係漸次的充塡以電鍍之導體，故各孔之形狀（低降， depression)乃因而變化。因此，依變化之介層孔形狀， 附著於介層孔壁面之氣泡可能難以移除。 但在本發明中，基板係依垂直延伸之方向浸入電渡液 中，且遂行電鍍時，所產生之氣泡係自下而上擊打整個 基板表面（雙面），故即使是介層孔中所形成者爲充塡之 介層孔，亦足以作適當的電鍍，同時，亦可防止在介層 孔中氣泡之連續附著。結果，介層孔中必可充塡以電鍍 之導體而無失敗情事，因之，即可毫無閃失的形成所希 形狀之充塡的介層孔導體。 毋庸贅言的，當介層孔中形成充塡之介層孔時，所使 用之電鍍液與電鍍條件自與形成杯形介層孔導體者不同。 本發明製法使用之基板可包括一下層’及一形成基板 一表面之電鍍阻擋層（plating resist layer) ’並具有使下 層顯露之諸多開孔。上述之該等介層孔可形成在該下層 中並在該電鍍阻擋層之該等開孔內顯露之。 此狀況中，自基板表面（相關電鍍阻擋層之表面）所測 579663 五、發明說明（5) 得各介層孔之深度，在比較未設電鍍阻擋層時係較深， 因此，當基板沈浸於電鍍液內時，介層孔中常存留有空 氣，致造成內部有氣泡之結果。又者，倘基板沈浸後介 層孔中附著有氣泡時，欲將該等氣泡去除將益形困難。 結果，在比較未設有電鍍阻擋層之狀況下，在絕大多數 狀況中，可能無法形成所希形狀之介層孔導體。 至在本發明中，如上述者，基板係以垂直之態勢浸入 鍍液中，並遂行電鍍，同時產生自下而上之上升氣泡且 全面擊打整個基板表面（雙面），因之，即使是因設置了 該電鍍阻擋層而使介層孔之深度增加，亦可施行適當之 電鍍，並可有效的移除介層孔中附著之氣泡，故可形成 所希形狀之介層孔導體而不致失敗。 顯然的’基板係在含帶電鍍阻擋層下完成電鍍，例如， 此狀況中’藉由半附加方法（s e m i _ a d d i t i v e m e t h 〇 d)使結 線層或其他層形成於下層之表面上，特別者，藉由無電 電鍍之達成，則在具有介層孔之下層表面上形成以無電 電鍍層乃可覆蓋住下層之整個表面及介層孔之整個壁面。 結果’具有符合於結線層形狀之開孔形狀之電鍍阻擋層於 是焉形成。本發明係利用在此狀態下之基板作爲基板而施 行電鍍。當基板經歷電鍍時，介層孔導體乃形成，且符合 於結線層或類似層之電鍍導體亦形成。電鍍完成後，將電 鍍阻擋層去除，之後，進行蝕刻以去除薄的無電電鍍層， 如是’即可形成所希圖型（pattern)之結線層或類似層。 實施方式： 579663 五、發明說明（6) 本發明之一可行實施例，將佐以附圖說明如後。 第1圖爲擬依本發明實施例方法所製造之結線基板 1的部分放大剖面圖。結線基板1假設爲矩形板形狀 (4 0 0 mm X 40 Omm)並具有一主面3及一反面5。結線基板 1包括一板形芯基板（絕緣樹脂層）7(厚度：約800 // m)， 對應厚度方向而言，其係設在中央處。亦形成有一絕緣 樹脂層9(厚度：約35 // m)，例如，可在絕緣層7之任 何一側上層設以環氧樹脂而成。又者，尙形成有一焊材 阻擋層（絕緣樹脂層）1 1 (厚度··約25 // m)，例如，可在 各絕緣樹脂層9上層設以環氧樹脂而成。 芯基板7之預定位置上開設有多數通孔1 3 (直徑：約 350// m)。各通孔13之壁面上，形成有實質上成圓柱形通 孔導體15(厚度：約25// m)。通孔導體15內部塞有一實 質上成極形之樹脂插塞1 7。此外，絕緣樹脂層9之預定 位置上形成有多數之介層孔1 9，每一介層孔之開孔直徑約 爲85 // m，所有介層孔1 9均整個貫穿絕緣樹脂基板9。再 者，各焊材阻擋層1 1之預定位置上形成有多數之墊形開孔 (pad opening)，該等開孔23係整個貫穿焊材阻擋層1 1。 在芯層7與各絕緣樹脂層9形成有一第1結線層25 (厚度：約25 v m)。第1結線層25係與通孔1 5暨相關 之充塡的介層孔2 1相連接。並且，在各絕緣樹脂層9 與相關之焊材阻擋層1 1間形成有一第2結線層27。第 2結線層27係與相關之充塡的介層孔2 1相接連。又者 ，第2結線層27 —部分之墊件（pad)27p係在焊材阻擋 ··579663 V. Description of the invention (1) The technical field to which the invention belongs: The present invention relates to a method for manufacturing a junction substrate 5 especially-a method for manufacturing a substrate containing a via hole conductor (Via C0 nd un tor). Y-Hachi technology: Conventionally, a junction substrate with a via hole conductor is known in the industry. This type of via hole conduction system is formed according to the following steps. First, a substrate having a via hole (via h ο 1 e) formed therein, a substrate: a plate, and a substrate are formed. Then, M is applied, and V V: electricity; electroless: electroplating (electroless platin g). Each interface J J: An electroless plated layer is formed on the wall surface of the FL 0, and then the substrate is immersed in the plating solution, and then electroplating is performed to form a plated conductor on the M \\ electroplated layer of each interface hole. However, in a certain ifeb condition > a via hole conductor having a predetermined shape is not formed in each via hole, even after plating is formed. In particular, even in a certain via hole, it is still impossible to perform plating The electroplated conductor is completely formed on the wall surface 0. In particular, if the via hole guide m Πϋ to be formed is not a cup-shaped via hole conductor 5 according to the shape of the wall surface of the mating via hole—kind of Filled vias formed by electroplated conductors to fill interstitial vias are usually filled with interstitial vias formed by electroplating and filled with interstitial pores.5 It is usually difficult to reach the full level. The reason for the above failure can be thought of. And know the following 〇Because the interstitial holes are recessed on the substrate surface, when the substrate is immersed in the plating solution 5 air will remain in a jfeb interstitial hole or bubbles will adhere to the wall surface of an Itb interstitial hole 0 Special Yes, after the filled via hole is formed, the shape of each via hole is changed when the plated conductor is formed in the via hole, and it is attached to the via hole according to the changed 3-layer hole shape. Description of the invention (2) The air bubbles on the wall surface are extremely difficult to remove. 0 These bubbles will prevent a sufficient amount of plating solution from being supplied to the wall surface of the interlayer hole. Therefore, it is difficult to generate the electroplating guide m rJS. The surface of the wall is a comprehensive method for forming electroplated conductors by the M J \\ method. Summary of the Invention: The present invention is based on the foregoing problems. Improved method for the junction substrate of the hole conductor This method can reliably form the interposer hole guide of a desired shape, and M y \\\ is about any position of the substrate in order to achieve the above-mentioned giant invention It provides a manufacturing method for manufacturing a conductor substrate including vias. The steps include: providing a substrate y with interlayer holes provided on the surface of the substrate 9 and using the same electrode to make the substrate extend vertically. Immersed in the plating solution > Bubbles are generated below the substrate in a way that the generated bubbles follow the surface of the substrate and rise from the bottom to the top, while at the same time they can hit the surface 9 and force current to flow through the plating Between the substrate and the substrate, the via hole conductor is formed within the via hole. Generally, it is intended to manufacture a junction base with the via hole conductor. Time 5 is to first repair a substrate with interposer holes and then perform electroplating to form interposer conductors thereon. However, the realization of the J plating according to the present invention is not just the immersion of the substrate in the plating solution. The surface of the substrate becomes parallel to the vertical direction, and the substrate is extended into the vertical direction and immersed in the plating solution. Or, the processing method of the bubbles is that the bubbles are generated below the substrate and rise along the substrate 4-> At the same time, non-uniform impact 5976663 5. Description of the invention (3) The entire substrate surface is plated for electroplating. The bubbles rise from the lower end to the upper end, and then rise to a position above the substrate. When plating is performed in a bubbling manner, the bubbles hit the surface of the substrate. Therefore, the bubbles remaining in the pores of the immersion substrate interlayer are removed at once along with the bubbles generated by the bubbling device. Moreover, even after the immersion, when bubbles are attached to the interlayer holes of the substrate, the attached bubbles will still be removed from the generated bubbles. As a result, the entire wall surface of each via hole can be fully supplied with a plating solution, and the formed plated conductor can cover the entire wall surface of each via hole. Therefore, according to the present invention, it is possible to form a desired-shaped via hole conductor. Furthermore, in the present invention, since the generated bubbles continuously hit the entire substrate surface from the lower end to the upper end, a via hole conductor of a desired shape can be formed in each via hole, and is located on the substrate. Where is not relevant. After the via hole conductor is formed, a conventional method can be used to form the wiring layer and other related processes', to form a complete wiring substrate. The generation of air bubbles can be as follows. A tube with a large number of holes is placed under the substrate; a gas such as air is fed into the tube. If so, the tube can generate air bubbles. When interlayer holes have been formed on both sides of the substrate Z, bubbling (that is, the use of air bubbles to produce an effect) is used to hit the two opposing surfaces of the substrate. In this case, two branches can be set appropriately apart. Bubbles are generated by the tubes, one of which is used to hit one side of the substrate, and the other is used to hit the other side of the substrate. The preferred one is the method according to the present invention for manufacturing & interlayer holes 579663 V. Description of the invention (4) The conductor is a junction substrate in the form of a filled via hole. In this case, the via hole conductor formed by electroplating is not a cup-shaped via hole conductor, and its shape is matched with the shape of the wall surface of each relevant via hole, that is, such via hole guide The system is filled with interstitial pores, which are formed by filling the interstitial pores with electroplating. When plating is performed, it often happens that the interstitial pore conductors of the desired shape cannot be formed. Sufficient concerns were placed in the hole. Because each interstitial hole is gradually filled with electroplated conductor, the shape of each hole (low depression, depression) changes accordingly. Therefore, depending on the shape of the via hole, the bubbles attached to the via wall surface may be difficult to remove. However, in the present invention, the substrate is immersed in the electro-hydraulic liquid in the direction of vertical extension, and when the electroplating is performed, the generated bubbles hit the entire substrate surface (double-sided) from the bottom up, so even the vias The formed interstitial holes are sufficient for proper electroplating. At the same time, continuous adhesion of bubbles in the interstitial holes can be prevented. As a result, the interposer holes can be filled with electroplated conductors without failure, so that the filled interposer conductors of the desired shape can be formed without flicker. Needless to say, when a filled via hole is formed in the via hole, the plating solution and plating conditions used are different from those forming the cup-shaped via hole conductor. The substrate used in the manufacturing method of the present invention may include a lower layer 'and a plating resist layer which forms a substrate and a surface, and has a plurality of openings for exposing the lower layer. The aforementioned interlayer holes may be formed in the lower layer and exposed in the openings of the plating barrier layer. In this case, measured from the surface of the substrate (the surface of the relevant plating barrier layer) 579663 5. Description of the invention (5) The depth of each via hole is deeper when no plating barrier layer is provided. Therefore, when the substrate is immersed When in the plating solution, air often remains in the interlayer holes, resulting in air bubbles inside. Furthermore, if bubbles are attached to the interstitial holes after the substrate is immersed, it will be difficult to remove these bubbles. As a result, in the case where the plating barrier layer is relatively not provided, in most cases, a via hole conductor having a desired shape may not be formed. To the present invention, as described above, the substrate is immersed in the plating solution in a vertical state and then electroplated, while generating bottom-up rising bubbles and hitting the entire substrate surface (double-sided), so even if The depth of the via hole is increased due to the provision of the plating barrier layer. Appropriate electroplating can also be performed, and the bubbles attached to the via hole can be effectively removed. Therefore, a via hole conductor of a desired shape can be formed. Don't fail. Obviously, the substrate is electroplated under a barrier layer with a plating layer, for example, in this case, a junction layer or other layer is formed on the surface of the lower layer by a semi-additive method (semi_additivemethod), in particular, by Achieved by electroless plating, an electroless plating layer is formed on the surface of the lower layer having the via hole, which can cover the entire surface of the lower layer and the entire wall surface of the via hole. As a result, a plated barrier layer having an opening shape conforming to the shape of the wiring layer is then formed. In the present invention, plating is performed using a substrate in this state as a substrate. When the substrate is subjected to electroplating, a via via conductor is formed, and a plated conductor conforming to a junction layer or the like is also formed. After the electroplating is completed, the electroplating barrier layer is removed, and then, etching is performed to remove the thin electroless electroplated layer. If it is', a junction pattern layer or the like of a desired pattern can be formed. Embodiments: 579663 5. Description of the invention (6) One of the feasible embodiments of the present invention will be described with the accompanying drawings as follows. FIG. 1 is a partially enlarged cross-sectional view of a wire-bonding substrate 1 to be manufactured according to a method of an embodiment of the present invention. The junction substrate 1 is assumed to have a rectangular plate shape (400 mm X 40 Omm) and has a main surface 3 and a reverse surface 5. The wiring substrate 1 includes a plate-shaped core substrate (insulating resin layer) 7 (thickness: about 800 // m), which is located at the center corresponding to the thickness direction. An insulating resin layer 9 (thickness: about 35 // m) is also formed. For example, an insulating resin layer 9 may be provided on one side of the insulating layer 7 with epoxy resin. In addition, 尙 is formed with a solder material barrier layer (insulating resin layer) 1 1 (thickness ·· about 25 // m). For example, an epoxy resin may be provided on each of the insulating resin layers 9. The core substrate 7 is provided with a plurality of through holes 1 3 (diameter: about 350 // m) at predetermined positions. On the wall surface of each through hole 13, a substantially cylindrical through hole conductor 15 (thickness: about 25 // m) is formed. Inside the through-hole conductor 15 is a substantially polar resin plug 17. In addition, a large number of via holes 19 are formed at predetermined positions of the insulating resin layer 9, and the diameter of each via hole is about 85 // m. All the via holes 19 penetrate the insulating resin substrate 9 as a whole. In addition, a plurality of pad-shaped pad openings are formed at predetermined positions of each of the welding material barrier layers 11, and the openings 23 are formed through the welding material barrier layer 11 as a whole. A first junction layer 25 (thickness: about 25 v m) is formed on the core layer 7 and each of the insulating resin layers 9. The first junction layer 25 is connected to the through hole 15 and the related via hole 21. In addition, a second junction layer 27 is formed between each insulating resin layer 9 and the related solder material barrier layer 11. The second junction layer 27 is connected to the related via hole 21. In addition, the second junction layer 27-part of the pad 27p is blocked by the welding material.
579663 五、發明說明（7) 層1 1之墊形開孔23中顯露。爲了防止墊件27p之氧化’ 乃在墊件27p上依序的形成以一鍍鎳層及一鍍金層（未示）。 具有上述構造之結線基板1的製造如下。 第一，準備一雙側以銅護面之基板作爲芯基板7，並 於芯基板7之預定位置上形成以多數通孔1 3 (見第2圖）。 接著，使芯基板7施以無電之銅電鍍，之後，作銅電 鍍，因而乃在芯基板7之對向側面上均形成電鍍層，該 電鍍層可實質的覆蓋各側面上銅膜之整個表面，並在各 通孔13之壁面上形成以實質上成圓柱形之通孔導體15。 其後，在各通孔導體1 5中形成以樹脂插塞1 7。特別 的，使用一具有諸孔洞之預設型式的掩罩，該等孔洞在 位置暨直徑上均係配合通孔導體1 5者，則樹脂膏乃可 經由印刷（PrintinS)而洩入通孔導體1 5內部。之後，樹 脂膏經加熱固化而形成爲樹脂插塞1 7。各樹脂插塞1 7 之對向端部均予拋光俾可和芯基板7之對應的表面齊平。 形成樹脂插塞1 7後，即將由銅膜與銅鍍層所組成之 銅層予以圖型化，以在芯層7之任一側上形成第1結線 層2 5。特別的，在銅層上形成以一半硬之蝕刻保護層， 其係經由一其預設圖型係符合於第1結線層2 5之掩罩 (mask)而予曝光，之後乃顯像。其後，藉加熱使蝕刻保 護層硬化，即得具有預設圖型之硬化蝕刻保護層。接著 ，自保護層顯露之銅層部分，以飩刻將之去除。完成整 個蝕刻後，將蝕刻保護層移除。 其次，將具有介層孔19(開口直徑：約85 // m)之絕緣 579663 五、發明說明（8) 樹脂層9形成於第1結線層25與芯基板7上。特別的， 第1結線層2 5與芯基板7上係形成有半硬之絕緣樹脂層 ，並經由一其預設圖型係符合於介層孔1 9之掩罩而予 曝光，之後乃顯像。接著，將該絕緣樹脂層9加熱令其 硬化，因之，在預設位置上具有介層孔1 9之絕緣樹脂 層9即形成。顯然的，藉電射機亦可形成介層孔1 9。 其次，遂行無電銅電鍍，即作成加第2圖中之粗線所 示，一種厚度約爲〇 · 7 // m，形成在第1樹脂介電層9上 及在介層孔1 9之壁面上的無電銅鍍層31。 之後，在各無電銅鍍層3 1上，形成以具有多數孔洞 3 5之預設圖型的電鍍阻擋層3 3。特別者，各無電銅鍍 層3 1上係形成有一半硬化之電鍍阻擋層，其係經由一 其預設圖型係符合於第2結線層27之掩罩而予曝光， 之後乃顯像。接著，藉加熱使其硬化，即形成爲一種在 預設位置上具有開孔35之電鍍阻擋層3 3。顯然的，開 孔3 5可作成爲符合第2結線層27與介層孔1 9之各種 不同形狀。 因之，乃獲得如第2圖所示之基板5 1。 其次，在銅電鍍步驟中，將基板5 1施以銅電鍍。 首先，以第3圖說明銅電鍍步驟中所使用之電鍍裝置 1 0 1。電鍍裝置1 〇 1設有一未例示之移動單元，用以將 基板5 1持住並將其移動。移動單元包括一持住基板5 1 之齒條及將該齒條依水平及垂直方向移動之移動機構。 尙且，電鍍裝置1 〇 1亦包括一銅鍍槽1 03，用以在基 -10- 579663 五、發明說明（9) 板5 1上形成銅電鍍導體。銅電鍍槽1 〇 3內儲存有銅電 鍍液1 〇 5 ’用以形成充塡之介層孔2 1。又者，銅電鍍槽 103之底面l〇3t附近，置設有二支管子107，各管子 107之長度約爲800 mm，並開設有大量的孔洞而可產生 氣泡109。二根管子1〇7互相以約60 mm之距離Η依平 行於銅電鍍槽1 〇 3底面1 0 3 t之方向作配置。故而，在 管子107內饋送空氣時，即由管子107之孔洞產生大量 的氣泡1 09，此等氣泡並朝上移動迨至銅電鍍液1 05之 頂面。 其次，說明銅電鍍步驟。 首先，以移動單元將置設於齒條上之基板5 1水平的 移動於銅電鍍槽1 03以上之位置。接著，使齒條朝下移 動，俾令基板5 1浸入銅電鍍槽1 03所貯之銅電鍍液1 〇5 中。此際，基板5 1係成垂直位置之沈浸，或其態勢爲 ，基板51之兩對向面53係成水平之面向者。進而，將 一銅製之電極1 1 0以垂直方向伸入銅電鍍液1 0 5中。基 板51(尤爲一種基板51之無電銅電鍍層31)與電極1 1〇 間則連接以電源PS，且將該電源PS通電，令基板51 與電極1 1 0間流通以電流。在沈浸已逾一預設之期間後 ，如第4圖所示，在基板5 1之各對向表面5 3上即形成 銅電鍍之導體。因之，基板53上即形成充塡介層孔2 1 與第2結線層2 7。 在銅電鍍過程中，並非僅係單純的將基板5 1浸入銅 電鍍液1 〇 5中遂行銅電鍍而已，此外，置設於基板5 1579663 V. Description of the invention (7) The pad-shaped opening 23 of the layer 11 is exposed. In order to prevent oxidation of the pad member 27p, a nickel-plated layer and a gold-plated layer (not shown) are sequentially formed on the pad member 27p. The junction substrate 1 having the above-mentioned structure is manufactured as follows. First, a copper substrate with a copper shield on both sides is prepared as the core substrate 7, and a plurality of through holes 1 3 are formed at predetermined positions of the core substrate 7 (see FIG. 2). Next, the core substrate 7 is subjected to electroless copper plating, and then copper plating is performed. Therefore, a plating layer is formed on the opposite sides of the core substrate 7, and the plating layer can substantially cover the entire surface of the copper film on each side. A through-hole conductor 15 having a substantially cylindrical shape is formed on the wall surface of each through-hole 13. Thereafter, a resin plug 17 is formed in each of the via-hole conductors 15. In particular, a preset type mask with holes is used, and the holes are matched with the through-hole conductor 15 in position and diameter, and the resin paste can be leaked into the through-hole conductor through printing (PrintinS). 1 5 inside. Thereafter, the resin paste is cured by heating to form a resin plug 17. The opposite ends of each of the resin plugs 17 are polished so as to be flush with the corresponding surface of the core substrate 7. After the resin plug 17 is formed, a copper layer composed of a copper film and a copper plating layer is patterned to form a first junction layer 25 on either side of the core layer 7. Specifically, a half-hard etching protection layer is formed on the copper layer, which is exposed through a mask whose preset pattern conforms to the first junction layer 25, and then is developed. Thereafter, the etching protection layer is hardened by heating to obtain a hardened etching protection layer having a predetermined pattern. Then, the copper layer exposed from the protective layer is removed by engraving. After the entire etch is completed, the etch protection layer is removed. Next, an insulation 579663 having a via 19 (opening diameter: about 85 // m) is used. 5. Description of the Invention (8) A resin layer 9 is formed on the first junction layer 25 and the core substrate 7. In particular, a semi-rigid insulating resin layer is formed on the first junction layer 25 and the core substrate 7, and is exposed through a mask whose preset pattern conforms to the interlayer hole 19, and is subsequently displayed. image. Next, the insulating resin layer 9 is heated to harden it, so that an insulating resin layer 9 having a via hole 19 at a predetermined position is formed. Obviously, the interlayer holes 19 can also be formed by using an electron beam transmitter. Secondly, electroless copper electroplating is performed, that is, as shown by the thick line in the second figure, a thickness of about 0.7 · m is formed on the first resin dielectric layer 9 and the wall surface of the dielectric hole 19上 的 电 电 铜 层 31。 On the electroless copper plating 31. After that, on each of the electroless copper plating layers 31, a plating barrier layer 3 with a predetermined pattern having a plurality of holes 35 is formed. In particular, a semi-hardened plating barrier layer is formed on each of the electroless copper plating layers 31, which is exposed through a mask whose preset pattern conforms to the second junction layer 27, and is then developed. Next, it is hardened by heating to form a plated barrier layer 3 3 having openings 35 at predetermined positions. Obviously, the openings 35 can be made into various shapes conforming to the second junction layer 27 and the vias 19. Therefore, a substrate 51 as shown in FIG. 2 is obtained. Next, in the copper plating step, the substrate 51 is subjected to copper plating. First, a plating apparatus 1 0 1 used in a copper plating step will be described with reference to FIG. 3. The plating apparatus 101 is provided with a non-illustrated moving unit for holding and moving the substrate 51. The moving unit includes a rack holding the substrate 5 1 and a moving mechanism for moving the rack horizontally and vertically. In addition, the electroplating device 101 also includes a copper plating tank 103 for forming a copper electroplated conductor on the base plate 5-10. The copper electroplating bath 103 stores a copper electroplating bath 105 for forming a filled via hole 21. In addition, near the bottom surface 103t of the copper plating tank 103, two tubes 107 are arranged, each tube 107 is about 800 mm in length, and a large number of holes are opened to generate bubbles 109. The two pipes 107 are arranged at a distance of about 60 mm from each other in a direction parallel to the bottom surface of the copper plating bath 103 and the distance of 103 tons. Therefore, when air is fed into the tube 107, a large number of bubbles 1 09 are generated from the holes of the tube 107, and these bubbles move upward to the top surface of the copper plating solution 105. Next, a copper plating process is demonstrated. First, the substrate 51 placed on the rack is horizontally moved to a position above the copper plating bath 103 by a moving unit. Next, the rack is moved downward, and the substrate 51 is immersed in the copper plating solution 105 stored in the copper plating bath 103. At this time, the substrate 51 is immersed in a vertical position, or its situation is, and the two facing surfaces 53 of the substrate 51 are horizontal facing persons. Further, a copper electrode 110 was vertically inserted into the copper plating solution 105. A power supply PS is connected between the substrate 51 (especially an electroless copper plating layer 31 of the substrate 51) and the electrode 110, and the power supply PS is energized, so that a current flows between the substrate 51 and the electrode 110. After the immersion has passed for a preset period of time, as shown in FIG. 4, copper-plated conductors are formed on the respective opposing surfaces 53 of the substrate 51. Therefore, the filling via hole 2 1 and the second junction layer 27 are formed on the substrate 53. In the copper electroplating process, it is not simply to immerse the substrate 5 1 in the copper plating solution 105 to perform copper electroplating. In addition, it is placed on the substrate 5 1
-11- 579663 五、發明說明（1〇) 下方之管子107內因饋入有空氣，故產生了大量之氣泡 1〇9(見第3圖），故特別的，饋入管子107內之空氣流量 爲4 0〜6 0 Ι/min，亦即每支管子107饋入之空氣流量爲 2 0〜3 0 Ι/min時，即可產生大量之氣泡109。 氣泡109係自基板51之下端部53d沿著基板表面53 上升至上端部53u，同時，並擊打基板51之兩面53B，53C ，氣泡繼而上升至基板51之上方的位置。易言之，在 遂行銅電鍍之同時並產生有氣泡，該等氣泡則係以均勻 之汸式擊打基板51之表面53而與其位在何處不生關聯 ，且氣泡1 09最後係上升至基板5 1以上之位置，故不 致駐留於上端部53u上。 顯然的，介層孔1 9係形成在各基板對向之兩面5 3上 ，故上升之氣泡係同時擊打該對向之兩面53。因二支管 子1 07係以間距Η設在銅電鍍槽1 03中，故一支管子 10 7Β所產生之氣泡，可擊打基板之一面53Β，而另一支 管子107C所產生之氣泡，則可擊打基板之另一面53 C 。由於管子107之長度（約800 mm)係作成約爲基板側面 長度（400 mm)之2倍，故擊打基板各面53之氣泡量約爲二 支管子所產生氣泡量（20〜30 1/m in)之·一半（10〜15 1/m in)。 倂同有起泡作用施行銅電鍍時，浸泡基板5 1之介層 孔1 9間殘留的氣泡，將隨另產生之氣泡1 09 —倂被移 除。又者，即或是基板5 1沈浸後在介層孔1 9中仍附著 有氣泡時，其亦將隨另產生之氣泡1 09 —倂被帶除。結 果，各介層孔19之整個表面上均可供應以銅電鍍液105 -12- 579663 五、發明說明（11 ) ，所形成之銅電鍍導體乃可含蓋各介層孔19之全部壁 面。因此，即可毫無閃失的形成所希形狀之充塡的介層 孑L 21(filled vias) 〇 再者，因爲氣泡1 Ο 9係自基板下端5 3 d沿著基板往上 端部5 3 u持續的擊打基板雙表面5 3，故在介層孔1 9中 乃可形成所希形狀之充塡的介層孔2 1，因而與其究係位 於基板何處並無關聯。 在本實施例中，介層孔係經銅電鍍所形成之充塡的介 層孔2 1，每一介層孔係形成爲在對應之介層孔1 9中施 以充塡之銅電鍍導體者。以習用者而言，各介層孔19 中通常均難以全面的充塡而成爲銅電鍍導體者。因通孔19 係漸次的充塡以銅電鍍導體，故孔之形狀（低降，deprrssion) 自亦改變。因之，依改變之介層孔形狀，附著於介層孔1 9 壁面之氣泡或將難以去除。 但在本實施例中，基板5 1係依垂直方向伸入沈浸於 鍍液105中，且在施銅電鍍之同時，係另產生氣泡109 沿著基板之整個雙面53上升並對該雙面擊打，故即使 介層孔1 9中形成有充塡的介層孔2 1，亦可適切的遂行 銅電鍍，此外，並可防止氣泡1 09持續的附著在介層孔 1 9上。結果，即可在無任何閃失下將銅電鍍導體充滿整 個介層孔1 9，因而即可形成所希形狀之充塡的介層孔2 1。 本實施例中，擬作銅電鍍之基板5 1包括形成基板雙 面53之絕緣樹脂層（下層）9及電鍍阻擋層33，並具有開 孔3 5，供絕緣樹脂層9之顯露。介層孔1 9中，擬形成 -13- 579663 五、發明說明（12) 之充塡的介層孔2 1係形成在絕緣樹脂層9中，並在電 鍍阻擋層3 3之開孔3 5中顯露。因此，由相對應基板表 面53(對應之電鍍阻擋層33的表面）所量得之各介層孔 1 9深度，在比較未設電鍍阻擋層3 3之狀況下係較深， 故當基板5 1沈浸於銅電鍍液1 05內時，介層孔1 9內極 常存留有空氣，致最終之形成品內即含有氣泡。又者， 當基板5 1沈浸後介層孔1 9上附著有氣泡時，欲將該等 氣泡去除將益形困難。結果，如未設以電鍍阻擋層3 3， 則在絕大部分狀況下，均難以形成所希形狀之充塡的介 層孔21。 但是，依本實施例，如上述者，基板5 1係依垂直之 態勢沈浸於電鍍液1 05中，並遂行銅電鍍，同時，另產 生氣泡1 09，其方式大量氣泡沿著整個基板雙面5 3上升 並予擊打，如是，即使是因設置了該電鍍阻擋層3 3使 介層孔1 9之深度增加，仍可適當的遂行銅電鑛，同時 ，並可防止氣泡1 09連續的附著在介層孔1 9上。結果 ，在無閃失下即可形成所希形狀之充塡的介層孔2 1。 當完成銅電鍍後（充塡的介層孔2 1已形成後）經過一段 預設之時間時，藉由移動機構，齒條乃自銅鑛液1 03中 朝上拉動且之後水平的移動至次一階段。 如此，即完成了銅電鍍之步驟。 其次，將電鍍阻擋層3 3由基板51處移除，俾令業被 電鍍阻擋層3 3所覆蓋之無電銅電鍍層3 1顯露。 之後，施行所謂的快速蝕刻，以移除顯露之無電銅電 -14- 579663 五、發明說明（13) 鍍層3 1。 其次，在絕緣樹脂層9與第2結線層27上形成以具 有墊形開孔23之焊材阻擋層1 1。特別者，係在各絕緣 層9與相對應之第2結線層27上形成以半硬化之焊材 阻擋層9，並經其預設圖型係符合於墊形開孔23之掩罩 予以曝光，之後顯像。其後，藉加熱使其硬化，乃形成 預設圖型之焊材阻擋層1 1。 之後，在自焊材阻擋層Π所顯露之墊狀物27p上， 依序的形成以鎳鍍層及金鍍層。 因之，即作成如第1圖所示之結線基板1。 本發明之實施例業如前述，惟本發明並非僅如上陳， 在本發明之思想及主要精神下，自有多種之技術性變更。 綜結而言，本發明之製法係用以製造多層樹脂結線基 板1，其中，該種基板係由多數之絕緣樹脂層7,9及1 1 與多數之結線層25及27等相互疊合而成，但是，本發 明亦可用以製造其他型式之結線基板，包括陶瓷結線基 板等，只要是藉電鍍使介層孔導體形成於其之介層孔中 者均可。尙且，該芯基板亦可爲一種其內具有結線層之 多層芯基板。 上述之實施例中，介層孔導體2 1係設爲充塡之介層 孔的形式者，但介層孔導體2 1亦可設爲一種適形之介 層孔，其中，介層孔1 9中並未全部充塡以電鍍材料者。 再者，在上述實施例中，介層孔導體（充塡的介層孔） 係經銅電鍍形成，但本發明可應用於介層孔導體（充塡-11- 579663 V. Description of the invention (10) A large amount of air bubbles 10 (see Fig. 3) was generated because air was fed into the tube 107 below, so in particular, the air flow fed into the tube 107 When it is 40 ~ 60 0 I / min, that is, when the air flow rate of each tube 107 is 20 ~ 30 0 I / min, a large number of air bubbles 109 can be generated. The bubble 109 rises from the lower end portion 53d of the substrate 51 along the substrate surface 53 to the upper end portion 53u, and at the same time, hits both sides 53B, 53C of the substrate 51, and the bubble rises to a position above the substrate 51. In other words, air bubbles are generated at the same time as the copper plating is performed. These air bubbles hit the surface 53 of the substrate 51 in a uniform manner and are not related to where they are located. Finally, the bubbles 1 09 rise to The substrate 51 does not reside on the upper end portion 53u because it is at a position above 51. Obviously, the interstitial holes 19 are formed on the opposite sides 53 of the substrates, so the rising bubbles hit the opposite sides 53 of the opposite sides at the same time. Because the two tubes 1 07 are arranged in the copper plating tank 103 with a distance, the bubbles generated by one tube 10 7B can hit one side of the substrate 53B, and the bubbles generated by the other tube 107C, Can hit the other side of the substrate 53 C. Since the length of the tube 107 (about 800 mm) is approximately twice the length of the side surface of the substrate (400 mm), the amount of bubbles hitting each side of the substrate 53 is about the amount of bubbles generated by two tubes (20 ~ 30 1 / m in) · half (10 ~ 15 1 / m in).倂 When copper plating is performed with the blistering effect, the remaining air bubbles between the interlayer holes 19 of the immersion substrate 51 will be removed along with the other air bubbles 1 09 — 倂. In addition, even if bubbles are still attached to the interstitial holes 19 after the substrate 51 is immersed, they will be removed along with the other bubbles 1 09- 倂. As a result, a copper plating solution 105 -12-579663 can be supplied on the entire surface of each interposer hole 19. V. Description of the Invention (11) The copper electroplated conductor formed can cover the entire wall surface of each interposer hole 19. Therefore, it is possible to form a filled filled interposer of a desired shape without flicker. L 21 (filled vias) 〇 Furthermore, since the bubbles 1 0 9 are from the lower end 5 3 d of the substrate to the upper end 5 3 u Continuously hitting both surfaces of the substrate 5 3, so the filled vias 21 of the desired shape can be formed in the vias 19, so it has nothing to do with where the substrate is located. In this embodiment, the via holes are filled via holes 21 formed by copper electroplating, and each via hole is formed by applying a filled copper plating conductor in the corresponding via hole 19. . As far as the user is concerned, it is usually difficult to fully fill each interlayer hole 19 to become a copper electroplated conductor. Because the through hole 19 is gradually filled with copper electroplated conductor, the shape of the hole (low drop, deprrssion) also changes. Therefore, depending on the shape of the via hole, the bubbles attached to the wall surface of the via hole 19 may be difficult to remove. However, in this embodiment, the substrate 51 is immersed in the plating solution 105 in a vertical direction, and at the same time as copper plating is applied, bubbles 109 are generated along the entire double-sided surface 53 of the substrate and rise to the double-sided Hitting, therefore, even if the filled via hole 21 is formed in the via hole 19, copper plating can be appropriately performed, and in addition, bubbles 1 09 can be prevented from continuously attaching to the via hole 19. As a result, it is possible to fill the entire via hole 19 with the copper-plated conductor without any flicker, so that a filled via hole 21 of a desired shape can be formed. In this embodiment, the substrate 51 to be copper-plated includes an insulating resin layer (lower layer) 9 and an electroplating barrier layer 33 forming both sides 53 of the substrate, and has openings 3 5 for the insulation resin layer 9 to be exposed. In the interstitial hole 19, it is intended to form -13-579663 5. The filled interstitial hole 2 1 of the description of the invention (12) is formed in the insulating resin layer 9 and the opening 3 3 in the plating barrier layer 3 3 Revealed. Therefore, the depth of each of the via holes 19 measured from the corresponding substrate surface 53 (the surface of the corresponding plating barrier layer 33) is deeper than in the case where the plating barrier layer 33 is not provided, so when the substrate 5 1 When immersed in the copper plating solution 105, air is often left in the interlayer holes 19, so that the final formed product contains air bubbles. In addition, when bubbles are attached to the interlayer holes 19 after the substrate 51 is immersed, it is difficult to remove the bubbles. As a result, if the plating barrier layer 3 3 is not provided, in most cases, it is difficult to form a filled via hole 21 having a desired shape. However, according to this embodiment, as described above, the substrate 51 is immersed in the plating solution 105 in a vertical state, and copper plating is performed, and at the same time, bubbles 1 09 are generated in a manner that a large number of bubbles along the entire substrate 5 3 rises and strikes. If yes, even if the depth of the interlayer holes 19 is increased due to the provision of the plating barrier layer 3 3, copper electricity ore can still be properly carried out, and at the same time, bubbles 1 09 can be prevented continuously. Attach to the via 19. As a result, a filled via hole 21 of a desired shape can be formed without flicker. When the copper plating is completed (after the filled interlayer holes 21 have been formed), a predetermined period of time elapses, the rack is pulled upward from the copper mineral liquid 103 by the moving mechanism and then moved horizontally to The next stage. In this way, the copper plating step is completed. Next, the plating barrier layer 3 3 is removed from the substrate 51, and the electroless copper plating layer 31 covered by the plating barrier layer 3 3 is exposed. After that, the so-called rapid etching is performed to remove the exposed electroless copper electricity. -14- 579663 V. Description of the invention (13) Plating layer 31. Next, a solder material barrier layer 11 having a pad-shaped opening 23 is formed on the insulating resin layer 9 and the second junction layer 27. In particular, a semi-hardened solder material barrier layer 9 is formed on each of the insulating layers 9 and the corresponding second junction layer 27, and is exposed through a mask conforming to the pad-shaped opening 23 by its preset pattern. , And then develop. Thereafter, it is hardened by heating to form a welding material barrier layer 11 of a predetermined pattern. Thereafter, a nickel plating layer and a gold plating layer are sequentially formed on the pad 27p exposed from the self-soldering material barrier layer Π. Therefore, the wiring board 1 shown in FIG. 1 is produced. The embodiments of the present invention are as described above, but the present invention is not merely as described above. Under the idea and main spirit of the present invention, there are various technical changes. In summary, the manufacturing method of the present invention is used to manufacture a multilayer resin wiring substrate 1, wherein the substrate is made of a plurality of insulating resin layers 7, 9 and 1 1 and a plurality of wiring layers 25 and 27, etc. However, the present invention can also be used to manufacture other types of junction substrates, including ceramic junction substrates, as long as the via hole conductors are formed in the via holes thereof by electroplating. Moreover, the core substrate may be a multilayer core substrate having a wiring layer therein. In the above embodiment, the via hole conductor 21 is set as a filled via hole, but the via hole conductor 21 can also be set as a conformable via hole, wherein the via hole 1 Not all of 9 are filled with plating materials. Furthermore, in the above embodiment, the via hole conductor (filled via hole) is formed by copper electroplating, but the present invention can be applied to the via hole conductor (filled via hole)
•15- 579663 五、發明說明（14 ) 的介層孔）係經其他金屬之電鍍者。 圖式簡單說明： 本發明之其他目的，特徵及優點等，將佐以如下之附 圖配合實施例之說明而更爲顯見，其中·· 第1圖爲本發明一實施例所製結線基板之部份放大剖 面圖。 第2圖用以製造該實施例結線基板之方法說明圖，所 使用之基板係在銅電鍍步驟中之基板者。 第3圖爲用以製造該實施例結線基板之方法說明圖， 係表示成形充塡之介層孔導體的銅電鍍步驟者。 第4圖爲用以製造該實施例結線基板之方法說明圖，係 表示藉銅電鍍形成充塡之介層孔導體後，基板之狀態者。 符號之說明： 7 板形芯 基 板 9 絕 緣 樹 脂 層 13 通 孔 15 通 孔 導 體 19 介 層 孔 25 第 1 結 線 層 31 電 銅 電 鍍 層 33 電 鍍 阻 擋 層 35 開 孔 5 1 基 板 53 對 向 基 板 方 向 -16-• 15-579663 V. Interposer hole of the invention description (14)) is electroplated by other metals. Brief description of the drawings: Other objects, features, and advantages of the present invention will be more apparent with the following drawings in conjunction with the description of the embodiments, where: FIG. 1 is a diagram of a wiring substrate made according to an embodiment of the present invention. Partially enlarged sectional view. Fig. 2 is an explanatory diagram of a method for manufacturing the wiring substrate of this embodiment. The substrate used is a substrate in a copper plating step. FIG. 3 is an explanatory diagram of a method for manufacturing the junction substrate of this embodiment, and shows a copper plating step of forming a filled via via conductor. Fig. 4 is an explanatory diagram of a method for manufacturing the wiring substrate of this embodiment, which shows the state of the substrate after forming a filled via via conductor by copper plating. Explanation of symbols: 7 plate-shaped core substrate 9 insulating resin layer 13 through-hole 15 through-hole conductor 19 via hole 25 first junction layer 31 electric copper plating layer 33 plating barrier layer 35 opening 5 5 substrate 53 facing the substrate- 16-