JP4354139B2 - Wiring board manufacturing method - Google Patents

Description

【００４７】
この基板に対し、無電解銅めっきで表面を導電化した後に、フィルドビア電気銅めっきを行った。電気銅めっき条件は表２に示す通りとした。
【００４８】
【表２】

【００４９】
この試験の結果を表３にまとめる。全般的にはアスペクト比が高くなるとボイド不良が発生するが、本発明の方法では電流密度の３Ａ／ｄｍ２のみにボイド不良が発生している。その他は不良の発生は皆無である。
【００５０】
【表３】

【００５１】
このように、本発明により、従来はボイドが発生していた条件でもボイドなく穴埋めすることが可能となり、埋め込み可能な範囲を広げることができることがわかった。ただし、埋め込み可能範囲は際限なく広げることができるわけではなく、それぞれの個別条件で、電流密度、ビアのサイズ（穴径，深さ），流速などの諸因子によって限定される。
【００５２】
【発明の効果】
従来は、電流密度を下げて、生産性を落とさなければ、ボイドが発生していた、穴径、深さのブラインドビアホールに対し、本発明の方法を用いてボイドなく穴埋めすることが可能となる。これにより、生産性を向上しつつ、ボイド発生の可能性を低減させるため、配線基板の性能向上につながる。
【図面の簡単な説明】
【図１】本発明のブラインドビアホールの電気銅めっき法の模式図。
【図２】従来技術のブラインドビアホールの電気銅めっき法の模式図。
【符号の説明】
１…ビルドアップ基板
２…ブラインドビアホール
３…めっき電極（カソード・基板表面）
４…めっき液バルク（層）
５…濃度勾配が生じている層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a wiring board manufactured through a process of filling a blind via hole by electrolytic copper plating, and more particularly to a method of manufacturing a wiring board characterized by an electrolytic copper plating means used in the process of filling a blind via hole.
[0002]
In recent years, with the miniaturization of electronic devices, the density of wiring layers of printed circuit boards used has been rapidly increased. For this reason, a substrate called a build-up substrate has been produced in large quantities. This build-up board is formed by alternately stacking insulating resin layers and wiring layers on the surface of the multilayer printed circuit board that is the core, and the conduction between the wiring layers forms via holes and copper plating is formed inside them. Done by doing. Conventionally, the copper layer was formed by applying the electroless copper plating and electrolytic copper plating techniques to the wall surface of the via hole, but in this method, the upper layer via hole cannot be formed on the via hole. There has been a problem that the degree of freedom in pattern design is lost. Therefore, a method called filled via, in which the via hole is filled with copper so that the via hole can be stacked on the via hole, has been attracting attention.
[0003]
[Prior art]
However, when this filled via is generally performed by electrolytic copper plating, voids are likely to be generated in the via hole 2 in the blind via hole 2 having a high aspect ratio (depth / hole diameter). In filled via electro copper plating, an accelerator and an inhibitor are added to the plating solution. The inhibitor suppresses the plating speed near the surface of the blind via hole 2, and the accelerator further increases the internal plating speed. The via hole 2 can be embedded. However, voids are generated when the copper ion supply rate corresponding to the plating rate increased by the action of the accelerator is not reached. That is, the generation of voids is determined by the relationship between the supply rate of copper ions from the copper plating solution and the consumption rate of copper ions by electroplating.
[0004]
Since the consumption rate of copper ions increases as the current density increases, it is important to increase the supply rate of copper ions to prevent the generation of voids as the current density increases.
[0005]
Conventionally, in the electroplating of the blind via hole 2 having a large aspect ratio, voids are prevented by reducing the current density. However, this method reduces the productivity of the plating process.
[0006]
On the other hand, in order to form a copper wiring for a semiconductor device, a “damascene process” including a step of performing electrolytic copper plating on a via and a trench formed on a wafer surface has been widely performed. In this process, hole filling is performed for vias and trenches having an opening diameter (width) of 0.2 μm or less and a depth of 2 μm or less. Is sufficiently supplied by diffusion, so that a sufficient embedding property can be expected even with a commonly used electrolytic copper plating solution. Further, since the copper film thickness to be plated is as small as 1 μm or less, the plating time may be short, and there is not much influence on the productivity of the plating process.
[0007]
On the other hand, as shown in FIG. 2, in the build-up substrate 1, the blind via hole 2 having a larger depth must be embedded. In this case, since the depth of the blind via hole 2 is large, the diffusion distance of copper ions (distance between the plating solution bulk 4 and the plating surface 3) is large, and the concentration gradient (concentration difference) serving as a driving force for diffusion is large. As a result, it was found that copper ion supply at a sufficient speed is less likely to occur in the blind via hole 2.
[0008]
Furthermore, since it is necessary to increase the plating film thickness in the build-up substrate 1 (> 10 μm), the plating time requires 45 minutes or more even at a normal current density (1 A / dm ² ). Lowering the current density leads to a significant decrease in productivity.
[0009]
[Problems to be solved by the invention]
The problem to be solved by the present invention is to have a blind via hole having a hole diameter of 0.5 to 150 μm, a depth of 2 to 100 μm, and an aspect ratio (depth / hole diameter) of 6 or less. In a build-up board made through a process of filling a hole by plating, the current density is not lowered, and the possible filling area where no void is generated is expanded.
[0010]
[Means for Solving the Problems]
The invention according to claim 1 of the present invention is a method of manufacturing a wiring board comprising a step of forming a wiring layer on a surface of a multilayer printed board serving as a core and a plating step of forming conduction between wiring layers.
The plating step includes a blind via hole having a hole diameter of 0.5 to 150 μm, a depth of 2 to 100 μm, and an aspect ratio (depth / hole diameter) of 6 or less, and filling the blind via hole by electrolytic copper plating. In the method of manufacturing a wiring board manufactured through the process, the electrolytic copper plating solution used in the process of filling the blind via hole is made of copper (II) ions 50 to 85 g / L, sulfuric acid 0 to 100 g / L, and chlorine ions. Using a plating solution containing 1 to 100 mg / L and containing an accelerator and an inhibitor, the temperature of the electrolytic copper plating solution is 30 to 65 ° C. , and the electrolytic copper plating solution is for a substrate having a blind via hole. Te, and this for performing electroplating to give a liquid flow parallel flow rate 0.05-0.5 M / s on the surface,
A method of manufacturing a wiring board characterized by the following.
[0011]
The invention according to claim 2 of the present invention is the method for manufacturing a wiring board according to claim 1, wherein the electroplating is performed at a current density of 3 A / dm ² or less .
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Since the supply of copper ions to the bottom of the blind via hole 2 is performed only by diffusion and liquid convection from the plating solution bulk 4 to the inside of the blind via hole 2, it is necessary to enhance both effects.
[0014]
In the present invention, in the filling of the blind via hole 2 in this region by copper plating, as described above, the supply of copper ions to the inside of the blind via hole 2 tends to be insufficient, so that diffusion and convection can be improved. I devised a way to improve both.
[0015]
In the present invention, in order to enhance the diffusion effect of copper ions, the copper concentration in the copper plating solution is increased, and in addition, the temperature of the plating solution is also increased.
[0016]
Furthermore, in the present invention, in order to enhance the effect of convection of the plating solution bulk 4, the flow of the plating solution bulk 4 parallel to the surface is applied to the build-up substrate 1 having the blind via hole 2 to perform electrolytic copper plating. I do.
[0017]
The theoretical process that led to the invention is shown below.
Mass transfer due to diffusion can be expressed as:
-DQ / dt = D * (Cb-Co) / δ ――――― (1)
Here, dQ / dt is the flux of the substance and is the amount of movement of the substance per unit time. D is the diffusion coefficient, Cb and Co are the concentration of the substance on the solution bulk and the electrode reaction surface, respectively, and δ is the distance of the layer (diffusion layer) where the concentration gradient occurs.
[0018]
On the other hand, the relationship between flux and current density is as follows:
−dQ / dt = I / (n * F) ――――― (2)
Thus, the current density I can be expressed as
I = n * F * D * (Cb-Co) / δ (3)
Here, n is the number of charges (n = 2 in Cu), and F is a Faraday constant. This I value is the maximum current density that can flow when only the movement of copper ions due to diffusion is taken into consideration.
[0019]
As described above, in filled via electrolytic copper plating, since the inside of the blind via hole 2 has a high current density due to the action of the accelerator, it is necessary to set copper ion supply conditions such that the value of I corresponds to that. If the conditions are not met, voids remain inside the blind via hole 2 due to insufficient supply of copper ions.
[0020]
From the above equation (3), it is necessary to increase the concentration difference (Cb-Co) and the diffusion coefficient in order to increase I in a diffusion-dominated situation. Since Co becomes almost zero on the electrode surface 4, it can be seen that it is necessary to increase Cb of the plating solution bulk 6. The diffusion coefficient can be increased by raising the temperature.
[0021]
With respect to δ, which is the distance of the layer 5 (diffusion layer) in which the concentration gradient is generated, I can be increased as the distance is decreased. In addition, since a concentration gradient always occurs inside the blind hole 2 where the plating reaction is taking place, it is considered that δ almost coincides with the depth of the blind hole 2. Therefore, the current density can be increased as the depth of the blind hole 2 is reduced. (See Figure 2)
[0022]
Attempts to increase the copper ion concentration in the copper plating solution have been made with respect to the above-described copper wiring for a semiconductor substrate. For example, in Japanese Patent Laid-Open No. 2000-80494 “copper damascene wiring plating solution”, the copper sulfate concentration is 4 so that copper ions are not diffusion controlled in the grooves and holes on the surface in the process of forming copper wiring by electrolytic copper plating. ˜200 g / L (copper concentration 1-50 g / L), sulfuric acid concentration 10-200 g / L, and chloride ion concentration 0-100 mg / L.
[0023]
In addition, in Japanese Patent Laid-Open No. 2001-49490 “Substrate Plating Method and Apparatus”, a copper sulfate concentration of 100 to 250 g / L (a copper concentration of 25 to 62.5 g / L), a sulfuric acid concentration of 10 to 100 g / L, and a chlorine ion concentration of 0 to A 100 mg / L plating solution is used. However, these are devised for semiconductor copper wiring, and are related to via holes having a hole diameter of 0.2 μm or less and a depth of about 1.2 μm or less.
[0024]
On the other hand, since the diffusion length of the copper ions inside the blind via hole 2 of the build-up substrate 1 which is an object of the present invention is large, it is difficult to control the diffusion rate only by the concentration condition of the plating solution. is there.
[0025]
Regarding the blind via hole 2 of the build-up substrate 1, it is necessary to raise the temperature of the plating solution in addition to the concentration condition of the plating solution. This effect is because the solubility of the copper ions in the plating solution is increased to increase the copper ion concentration and lead to an increase in the value of the diffusion coefficient.
[0026]
According to the first aspect of the present invention, in order to improve the copper ion diffusion effect, the copper concentration in the copper plating solution is increased and the temperature of the plating solution is also increased so that the supply of copper ions can be improved. .
[0027]
Specifically, plating is performed at a temperature of 30 to 65 ° C. using a plating solution containing copper (II) ions 50 to 85 g / L, sulfuric acid 0 to 100 g / L, and chlorine ions 1 to 100 mg / L. .
[0028]
If the copper ion concentration is less than 50 g / L, the effect of diffusion enhancement is low, and if it exceeds 85 g / L, the copper salt cannot be dissolved even if the liquid temperature is increased.
[0029]
If the sulfuric acid concentration exceeds 100 g / L, the copper salt cannot be dissolved within the above range. However, the inclusion of sulfuric acid can increase the electrical conductivity of the plating solution and improve the uniformity of the copper film thickness.
[0030]
When the concentration of chlorine is too low, the gloss of the plating film cannot be obtained, and when it is too high, the physical properties of the plating deposit are lowered.
[0031]
Due to the temperature rise of the plating solution, not only the copper ions but also the diffusion rate of the inhibitors and accelerators contained in the solution increases. As a result, the inhibitor and the accelerator have the same effect on the hole surface portion and the hole bottom portion of the blind via hole 2, and conformal (the copper plating film thickness of the blind via hole 2 surface portion and the bottom portion is equivalent). The shape tends to precipitate. When the temperature exceeds 65 ° C., this effect becomes remarkable and it becomes difficult to fill the blind via hole 2.
[0032]
In the present invention, it is preferable to reduce the concentration of the inhibitor and the accelerator as compared with the standard. For example, when using Cu-Brite VF (manufactured by Ebara Eugleite Co., Ltd.), the amount of additive is not 20 mL / L as standard, but 8 mL / L at 40 ° C. and 8 mL / L at 60 ° C. If it is less than 30 ° C., sufficient copper ions cannot be dissolved in the liquid, and the diffusion rate of copper ions is low, so voids are generated.
[0033]
Furthermore, in the invention according to claim 1 of the present invention shown in FIG. 1, the plating solution bulk 4 parallel to the surface of the buildup substrate 1 having the blind via hole 2 is improved in order to enhance the effect of convection of the solution. Electrolytic copper plating is performed by applying a liquid flow. The I value in the equation (3) takes into consideration only the effect of diffusion, but by forcibly moving the copper ions by convection, the bulk of the plating solution bulk 4 reaches the surface and inside of the blind via hole 2. By causing a liquid flow and increasing the supply amount of copper ions, it is possible to flow a current density larger than the I value by the effect.
[0034]
Parallel to the surface of the build-up substrate 1, the flow rate of the plating solution bulk 4 is set to 0.01 m / s or more, more preferably 0.05 to 0.5 m / s. As a result, a spiral liquid convection is formed inside the blind via hole 2, and this flow causes copper ions to flow from the plating solution bulk 4 into the blind via hole 2. Of course, the flow velocity inside the blind via hole 2 is significantly lower than that on the surface, but the larger the flow rate of the plating solution bulk 4 on the surface of the buildup substrate 1, the larger the convection inside the blind via hole 2 can be. This is effective in increasing the flow velocity.
[0035]
Since copper ions flow into the blind via hole 2 from the plating solution bulk 4, the distance between the laminar flow of the plating solution bulk 4 material concentration Cb and the concentration Co of the material on the electrode plating reaction surface is close, and δ In this case, the distance of the layer 5 (diffusion layer) in which the concentration gradient occurs is significantly reduced. As a result, the supply amount of copper ions is increased from the relational expression (1), and the current density associated with the expression (3) is also increased.
[0036]
However, in the high temperature region of the present invention, as described above, the diffusion rate of the coexisting inhibitor and accelerator is increased, so that the copper deposition on the blind via hole 2 tends to be in a conformal shape and is too strong. The current further promotes this effect. Accordingly, the upper limit of the liquid flow is suitably 0.5 m / s.
[0037]
A liquid flow of the plating solution bulk 4 parallel to the surface can be obtained by ejecting the solution from the nozzle in a direction parallel to or perpendicular to the build-up substrate 1. Even in the case of being perpendicular to the substrate 1 as well as in the case of being perpendicular, the liquid flow is directed in a parallel direction along the substrate surface after colliding with the substrate 1, so that a substantially parallel flow can be formed. . Due to the parallel flow, a spiral liquid convection is formed inside the blind via hole 2, and by this flow, the plating solution bulk layer 4 flows deeply into the blind via hole 2 and a large amount of copper ions is supplied to the surface of the plating electrode 3. The
[0038]
In the present invention, bis (3-sulfopropyl) disulfide (hereinafter abbreviated as “SPS”) can be mainly used as the accelerator, and the concentration is suitably 0.001 to 10 mg / L. As other accelerators, bissulfo disodium disulfide, bis (2-sulfoethyl) disodium disulfide, tetramethylthiuram disulfide, tetraethylthiuram disulfide, and the like can be used.
[0039]
As the inhibitor, a polyether compound can be used, and preferably polyethylene glycol (hereinafter abbreviated as “PEG”) (molecular weight 200 to 10,000) or a copolymer of PEG and polypropylene glycol (molecular weight 400 to 10,000).
) Is appropriate. The concentration is suitably 0.1 to 100 mg / L.
[0040]
In addition to the above components, the electrolytic copper plating solution mainly contains Janus Green B, a tertiary alkylamine, and polyepichlorohydrin as other additives, depending on the requirements such as the glossiness of the plating surface. Tetraammonium salt adducts, polyalkylethyleneimines, amide compounds and the like are also used. Of course, commercially available additives can also be used. Examples include Cu-Brite VF (manufactured by Sugawara Eugleite Co., Ltd.), Cupronal VF (manufactured by Nippon Leronal Co., Ltd.) and the like.
[0041]
As described above, when the via hole is filled by electrolytic copper plating to the blind via hole 2 having a hole diameter of 0.5 to 150 μm, a depth of 2 to 100 μm, and an aspect ratio (depth / hole diameter) of 6 or less, plating is performed. The temperature of the solution is set to 30 to 65 ° C., and the plating solution containing copper ions 50 to 85 g / L, sulfuric acid 0 to 100 g / L, and chlorine ions 1 to 100 mg / L is used to enter the inside of the via hole 3 of the blind via hole 2. To improve the supply of copper ions. Thereby, generation | occurrence | production of a void can be suppressed at the time of hole filling by electrolytic copper plating, and the application range which can be filled up compared with the past can be expanded.
[0042]
<Example 1>
According to the present invention, in the filling of the blind via hole 2 by electrolytic copper plating, it is possible to expand a plating condition range such as a size that can be embedded.
[0043]
Examples are shown below. First, one kind of double-sided board was selected for the multilayer printed circuit board as the core. In the build-up process of forming a wiring layer on the surface of the multilayer printed board, an insulating resin was applied to form an insulating resin layer. The insulating resin layer was optimized in the range of 100 μm to 2 μm. Blind via holes 2 were formed at predetermined positions on the surface of the insulating resin layer. The drilling method may be a photolithographic method or a laser beam irradiation, which is appropriately used.
[0044]
Next, the plating process for forming conduction between the wiring layers produced a wiring board made of filled vias. The blind via hole 2 is made through a process of filling with copper electroplating. First, a thin film layer is formed on the entire surface of the blind via hole 2 by electroless plating, and the thin film layer is used as an electrode by electroplating. Filled vias were formed by filling the blind via holes with electrolytic copper plating. Next, a photosensitive resin is applied to the entire surface to form a resist layer made of the photosensitive resin. A predetermined wiring circuit pattern was formed on the resist layer by photolithography using an exposure, development process, corrosion process, and thin film process. As described above, generally, insulating resin layers and wiring layers are alternately stacked on the surface of a multilayer printed circuit board serving as a core, and conduction between the wiring layers is performed by electrolytic copper plating in the blind via hole 2 to manufacture the wiring board. To do.
[0045]
Next, a build-up substrate 1 having four types of blind via holes 2 opened on the surface of the wiring substrate was produced. The four samples are shown in Table 1.
[0046]
[Table 1]

[0047]
The substrate was subjected to filled via electrolytic copper plating after the surface was made conductive by electroless copper plating. The electrolytic copper plating conditions were as shown in Table 2.
[0048]
[Table 2]

[0049]
The results of this test are summarized in Table 3. In general, a void defect occurs when the aspect ratio becomes high, but in the method of the present invention, a void defect occurs only in the current density of 3 A / dm2. In other cases, no defects occurred.
[0050]
[Table 3]

[0051]
As described above, according to the present invention, it has been found that it is possible to fill a hole without a void even under a condition where a void has been generated in the past, and it is possible to widen a range in which the void can be filled. However, the embeddable range cannot be expanded indefinitely, and is limited by various factors such as current density, via size (hole diameter, depth), and flow velocity under each individual condition.
[0052]
【The invention's effect】
Conventionally, if the current density is lowered and the productivity is not lowered, it becomes possible to fill the blind via hole having a hole diameter and depth without voids by using the method of the present invention. . This improves the performance of the wiring board in order to reduce the possibility of void generation while improving productivity.
[Brief description of the drawings]
FIG. 1 is a schematic view of an electrolytic copper plating method for a blind via hole according to the present invention.
FIG. 2 is a schematic view of a conventional method for electro copper plating of blind via holes.
[Explanation of symbols]
1 ... Build-up substrate 2 ... Blind via hole 3 ... Plating electrode (cathode / substrate surface)
4 ... Plating solution bulk (layer)
5 ... Layer with concentration gradient

Claims (2)

In a method for manufacturing a wiring board comprising a step of forming a wiring layer on the surface of a multilayer printed board serving as a core, and a plating step of forming conduction between wiring layers,
The plating step includes a blind via hole having a hole diameter of 0.5 to 150 μm, a depth of 2 to 100 μm, and an aspect ratio (depth / hole diameter) of 6 or less, and filling the blind via hole by electrolytic copper plating. In the method of manufacturing a wiring board manufactured through the process, the electrolytic copper plating solution used in the process of filling the blind via hole is made of copper (II) ions 50 to 85 g / L, sulfuric acid 0 to 100 g / L, and chlorine ions. Using a plating solution containing 1 to 100 mg / L and containing an accelerator and an inhibitor, the temperature of the electrolytic copper plating solution is 30 to 65 ° C. , and the electrolytic copper plating solution is for a substrate having a blind via hole. Te, and this for performing electroplating to give a liquid flow parallel flow rate 0.05-0.5 M / s on the surface,
A method of manufacturing a wiring board, characterized in that ^{2. The} method of manufacturing a wiring board according to claim 1, wherein electroplating is performed at a current density of 3 A / dm ² or less .

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