TW575952B - Lower profile package with power supply in package - Google Patents

Lower profile package with power supply in package Download PDF

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Publication number
TW575952B
TW575952B TW91137193A TW91137193A TW575952B TW 575952 B TW575952 B TW 575952B TW 91137193 A TW91137193 A TW 91137193A TW 91137193 A TW91137193 A TW 91137193A TW 575952 B TW575952 B TW 575952B
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Taiwan
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package
substrate
scope
component
patent application
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TW91137193A
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TW200301958A (en
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Eleanor P Rabadam
Richard B Foehringer
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Dc-Dc Converters (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

575952 玖、發明說明 :發明所屬之技術領域、先前技術、内容、 C發明所屬之技術領域3 背景 本發明是大致有關於積體電路，且特別是有於用以 5封裝一積體電路晶片之裝置。 C先前技術；j 一積體電路晶片可以藉由一微電子製程製造在一基 板上而該基板可為一矽晶圓，通常，多數被分割線分 開之晶塊（晶片）係同時形成在一單一晶圓上，各個晶片或 10晶塊係藉由在該等分割線上切割或鋸斷而分開。 各晶片必須與外部電路電氣地耦合，但是，該晶片 是易碎的且太小而不易處理。此外，它們亦容易受環境 之污染與腐蝕而被破壞，並且除非散熱，否則會在操作 時受到過熱的影響。_晶片封裝體為晶片提供機械支持 、電連接、防止受到污染與腐姓及在操作時之散熱。 封裝該晶片之製程可包括將該晶片黏著於該封裝體 片上之墊，及 將該晶 上，由在該封裝體上之引線接合至在該晶片 將該晶片包封起來以達成保護之目的。 以位在該晶
體内。由於該充電泵未結合於該晶片中 一位於封裝體内電源供應器（PSIP)結構係 片外侧之電感充電泵取代電容充電泵，但仍 開之被動電路元件， 起包含在該封裝體内 6 575952 玖、發明說明 ，所得之封裝體通常比較大，因此，成本可以節省，但 代價是封裝體尺寸較大。 該封裝體尺寸較大在某些應用中將會成為一問題， 設計者在使用PSIP零件時會猶豫，因為如此做會必須重 5 新設計電路板布局以配合較大之封裝體尺寸。在某些情 形下，額外的電路板空間可能難以取得。 因此，PSIP封裝體需要實質地保有非PSIP形態之因 素。 Γ發明内容3 10 圖式簡單說明 第1圖是本發明之一實施例之積體電路之封裝體的 放大橫截面圖； 第2圖是本發明之另一實施例之積體電路之封裝體 的放大橫截面圖；及 15 第3圖是第2圖所示之實施例之仰視圖。 I：實施方式3 詳細說明 請參閱第1 @，本發明之一實施例之一球格拇陣列 (BGA)封裝體1〇可包括一基板12，而該基板12則可與 2〇使用多數焊料球25之外部電路電氣輛合。該封裝體1〇 可包含-使用’例如，一適當黏著劑18而黏著於該基板 12之積體電路晶片14。在—實施例中，—組低度輪廊被 動疋件16a肖16b形成—位在該晶片14外部之充電果。 該等被動元件16a與16b可以使用，例如該黏著劑⑽ 7 575952 玖、發明說明 黏者於該晶片14之上表面。 該4充電泵元件16可包括電感器與電容器，該黏著 劑18可以是一環氧樹脂黏著劑。此外，由於該充電栗元 件16係位在該封裝體10中，雖然在該晶片ι4外側，但 5該封裝體可以是位於封裝體内電源供應器（PSIP)。 接合線20提供在該基板12與該晶片14之間的電氣 連接，以及在該基板12與該等被動元件丨6之間的電氣 連接。一保護罩24包封該晶片14與元件16，形成一模 製之陣列封裝體（MAP)。 10 藉由使用PSIP，可得到一較小之晶片14，但是，以 往’由於未結合該等元件，該封裝體尺寸會超過一通 常包括相同電氣裝置之非PSIP封裝體之形態因素。 該封裝體10可大致保持一對應非PSIP封裝體之形 態因素，因此該封裝體〗0可嵌入位在用於具有相同功能 15之對應非PSIP封裝體之電路板上的空間内，故，可得到 一結構緊密之封裝體10,且其具有一較佳成本並且大致 保持對應（但更昂貴的）非pSIp封裝體。
在某些貫施例中’該等被動元件1 6可以被選擇成具 有不超過16mii之高度。在某些實施例中，這封裝體 20 10之垂直輪廓可利用BGA封裝技術再降低，而該BGA 封裝技術係可產生一相較於插腳格柵陣列（pGA)封裝技術 較低之垂直輪廓。該封裝體之x、y尺寸可利用如使用者 分配之環氧樹脂作為黏著劑18而不是將該等被動元件16 表面安裝於在該晶片14旁之基板12的黏著方法。 8 575952 玖、發明說明 請參閱第2圖，在另一 pSIP實施例中，一球袼栅陣 列（BGA)封裝體26包括一安裝在一基板28上之積體電路 晶片29，在一例子中，該基板28之上表面可使用一罩 30來包封，該封裝體26係使用多數設置在該基板28之 5 下表面上之焊料球34而與外電路電氣地連接。多數包括 電感器與電容器之被動元件32a與32b可形成一在該晶 片29外部且設置在其下方的充電泵。 請參閱第3圖，該等元件32可以黏著在該基板28 下方且在一無焊料球34之中央區域33内。接著，該封 1〇裝體26藉由表面安裝該等焊料球34而與外部電路連接 〇 在一實施例中，該等被動元件32a與32b不會超過 該等焊料球34之高度，因此，該等被動元件32可包含 在該BGA基板28之下表面上且不會增加該封裝體26之 回度，如同該等被動元件係被結合在該晶片29之内側一 般。因此，由於psip結構，該封裝體26具有一較小晶 片29之優點且它仍具有大致相同之形態因素。 雖然本發明已對有限數目之實施例說明過了，但是 所屬技術領域中具有通常知識者可了解多㉟由其產生之 2〇修：與變化。以下申請專利範圍涵蓋落在本發明之精神 與範疇内之所有這些修改與變化。 【圖式簡說^明】 第1圖是本發明之—實施例之積體f路之封裝體的 放大橫截面圖； 9 575952 玖、發明說明 第2圖是本發明之另一實施例之積體電路之封裝體 的放大橫截面圖；及 第3圖是第2圖所示之實施例之仰視圖。 【圖式之主要元件代表符號表】 10.. .球格栅陣列封裝體 12…基板 14…晶片14 16，16&，161)...被動元件 18.. .黏著劑 20.. .接合線 24…保護罩 25.. .焊料球 26.. .球格柵陣列封裝體 28…基板 29.. .積體電路晶片 30···罩 32,32a，32b···被動元件 33···中央區域 34.. .焊料球 10

Claims (1)

  1. 575952 拾、申請專利範圍 10 15 20 1· 一種用於一電子裝置之封裝體，包含·· 一基板； 一積體電路晶片，安裝在該基板上； 一充電泵，包括一安裝在該晶片上之被動元件且 與該晶片電氣耦合，其中該元件由該晶片延伸出來之 長度小於或等於16mil。 2·如申請專利範圍第1項之封裝體 接於該基板之焊料球之球袼栅陣列 3·如申請專利範圍第2項之封裝體： 著劑黏著於該晶片。 4·如申請專利範圍第3項之封裝體， 用者分配之環氧樹脂。 5·如申請專利範圍第3項之封裝體， 片係使用接合線而與該基板電氣地連接 6·如申請專利範圍第1 固示1項之封裝體，其中該元件是一電 感器。 7·如申請專利範圍第1 項之封裝體，其中該元件是一電 容器。 I如申請專利範圍第1 禮制由 項之封裝體，其中該封裝體是一 横裘陣列封裝體。 I如申請專利範圍第1 位於封㈣免 、之封裝體，其中該封裝體使用 、子裝肢内電源供應器技術。 1()· 一種用於一雷 、電子裝置之封裝體，包含： 一基板； 包括一具有多數連 其中該元件係以黏 其中該黏著劑是使 其中該元件與該 a曰 11 g、申請專利範圍 —積體電路晶片，安裝在該基板上； 一具有多數連接於該基板之焊料球之球格柵陣列 ，該基板包括一無該等焊料球之區域；及 5 一充電泵，包括一安裝在該區域上之被動元件且 與該晶片電氣耦合，其中該元件由該晶片延伸出來之 長度小於或等於該等焊料球由該基板延伸出來的長度 〇 U.=申請專利範圍第H)項之封裝體，其中該元件係表面 安裝於該基板上。 〇 12.如中請專利第11項之封裝體，其中該黏著是-焊 料膏。 13. 如申請專利範圍第1G項之封裝體，其中該元件是一電 感益。 14. 如申請專利範圍第10項之封裝體，其中該元件是一電 容器。 15·如申請專利㈣第H)項之封裝體，其中該封裝體是一 模製陣列封裝體。 16.如申請專利範圍第1G項之封裝體，其中該封裝體使用 位於封裝體内電源供應器技術。 20 I7· 一種形成一封裝體之方法，包含： 形成一基板； 將-積體電路晶片安裝在該基板上； 形成八有充電栗之封裝體，且該充電系在該 封裝體中耦合於該晶片；& 12 拾、申請專利範圍 將—被動元件安裝在該晶片上且使該元件與該晶 片電氣地耦合，使得該元件由該晶片延伸出來的長度 小於或等於16mil。 又 $ 18.如中請專利範圍第17項之方法，包括將-具有多數焊 料球之球格栅陣列連接於該基板上。 19·如申請專利範圍第18項之方法，包括將該元件黏著於 該晶片上。 20.如申請專利範圍第19項之方法，包括使用使用者分配 之環氧樹脂來黏著於該元件。 10 21·㈣請專利㈣第2G項之方法，包括使用接合線來電 氣連接該7G件與該基板以及電氣連接該晶片與該基板 Ο 22.如申請專利範圍第17項之方法，包括形成一模製陣列 封裝體。 15 23·如申請專利範圍第17項之方法，包括使用位於封裝體 内電源供應器技術。 24· —種形成一封裝體之方法，包含： 形成一基板； 將一積體電路晶片安裝在該基板上； 20 形成一包括一充電泵之封裝體，且該充電泵與該 晶片輕合； 將一具有多數焊料球之球格柵陣列連接至該基板 上’該基板包括一無該等焊料球之區域；及 將一被動元件安裝在該區域上且使該元件與該晶 13 5 拾、申請專利範圍 電氣地輕3，使付該元件由該晶片延伸出來的長戶 小於或等於該等焊料球由該基板延伸出來之長度。 25=申請專利範㈣24項之方法，包括將該元^表面安 裳於該基板上。 26.如申請專利範圍第25項之方法 接該元件。 27·如申請專利範圍第24項之方法 封裴體。 10 包括使用焊料膏來連 包括形成一模製陣列 包括使用位於封裝體 28·如申請專利範圍第24項之方、去 内電源供應器技術。 14
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