TW571395B - Multi-threshold MIS integrated circuit device and circuit design method thereof - Google Patents

Multi-threshold MIS integrated circuit device and circuit design method thereof Download PDF

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Publication number
TW571395B
TW571395B TW091123730A TW91123730A TW571395B TW 571395 B TW571395 B TW 571395B TW 091123730 A TW091123730 A TW 091123730A TW 91123730 A TW91123730 A TW 91123730A TW 571395 B TW571395 B TW 571395B
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macro
power supply
supply line
integrated circuit
critical
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TW091123730A
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Chinese (zh)
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Satoru Miyagi
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Fujitsu Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Description

571395 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明）571395 发明 Description of the invention (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and a brief description of the drawings)

t發明所屬之技術領域I 發明領域 本發明係論及一種多臨界電壓式MIS積體電路裝置和 5 其一電路设計方法，以及係特別論及一 Ml S(金屬絕緣體半 導體）’·尤其是特別論及一多臨界電壓式CMOS(互補型金 屬氧化物半導體）積體電路裝置，和彼等之電路設計方法 ’彼等係設置有一種電路，其係包括一低臨界電壓式MIS 電晶體，和一可在待命期間遮蔽一流經此電路之漏電流的 10 高臨界電壓式MIS電晶體。The technical field to which the invention belongs I. Field of the Invention The present invention relates to a multi-critical voltage type MIS integrated circuit device and a circuit design method, and particularly to an Ml S (metal insulator semiconductor) '· especially In particular, a multi-critical voltage type CMOS (complementary metal-oxide-semiconductor) integrated circuit device and their circuit design methods are described. They are provided with a circuit that includes a low-critical voltage type MIS transistor. And a 10 high critical voltage type MIS transistor that can shield the leakage current through the circuit during standby.

L· iltr U 發明背景 近年來，人們一直在追求較高速之可攜式電子裝置， 和彼等較低之電力消耗，以便有長的電池壽命。在CM〇s 15 LSI中，由於電力消耗係正比於其電壓之平方，其電力消 耗之降低，可藉由降低其電力供應電壓來加以完成。然而 P牛低其黾力供應電壓’將會導至彼等s電晶體之運作 速率的降低。因此，其運作速率之提昇，一直是藉由降低 彼等MOS電晶體之臨界電壓來加以達成。 2〇 然而，降低其臨界電藶，將會造成彼等MOS電晶體在 待命期間之漏電流的增加，其結果是使其很難達成較低之 電力消耗。為克服此等.問題，人們_直是使用—類似家 7(A)和7(B)圖中所顯示2MTCM〇s(多臨界電壓cm〇s)。 在第7(A)圖中，有一包括一低臨界電壓式m〇s電晶體 5 571395 玖、發明說明 之邏輯電路10，連接於一實質電力供應電壓V_VDD之供應 線與一接地電壓VSS之供應線中間，以及有一可用以遮蔽 其漏電流之高臨限電壓式PMOS電晶體T1，連接於上述實 質電力供應電壓V_VDD之供應線與一電力供應電壓VDD 5 之供應線中間。在活動時間中，其電力控制信號*PCNT， 係使成為低邏輯位準，而使其PMOS電晶體T1啟通，以及 其V_VDD供應線之電壓，因而會變為VDD，舉例而言， 1.8 V。反之，在待命期間，其電力控制信號*PCNT，係使 成為高邏輯位準，而使其PMOS電晶體T1啟斷，以及其邏 10 輯電路10之漏電流，因而會被遮蔽掉。 參照第7(B)圖，有一可用以遮蔽其漏電流之高臨限電 壓式PMOS電晶體T2，連接於上述實質電力供應電壓 V_VDD之供應線與其電力供應電壓VDD之供應線中間， 以及有一可用以遮蔽其漏電流之高臨限電壓式NMOS電晶 15 體T3，連接於上述實質電力供應電之供應線與其 電力供應電壓VSS之供應線中間。在活動時間中，彼等互 補式電力控制信號*PCNT和PCNT，係使分別成為低邏輯 位準和高邏輯位準，而使該等PMOS電晶體T2和NMOS電 晶體T3啟通。反之，在待命期間，該等電力控制信號 20 *PCNT和PCNT，係使分另|J成為高邏輯位準和低邏輯位準 ，而使該等PMOS電晶體T2和NMOS電晶體T3啟斷，以及 其邏輯電路10之漏電流，因而會被遮蔽掉。 下文之說明係僅針對一具有第7(A)圖之漏電流屏蔽電 路的情況，但其同樣適用於一具有第7(B)圖之漏電流屏蔽 6 571395 玖、發明說明 電路的情況。 如第8圖中所示，其一巨集器20係包括N個元件列21至 一 牛例而a，如第9圖中所示，每一元件列係包含許多 ^準％件31 ' 32、33、··· ’和-些邏輯閘，前者係包含一 一 口具有可用以遮蔽漏電流之高臨界電壓的pM〇s電晶體 ，每一閘極則係供有*PCNT，以及後者係包含一些各具有 低界電壓式M0S電晶體。或者，如第10圖所示，每一元 件列係包含一標準元件30和一些類似NAND邏輯閘元件 31八、反相器元件32A等標準元件，前者僅包含一具有可 1〇用以遮蔽漏電流之高臨界電壓的PMOS電晶體，以及後者 係包含一些各具有低臨界電壓式MOS電晶體。在一元件列 中，係佈置有多數可用以遮蔽漏電流之標準元件3〇。 在一巨集器係作為1p(智慧財產）而購買自其他公司之 f月况中，右该巨集器並未包括一可用以遮蔽漏電流之M〇s 5電曰θ體，此MOS電晶體務必要如第9或丨〇圖中所示地被嵌 入而且，當該巨集器係包括一些可用以遮蔽漏電流之 M〇S包晶體時，此可用以遮蔽泄漏電流之M0S電晶體，務 必要自每元件列移除，藉以達成較高之積體化，而犧牲 其待命期間之電力消耗的降低。 2〇 此外，在第9圖所顯示之電路的情況中，由於上述漏 電流屏蔽MOS電晶體之閘極寬度在決定上，係考慮到流經 其邏輯閘之電路的裕度，以便不致阻礙到每一邏輯閘有關 速率之提昇，其整個電路中之裕度，將會變得過大，而增 加了此巨集為在其基質上面所佔據之面積。在第^圖所顯 7 坎、發明說明 丁之電路的情況中’由於在其漏電流屏蔽元件中，並未納 =輯閘’其無用之面積將變得増大，因而會增加該巨集 口口在其基質上面所佔據之面積。 t ^ 發明概要 因此，本發明之一目地，旨， 曰在&供一種多臨界MIS(金 屬絕緣體半導體）積體電路裝 罝和其一電路設計方法， 〆、中之巨集器，並不需要句 ^ 而要匕括貫貝電力供應線和一高臨 界電壓式漏電流屏蔽MI S電晶體。 10 在本發明之—特徵中，係提供有-種多臨界體 電路裝置，其-基體上面係包括： 、一巨集器，其係包括一内部電路和一與此内部電路相 連接之貫質電力供應線，其内部電路，係包括—具有一第 一臨界電壓之MIS電晶體；和 15 -漏電流屏蔽MIS電晶體元件，其係具有一與一電力 制線相連接之閘極線，具有_與此閉極線相重合之縱長 方向’在形成上係沿其巨集器之巨集器框的邊緣，具有一 與其第-臨界電壓不同之第二臨界電壓，以及具有一其一 20 明内容】 端部和另-端部分別連接至一電力供應線和第一實質電力 供應線的電路路彳呈。 、依據it匕酉己置，上述未包含實質電力供應線和一漏電 机屏蔽MIS電晶體之巨集器的電力供應線，可被用作一實 質電力供應線。此外，此可容許降低一多臨界·積體電 置之4時間。進而’上述漏電流屏蔽應電晶體元 8 571395 玖、發明說明 件類似長度等之尺度，可依據其巨集器之電流消耗，適當 地加以決定，藉以相照於先存技藝，抑制其巨集器在其義 質上面所佔據之面積的增大。 圖式簡早說明 5 第1圖係一依據本發明之一第一實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖； 第2圖係一可更明細顯示第丨圖中所示pM〇s電晶體元 件5 1和其鄰近之佈線圖； 第3圖係一可更明細顯示第1圖中所示巨集器2〇a之— 10 部份内部的佈線圖； 第4圖係一依據本發明之一第二實施例的多臨界電壓 MOS積li電路裝置之示意晶片上佈線圖； 第5圖係一依據本發明之一第三實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖； 15 第6圖係一依據本發明之一第四實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖； 第7(A)和7(B)圖係一些可顯示先存技藝式多臨界電壓 CMOS半導體電路之視圖； 第8.圖係一可顯示一先存技藝式由一些標準元件陣列 20所組成之先存技藝式巨集器的佈線圖； 第9圖係一可顯示第8圖中所示一部分元件列的電路圖 ;而 第10圖則係一可顯示第8圖中所示一部分元件列的另 一配置之電路圖。 9 571395 玫、發明說明 【實施方式3 較佳實施例之詳細說明 下文將參照諸圖更詳細地說明本發明之較佳實施例。 第一實施例 5 第1圖係一依據本發明之一第一實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖。 有一些巨集器20A、20B、和20C，係佈置在一半導體 晶片50上面，以及彼等中的任何一個，並未具有第7(A)或 7(B)圖中所顯示之漏電流屏蔽電路，但舉例而言係一些作 10為1P而購買自其他公司者。彼等巨集器20A、20B、和20C ，舉例而言，分別係一記憶體、一 DSP(數位信號處理器） 、和CPI)。依據本發明，在決定上是否使用該等巨集器 20A至20C中之電力供應電壓VDD和vss的供應線，使分別 作為實質電力供應電壓V一 VDD和V-VSS，係依據是否使此 15等供應線獨立地與彼等漏電流屏蔽電路相連接，來加以決 定。在第一實施例中，由於該等巨集器2〇A至2〇c中之 VDD供應線，係被用作V—VDD供應線，VDD係以v—vdd 表示。 該等巨集器20A至20C中之巨集器框，全係呈矩形之 20外形，以及有一些高臨界電壓式漏電流屏蔽讀⑽電晶體 元件，係沿每一巨集器框之邊緣而佈置。 更明確地說，彼等PM0S電晶體元件51至53，係在其 巨集器20A之巨集器框的周圍部分内，沿此巨集器框之三 個邊緣而佈置。其元件ϋ6 ^L. iltr U Background of the Invention In recent years, people have been pursuing higher speed portable electronic devices and their lower power consumption in order to have a long battery life. In the CMOS 15 LSI, since the power consumption is proportional to the square of its voltage, the reduction of its power consumption can be accomplished by reducing its power supply voltage. However, the lower the supply voltage of the P-Null will cause the operating speed of their transistors to decrease. Therefore, the improvement of its operating speed has been achieved by reducing the threshold voltage of their MOS transistors. 2〇 However, reducing their critical voltage will cause the leakage current of their MOS transistors to increase during standby. As a result, it will be difficult to achieve lower power consumption. To overcome this problem, people use it directly—similar to the 2MTCM0s (multi-critical voltage cm0s) shown in the figures 7 (A) and 7 (B). In Figure 7 (A), there is a logic circuit 10 including a low critical voltage type MOS transistor 5 571395 玖, an explanation of the invention, a supply line connected to a substantial power supply voltage V_VDD and a ground voltage VSS supply In the middle of the line, there is a high-threshold voltage PMOS transistor T1 that can be used to shield its leakage current. It is connected between the supply line of the substantial power supply voltage V_VDD and the supply line of a power supply voltage VDD 5. During the active time, its power control signal * PCNT is set to a low logic level, which causes its PMOS transistor T1 to turn on, and the voltage of its V_VDD supply line, so it will become VDD, for example, 1.8 V . Conversely, during standby, its power control signal * PCNT is set to a high logic level, causing its PMOS transistor T1 to turn on and off, and the leakage current of its logic circuit 10, which will be masked. Referring to FIG. 7 (B), there is a high-threshold voltage PMOS transistor T2 that can be used to shield its leakage current, which is connected between the supply line of the above substantial power supply voltage V_VDD and the supply line of its power supply voltage VDD, and there is an available A high-threshold voltage NMOS transistor 15 body T3, which shields its leakage current, is connected between the above-mentioned supply line of substantial power supply and the supply line of its power supply voltage VSS. During the active time, their complementary power control signals * PCNT and PCNT make the low logic level and high logic level, respectively, so that these PMOS transistors T2 and NMOS transistors T3 are turned on. On the contrary, during the standby period, the power control signals 20 * PCNT and PCNT make the | J high and low logic levels, and the PMOS transistors T2 and NMOS transistors T3 are turned on and off. And the leakage current of the logic circuit 10 will be shielded. The following description is only for the case of a leakage current shielding circuit with Figure 7 (A), but it also applies to the case of a leakage current shielding with Figure 7 (B). As shown in FIG. 8, a macro-collector 20 includes N element rows 21 to 1 and a. As shown in FIG. 9, each element row includes a plurality of standard elements 31 ′ 32 , 33, ..., and some logic gates, the former is a pM0s transistor with a high threshold voltage that can be used to shield the leakage current, each gate is provided with * PCNT, and the latter is Contains a number of low-voltage MOS transistors. Alternatively, as shown in FIG. 10, each element series includes a standard element 30 and some similar standard elements such as NAND logic gate element 31, inverter element 32A, etc., the former includes only one element with a size of 10. PMOS transistors with high current threshold voltages, and the latter include some MOS transistors each with a low threshold voltage. In a component row, a plurality of standard components 30 which can be used to shield leakage current are arranged. In the case of a macro device purchased from other companies as 1p (intelligent property), the macro device does not include a MOS body which can be used to shield leakage current. This MOS device The crystal must be embedded as shown in Figure 9 or 〇. Also, when the macro-system includes some MOS package crystals that can be used to shield the leakage current, this MOS transistor can be used to shield the leakage current. It must be removed from each component row in order to achieve a higher integration, while sacrificing the reduction of power consumption during its standby period. 2〇 In addition, in the case of the circuit shown in FIG. 9, the gate width of the MOS transistor is determined due to the leakage current, and the margin of the circuit flowing through the logic gate is taken into consideration so as not to hinder The increase in the speed of each logic gate will increase the margin in the entire circuit, and increase the area occupied by this macro on its substrate. In the case of the circuit shown in Fig. 7 and the description of Ding's circuit, 'Because it is not included in its leakage current shielding element, it will become unusable area, which will increase the macro port. The area occupied by its substrate. ^ SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a multi-critical MIS (metal insulator semiconductor) integrated circuit device and a circuit design method therefor. Sentences are needed. Instead, use a penetrating power supply line and a high threshold voltage leakage current shielded Mist transistor. 10 In the feature of the present invention, a multi-critical body circuit device is provided. The base body includes: a macro-concentrator, which includes an internal circuit and a continuous circuit connected to the internal circuit. A power supply line whose internal circuit includes a MIS transistor having a first critical voltage; and a 15-leakage current shielding MIS transistor element having a gate line connected to a power system line having _The lengthwise direction coinciding with this closed pole line is formed along the edge of the macroframe of its macro, has a second critical voltage different from its first critical voltage, and Contents of the circuit: The end and the other end are connected to a circuit of a power supply line and a first substantial power supply line, respectively. According to it, the above-mentioned power supply line that does not include a substantial power supply line and a macro-collector of a leakage-shielded MIS transistor can be used as a substantial power supply line. In addition, this allows to reduce the time of a multi-critical integrated circuit by 4 times. Furthermore, the above-mentioned leakage current shielding transistor 8 571395 玖, the similar length of the invention description, etc. can be appropriately determined according to the current consumption of its macro device, so as to compare with the pre-existing technology and suppress its macro. The increase in the area occupied by the organ over its meaning. Brief description of the drawings 5 Fig. 1 is a schematic wiring diagram on a chip of a multi-critical voltage MOS integrated circuit device according to a first embodiment of the present invention; Fig. 2 is a diagram showing the details in Fig. 丨Figure 4 shows the pM0s transistor element 51 and its adjacent wiring diagrams; Figure 3 is a wiring diagram showing the details of the -10 part of the macro-processor 20a shown in Figure 1; Figure 4 FIG. 5 is a schematic wiring diagram on a wafer of a multi-critical voltage MOS integrated circuit device according to a second embodiment of the present invention; FIG. 5 is a multi-critical voltage MOS integrated circuit device according to a third embodiment of the present invention 15 is a schematic diagram of a wiring on a wafer; FIG. 6 is a schematic diagram of a wiring on a wafer of a multi-critical voltage MOS integrated circuit device according to a fourth embodiment of the present invention; FIGs. 7 (A) and 7 (B) are Some views showing pre-existing technology-type multi-critical-voltage CMOS semiconductor circuits; FIG. 8 is a wiring diagram showing a pre-existing technology-type macro device composed of some standard element arrays 20; Figure 9 is a circuit diagram showing a part of the component rows shown in Figure 8; and FIG 10 is a system circuit diagram showing another configuration may be a portion of the element row as shown in FIG. 8. 9 571395 Description of the invention [Detailed description of the preferred embodiment of the third embodiment The preferred embodiment of the present invention will be described in more detail below with reference to the drawings. First Embodiment 5 FIG. 1 is a schematic on-wafer wiring diagram of a multi-critical voltage MOS integrated circuit device according to a first embodiment of the present invention. There are some macros 20A, 20B, and 20C, which are arranged on a semiconductor wafer 50 and any of them, and do not have the leakage current shield shown in Figure 7 (A) or 7 (B). Circuit, but for example, some are 10 for 1P and purchased from other companies. The macros 20A, 20B, and 20C are, for example, a memory, a DSP (digital signal processor), and a CPI, respectively. According to the present invention, whether to use the supply lines of the power supply voltages VDD and vss in the macros 20A to 20C to determine the actual power supply voltages V_VDD and V-VSS, respectively, is determined based on whether or not the The supply lines are independently connected to their leakage current shielding circuits to determine. In the first embodiment, since the VDD supply lines in the macros 20A to 20c are used as V-VDD supply lines, VDD is represented by v-vdd. The macroframes in these macroframes 20A to 20C are all in the shape of a rectangular 20, and there are some high critical voltage leakage current shielding reading transistor elements, which are along the edges of each macroframe. Layout. More specifically, their PMOS transistor elements 51 to 53 are arranged in the peripheral portion of the macroframe of their macro 20A, and are arranged along three edges of this macro frame. Its element ϋ6 ^

仵51係包括·一平行於其巨集器20A 10 571395 玖、發明說明 之巨集器框的一個邊緣之閘極線51G ,和一分別成整體形 成於此閘極線5 1G之兩側的源極區域5丨s和汲極區域5 id。 此凡件5 1之縱長方向，係與其閘極線5 1G之方向相重合。 些說明在此半導體晶片50之邊緣部分内的矩形，係指示 5 一些各為一供外部電力供應電壓用之墊片的I/O元件，或 一供外部信號和一 I/O緩衝邏輯閘用之1/0元件。 該等PMOS電晶體元件5 1與巨集器20A間之關係，係 與第7(A)圖中所顯示之PM0S電晶體丁丨和邏輯電路1〇間的 關係相同。上述PMOS電晶體元件5 1之源極區域5 1 S，係連 1〇接至彼等VDD墊片60和61，以供外部連接用，其閘極線 51G係連接至一;[/〇元件73，以及其汲極區域51]〇，係連接 至其巨集器20A之V一 VDD端子。其I/O元件73 ,係包括一 墊片73a和一緩衝邏輯閘73b ,後者係具有一連接至其墊片 73a之輸入端，和一連接至其閘極線51G之輸出端。其巨集 15器20A内一未示出之VSS供應線，係連接至上述半導體晶 片50之邊緣部分内所形成的之vss墊片。 其墊片73a可接收來自外部之電力控制信號*pCNT。 在活動時間中，此電力控制信號*PCNT，係使成為低邏輯 位準，而使其PMOS電晶體元件51啟通，以及上述施加至 20 VDD墊片60和61之電力供應電壓VDD，係透過其？1^〇8電 晶體元件51，施加至其巨集器2〇A内之ν—νΕω線。在待命 期間，該電力控制信號*PCNT，係使成為高邏輯位準，藉 以啟斷其PMOS電晶體元件5 1，因而可阻礙漏電流，不使 流經其1集器20 A内所包括而在啟斷狀態中之低臨界電壓 11 571395 玖、發明說明 式MOS電晶體。 該等PMOS電晶體元件52至54之運作和配置，係與上 述PMOS電晶體元件51者相類似。 應用至該等巨集器20B和20C者，係與上述巨集器20A 5 者相同。亦即，彼等PMOS電晶體元件54至56，係沿其巨 集器20B之巨集器框的三個對應邊緣而佈置，以及彼等 PMOS電晶體元件57、58、59A、和53，係沿其巨集器20C 之四個對應邊緣而佈置。由於其巨集器20C，係具有相當 高之電流消耗，其一PMOS電晶體元件59B，在佈置上係與 10 其PMOS電晶體元件59A並聯，以及其PMOS電晶體元件 59A和59B，係並聯連接在該等巨集器20C與VDD墊片69之 間。其PMOS電晶體元件51至59B之閘極線，係彼此共同連 接在一起。彼等VDD墊片62至72，係連接至該等相應 PMOS電晶體元件之對應源極區域。 15 第2圖係一可更明細顯示第1圖中所示PMOS電晶體元 件51和其鄰近之佈線圖。 在第2圖中，其X和Y方向中之金屬線，係隸屬不同之 接線層，以及參考符號A和B，係分別指示一些在一第一 金屬接咸層和一在其上方之第二金屬接線層的金屬。不同 20 接線層内之接線間的配線，係透過此圖中以表示在對 應接點孔内之導體相連結。在第2圖中，電壓VDD和 V—VDD之接線係力口有斜線。一些說明在其巨集器20A和 I/O元件之邊緣部分内的小矩形，係指示一些將此等巨集 器20 A和I/O元件視為黑箱時之端子，彼等係供此等巨集器 12 571395 玖、發明說明 與I/O元件用之自動接線設計。其一 VDD供應線80A和一 VSS供應線81A ’係分別隸屬第1圖中之虛線所示的VDD供 應環80和VSS供應環81，在此圖中，為簡單計，每一虛線 係代表V.DD和VSS環兩者。 5 其一 VDD供應線82B1，係連接於該等VDD墊片60與 VDD供應線80A之間，以及其VDD供應線82B2和82B3，係 連接於該等VDD供應線80A與源極區域51S之間。此外， 彼等VDD供應線83B1、83B2、和83B3，係連接於其汲極 區域51D與其巨集器20A之對應V—VDD端子中間。其VSS 10 供應線81A，一邊係連接至一未示出之VSS墊片，以及另 一邊係透過彼等VSS供應線84B1和84A，以及接著透過彼 等VSS供應線84B2和84B3，連接至其巨集器20A多數之 VSS端子。其緩衝邏輯閘73bi輸出端，係透過該等控制 信號線85B1、85A1、85B2、和85A2，連接至其閘極線 15 5 1G。在第2圖中，此等控制信號線為簡單計，係以中心線 顯示。 第3圖係一可部份地顯示第1圖中所示巨集器2〇A之内 部的明細佈線圖。 其巨集器20A之一第一元件列，係包括一身為標準元 20件之NAND邏輯閘元件31A和反相器元件32A。此等NAND 邏輯閘元件3 1A和反相器元件32A，係具有與第10圖者相 同之電路配置，以及兩者係透過一信號線34彼此相連接。 在第3圖中，此信號線為簡單計，係以中心線顯示。為供 應一電力供應電壓給其第一元件列，沿著此第一元件列之 13 571395 玖、發明說明 一端側和另一端側，分別有一 VDD供應線83B1X和一 VSS 供應線84B2X形成。其V—VDD供應線83B2X，係供一第二 元件列使用。該等V—VDD供應線83B1X、VSS供應線 84B2X、和V—VDD供應線83B2X，係分別連接至第2圖中 5 所顯示之V—VDD供應線83B1、VSS供應線84B2、和 V—VDD供應線83B2。每一元件之V—VDD供應線，係在一 與V_VDD供應線86A相垂直之方向中，與其相連接，以及 同樣地，每一元件之VSS供應線，係在一與VSS供應線87A 相垂直之方向中，與其相連接。 10 依據此第一實施例之多臨界電壓MOS積體電路裝置， 由於其一高臨界電壓式漏電流屏蔽PMOS電晶體，在佈置 上係沿薯一巨集器之巨集器框的每一邊緣，在第9圖中所 顯示之先存技藝式巨集器内部的每一標準元件中，並不需 要佈置上述高臨界電壓式漏電流屏蔽PMOS電晶體T1，或 15 者在第10圖所顯示之每一元件列中，並不需要佈置該等多 數漏電流屏蔽標準元件30，此將可容許縮短其設計時間。 此外，上述漏電流屏蔽PMOS電晶體元件類似長度等之尺 度，係依據其巨集器之電流消耗，適當地加以決定，抑制 其巨集器在其基質上面所佔據之面積的增大。其結果是可 20 使由於在每一元件列之每一元件内的PMOS電晶體T1之形 成，或使由於在每一多數之元件内的漏電流屏蔽標準元件 30之形成，抑制其巨集器在其晶片上面所佔據之面積的增 大。 第二實施例 14 571395 玖、發明說明 第4圖係一依據本發明之一第二實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖。 5 10 在此半導體晶片50A中，該等電力供應電壓VDD和 vss，係自—些供外部連接狀vdd墊#，直接施加至一 巨集為2GD 〇此巨集器2GD，並未設置—高臨界電塵式電 源屏蔽MOS電晶體。此巨集器細，可透過_經由—控制 信號線90連接至—PM〇s電晶體元件^至”和”至”^的閘 極線之端子’輸出—電力控制信號*PCNT。使用此電力控 制信號*PCNT，其巨隼20Π，ϋ玄α # 4务al * ^ ^ 20D將可依據外部信號或内部 狀態，來執行該等PM0S電晶體元件51至53和57至596之啟 通/啟斷控制。其他者係與第一實施例相同。 第三實施例 第5圖係一依據本發明之一第三實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖。 15 在此半導體晶片50B中，代替第4圖之漏電流屏蔽 PMOS電晶體元件51，沿其巨集器2()A之巨集器框的一個 邊緣佈置的’是安排有—以1()()//111為例之預定長度而登錄 在一元件庫内的PMOS電晶體元件511至513。彼等相鄰之 PMOS電晶體511至513的閘極線，係彼此相連接。其巨集 20器2〇A所需PM0S電晶體元件511至513之數目，係基於此 巨集器20A在活動時間内之電流消耗，來加以決定。相同 之事件可應用至其他之PM0S電晶體元件。例外的是與第4 圖之PMOS電晶體元件59B相應者，已在第5圖中被省略。 其他者係與第一實施例相同。 15 571395 玖、發明說明 此第三實施例，可容許藉由使用一登錄在上述元件庫 内之單一電晶體元件，來形成每一巨集器有關之漏電流屏 蔽PMOS電晶體元件。 理應注意的是，第1和4圖中所顯示之每一漏電流屏蔽 5 NMOS半導體電晶體元件，可藉由連續佈置一些在預定長 度上使卉間無間隙之電晶體元件，來加以設立成。 第四個實施例 第6圖係一依據本發明之一第四實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖。 10 在此半導體晶片50C中，每一巨集器内部之VDD和 VSS供應線，係被用作對應之V_VDD*V_VSS供應線。此 夕卜，為在如第7(B)圖所示之VDD供應線側和VSS供應線側 ，形成該等漏電流屏蔽電路，有一些高臨界電壓式漏電流 屏蔽PMOS電晶體元件51P、53P、59AP、和59BP，連接於 15 該等供外部連接用之VDD墊片與彼等巨集器之V_VDD端 子中間，以及有一些高臨界電壓式漏電流屏蔽NMOS電晶 體元件52、57、和58，連接於該等供外部連接用之VSS墊 片與彼等巨集器之V__VSS端子中間。該等PMOS電晶體元 件51P、53P、59AP、和59BP之閘極線，和該等NMOS電 20 晶體元件52、57、和58之閘極線，係分別透過彼等控制信 號線91和90，連接至一巨集器20E之對應電力控制信號 *PCNT和PCNT的端子。 其巨集器20E，可容許藉由分別設定該等互補式電力 控制信號PCNT和*PCNT為高邏輯位準和低邏輯位準，而 16 571395 玖、發明說明 使δ亥等NMOS電晶體元件52、57、和％、和pM〇s電晶體 兀件51P、53P、59AP、和59BP啟通，以及可反向地容許 藉由設定低_位準和高邏輯位準，而使彼等啟斷。 雖然本發明之較佳實施例，業已經做了說明，理應瞭 5解的是，本發明並不受限於本說明書之說明，以及在不違 離本發明之精神與範圍之下，可做成各種之變更形式和修 飾體。 舉例而言，上述之漏電流屏蔽電晶體元件，可採用 NMOS半導體以代替PM0S。 1〇 此外’雖然第4圖中所顯示之半導體晶片5〇A在設立上 ’係使其巨集器20D，同時執行該等巨集器2〇A和20C所有 之漏電流屏蔽PMOS電晶體元件的啟通/啟斷控制，其巨 集器20D，係可獨立地執行其巨集器2〇A之漏電流屏蔽 PM〇S電晶體元件的啟通/啟斷控制，和其巨集器20C之漏 15電流屏蔽PMOS電晶體元件的啟通/啟斷控制。 此外，其低臨界電壓電晶體電路，僅被要求納入一 MIS電晶體。 【圖式簡單說明】 第1圖係一依據本發明之一第一實施例的多臨界電壓 20 MOS積體電路裝置之示意晶片上佈線圖； 第2圖係一可更明細顯示第i圖中所示pM〇s電晶體元 件5 1和其鄰近之佈線圖； 第3圖係一可更明細顯示第！圖中所示巨集器2〇a之一 部份内部的佈線圖； 17 571395 玖、發明說明 第4.圖係一依據本發明之一第二實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖； 第5圖係一依據本發明之一第三實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖； 第ό圖係一依據本發明之一第四實施例的多臨界電壓 MOS積體電路裝置之示意晶片上佈線圖； 第7(Α)和7(Β)圖係一些可顯示先存技藝式多臨界電壓 CMOS半導體電路之視圖； 弟8圖係一可劈干 土太The 仵 51 series includes a gate line 51G parallel to one edge of the macroframe 20A 10 571395 发明, an edge of the macroframe of the invention, and a gate line 51G formed integrally on both sides of the gate line 51G. Source region 5 s and drain region 5 id. The lengthwise direction of each piece 51 is coincident with the direction of its gate line 51G. The rectangles described in the edge portion of the semiconductor wafer 50 indicate 5 that each I / O element is a pad for external power supply voltage, or an external signal and an I / O buffer logic gate. 1/0 component. The relationship between the PMOS transistor 51 and the macro 20A is the same as the relationship between the PMOS transistor D1 and the logic circuit 10 shown in FIG. 7 (A). The source region 5 1 S of the above PMOS transistor element 51 is connected 10 to their VDD pads 60 and 61 for external connection, and its gate line 51G is connected to one; [/ 〇 element 73, and its drain region 51], are connected to the V-VDD terminal of its macro 20A. Its I / O element 73 includes a pad 73a and a buffer logic gate 73b, the latter having an input terminal connected to its pad 73a and an output terminal connected to its gate line 51G. A not-shown VSS supply line in the macro device 20A is connected to a vss pad formed in the edge portion of the semiconductor wafer 50 described above. The pad 73a can receive an external power control signal * pCNT. During the active time, the power control signal * PCNT is set to a low logic level, so that the PMOS transistor element 51 is turned on, and the power supply voltage VDD applied to the 20 VDD pads 60 and 61 described above is transmitted through its? 1 ^ 08 transistor element 51 is applied to the ν-νΕω line in its macro 20A. During the standby period, the power control signal * PCNT is set to a high logic level, so as to turn on and off its PMOS transistor element 51, which can block the leakage current and prevent it from flowing through its included 20 A collector. Low threshold voltage in the on-off state 11 571395 玖, invented MOS transistor. The operation and configuration of these PMOS transistor elements 52 to 54 are similar to those of the PMOS transistor element 51 described above. Those applied to these macros 20B and 20C are the same as those of the above-mentioned macros 20A 5. That is, their PMOS transistor elements 54 to 56 are arranged along the three corresponding edges of the macroframe of their giant 20B, and their PMOS transistor elements 57, 58, 59A, and 53, are Arranged along four corresponding edges of its macro 20C. Due to its macro 20C, it has a relatively high current consumption. One of its PMOS transistor elements 59B is arranged in parallel with 10 of its PMOS transistor elements 59A, and its PMOS transistor elements 59A and 59B are connected in parallel. Between the macros 20C and the VDD pad 69. The gate lines of the PMOS transistor elements 51 to 59B are connected to each other in common. These VDD pads 62 to 72 are connected to corresponding source regions of the corresponding PMOS transistor elements. 15 Fig. 2 is a wiring diagram showing the PMOS transistor element 51 shown in Fig. 1 and its neighbors in more detail. In the second figure, the metal wires in the X and Y directions belong to different wiring layers, and the reference symbols A and B indicate some of a first metal receiving layer and a second above it, respectively. Metal wiring layer metal. The wiring between the wirings in the different 20 wiring layers is connected to the conductors in the corresponding contact holes through this figure. In the second figure, the connection lines of the voltages VDD and V-VDD have diagonal lines. Some small rectangles illustrated in the edge portions of its macro 20A and I / O elements are indicative of some terminals when this macro 20 A and I / O elements are considered as black boxes, which are provided for these Macro device 12 571395 发明, invention description and automatic wiring design for I / O components. A VDD supply line 80A and a VSS supply line 81A ′ are respectively attached to the VDD supply ring 80 and the VSS supply ring 81 shown by the dotted lines in FIG. 1. In this figure, for simplicity, each dotted line represents V Both .DD and VSS rings. 5 One of the VDD supply lines 82B1 is connected between the VDD pads 60 and VDD supply line 80A, and the VDD supply lines 82B2 and 82B3 are connected between the VDD supply lines 80A and the source region 51S. . In addition, their VDD supply lines 83B1, 83B2, and 83B3 are connected between their drain regions 51D and their corresponding V-VDD terminals of the macro 20A. Its VSS 10 supply line 81A is connected to an unshown VSS pad on one side, and connected to its giant through their VSS supply lines 84B1 and 84A, and then through their VSS supply lines 84B2 and 84B3. The majority of VSS terminals of the collector 20A. The output of its buffer logic gate 73bi is connected to its gate line 15 5 1G through these control signal lines 85B1, 85A1, 85B2, and 85A2. In Figure 2, these control signal lines are for simplicity and are shown on the center line. Fig. 3 is a detailed wiring diagram which can partially show the inside of the macro 20A shown in Fig. 1. One of the first element arrays of the macro device 20A includes a NAND logic gate element 31A and an inverter element 32A, which are 20 standard elements. These NAND logic gate elements 31A and inverter elements 32A have the same circuit configuration as that of FIG. 10, and both are connected to each other through a signal line 34. In Figure 3, this signal line is a simple measure and is shown with the center line. In order to supply a power supply voltage to its first element row, 13 571395 玖 along the first element row, description of the invention One end side and the other end side, respectively, a VDD supply line 83B1X and a VSS supply line 84B2X are formed. The V-VDD supply line 83B2X is used for a second component row. The V-VDD supply line 83B1X, VSS supply line 84B2X, and V-VDD supply line 83B2X are connected to V-VDD supply line 83B1, VSS supply line 84B2, and V-VDD, respectively, shown at 5 in FIG. 2. Supply line 83B2. The V-VDD supply line of each component is connected to it in a direction perpendicular to the V_VDD supply line 86A, and similarly, the VSS supply line of each component is connected to a VSS supply line 87A. In its direction, it is connected to it. 10 The multi-threshold voltage MOS integrated circuit device according to this first embodiment, because of its high-critical-voltage leakage current shielding PMOS transistor, is arranged along each edge of the macroblock box of a macroblock. In each of the standard components inside the preexisting technology type macro shown in FIG. 9, it is not necessary to arrange the above-mentioned high critical voltage type leakage current shielding PMOS transistor T1, or 15 is shown in FIG. 10. It is not necessary to arrange the majority of the leakage current shielding standard components 30 in each component column, which will allow the design time to be shortened. In addition, the above-mentioned dimensions of the leakage current shielding PMOS transistor element are similarly determined according to the current consumption of the macro-controller, and the increase of the area occupied by the macro-controller on its substrate is appropriately suppressed. As a result, the formation of the standard component 30 can be suppressed due to the formation of the PMOS transistor T1 in each element of each element row or the leakage current in each of the plurality of elements, thereby suppressing its macro. The area occupied by the device above its wafer is increased. Second Embodiment 14 571395 (ii) Description of the Invention FIG. 4 is a schematic on-wafer wiring diagram of a multi-critical voltage MOS integrated circuit device according to a second embodiment of the present invention. 5 10 In this semiconductor wafer 50A, the power supply voltages VDD and vss are from some externally connected vdd pads #, which are directly applied to a macro 2GD. This macro 2GD is not set—high Critical Electro-Dust Power Shielded MOS Transistor. This macro is thin, and can be connected to the terminals of the gate line of the PMMOS transistor element through to the control signal line 90 to the output of the power control signal * PCNT. Use this power Control signal * PCNT, its giant 隼 20Π, ϋ 玄 α # 4serviceal * ^ ^ 20D will be able to perform the activation / startup of these PM0S transistor elements 51 to 53 and 57 to 596 according to external signals or internal states The other parts are the same as the first embodiment. Fig. 5 of the third embodiment is a schematic on-wafer wiring diagram of a multi-critical voltage MOS integrated circuit device according to a third embodiment of the present invention. 15 Here In the semiconductor wafer 50B, instead of the leakage current shielding PMOS transistor element 51 of FIG. 4, “is arranged” along one edge of the macroframe of the macroframe 2 () A—with 1 () () / / 111 is an example of a predetermined length and is registered in a component library of PMOS transistor elements 511 to 513. The gate lines of their adjacent PMOS transistors 511 to 513 are connected to each other. Its macro 20 devices 2 〇A The number of PM0S transistor elements 511 to 513 required is based on the current consumption of the macro 20A during the active time. The same event can be applied to other PM0S transistor devices. The exception is the corresponding to the PMOS transistor device 59B in Figure 4, which has been omitted in Figure 5. The others are related to the first The embodiment is the same. 15 571395 发明 Description of the invention This third embodiment allows the use of a single transistor element registered in the above-mentioned element library to form a leakage current shielded PMOS transistor element related to each macro device. It should be noted that each of the leakage current shielding 5 NMOS semiconductor transistor elements shown in Figures 1 and 4 can be set up by continuously arranging transistor elements with a predetermined length so that there is no gap between the plants. Fourth Embodiment FIG. 6 is a schematic on-wafer wiring diagram of a multi-critical voltage MOS integrated circuit device according to a fourth embodiment of the present invention. 10 In this semiconductor wafer 50C, each macro The internal VDD and VSS supply lines are used as the corresponding V_VDD * V_VSS supply lines. In addition, these drains are formed on the VDD supply line side and the VSS supply line side as shown in Figure 7 (B). Current shielding circuit, Some high critical voltage type leakage current shielding PMOS transistor elements 51P, 53P, 59AP, and 59BP are connected between 15 VDD pads for external connection and the V_VDD terminal of their macro, and there are some high critical Voltage-type leakage current shielding NMOS transistor elements 52, 57, and 58 are connected between these VSS pads for external connection and the V__VSS terminals of their macros. These PMOS transistor elements 51P, 53P, 59AP The gate lines of, and 59BP, and the gate lines of these NMOS 20 crystal elements 52, 57, and 58 are connected to the corresponding power control of a macro 20E through their control signal lines 91 and 90, respectively. Signal * PCNT and PCNT terminals. The macro 20E allows the complementary power control signals PCNT and * PCNT to be set to a high logic level and a low logic level, respectively, while 16 571395 发明, invention description makes δ Hai and other NMOS transistor elements 52 , 57, and%, and pM0s transistor elements 51P, 53P, 59AP, and 59BP are turned on, and they can be reversely allowed to be turned on and off by setting the low level and high logic level . Although the preferred embodiment of the present invention has been described, it should be understood that the present invention is not limited to the description of this specification, and can be done without departing from the spirit and scope of the present invention. Into various changes and modifications. For example, the above-mentioned leakage current shielding transistor element may use NMOS semiconductor instead of PMOS. 1〇 In addition, "Although the semiconductor wafer 50A shown in Fig. 4 is being set up", it is necessary to make the macros 20D, and simultaneously execute all the leakage currents of these macros 20A and 20C to shield the PMOS transistors The on / off control of the macro controller 20D can independently perform the on / off control of the leakage current shielding PMMOS transistor element of its macro 20A, and its macro 20C The leakage 15 current shields the on / off control of the PMOS transistor element. In addition, its low threshold voltage transistor circuit is only required to be incorporated into a MIS transistor. [Brief description of the drawings] FIG. 1 is a schematic on-wafer wiring diagram of a multi-critical voltage 20 MOS integrated circuit device according to a first embodiment of the present invention; FIG. 2 is a more detailed display of FIG. I The shown pM0s transistor element 51 and its adjacent wiring diagram; Figure 3 is a more detailed display of the first! The wiring diagram inside a part of the macro device 20a shown in the figure; 17 571395 发明, description of the invention 4. The diagram is a multi-critical voltage MOS integrated circuit device according to a second embodiment of the present invention Schematic wiring diagram on a wafer; FIG. 5 is a schematic wiring diagram on a wafer of a multi-critical voltage MOS integrated circuit device according to a third embodiment of the present invention; FIG. 5 is a fourth embodiment of the present invention Schematic on-wafer wiring diagrams of the multi-critical voltage MOS integrated circuit device; Figures 7 (A) and 7 (B) are some views showing pre-existing technology-type multi-critical voltage CMOS semiconductor circuits; Chopping dry soil too

係一可顯示第8圖中所示一 颂不先存技藝式由一些標準元件陣列 部分元件列的電路圖It is a circuit diagram that can show a circuit shown in Fig. 8 with some standard component arrays and some element arrays.

一配置之電路圖。 一部分元件列的另 18 571395 玖、發明說明 【圖式之主要元件代表符號表】 ίο...邏輯電路 20.. .巨集器 20A-20C...巨集器 20D··.巨集器 20E...巨集器 20A...巨集器元件 21-2N...元件歹 ij 30…標準元件 31，32,33，··.標準元件 31A...NAND邏輯閘元件 32A...反相器元件 34.. .信號線 5 0...半導體晶片 50A…半導體晶片 50B...半導體晶片 50C...半導體晶片 51.. .電晶體元件 51-53... PMOS電晶體元件 51D...汲極區域 51G...閘極線 515.. .源極區域 51Ρ，53Ρ，59ΑΡ，59ΒΡ···ΡΜΟ S電晶體元件 52.57.58.. .NMOS電晶體元件 54-56...PMOS電晶體元件 57,58,59A,53 ...PMOS 電晶體元件 59B...PMOS電晶體元件 60.61.. .VDD 墊片 62-72...VDD 墊片 69.. .VDD 墊片 73.. .1.O 元件 73a...墊片 73b...緩衝邏輯閘 80.. .VDD供應環 81.. .VSS供應環 80A...VDD供應線 81A...VSS供應線 82B1...VDD 供應線 82B2,82B3...VDD供應線 8361，8362,8363...乂00供應線 83B1X...VDD 供應線 83B2X...V_VDD 供應線 84B1，84A...VSS 供應線 84B2,84B3...VSS 供應線 84B2X...VSS 供應線 85B1，85A1，85B2,85A2·..控 制信號線 86A...V_VDD供應線 87A...VSS供應線 90.. .控制信號線 91.. .控制信號線 511-513...PMOS電晶體元件 19A configuration circuit diagram. Part of the component list of another 18 571395 发明, description of the invention [Schematic representation of the main components of the table of symbols] Logic circuit 20.... Macro device 20A-20C ... Macro device 20D ... Macro device 20E ... Macro 20A ... Macro element 21-2N ... Element 歹 ij 30 ... Standard element 31, 32, 33, ... Standard element 31A ... NAND logic gate element 32A .. Inverter element 34 .. Signal line 5 0 ... Semiconductor wafer 50A ... Semiconductor wafer 50B ... Semiconductor wafer 50C ... Semiconductor wafer 51..Transistor element 51-53 ... PMOS transistor Element 51D ... Drain region 51G ... Gate line 515 .. Source region 51P, 53P, 59Ap, 59Bp ... SMOS transistor 52.57.58 ... NMOS transistor 54-56 ... PMOS transistor element 57,58,59A, 53 ... PMOS transistor element 59B ... PMOS transistor element 60.61 ..... VDD pad 62-72 ... VDD pad 69..VDD Pad 73 .. .1.O Element 73a ... Pad 73b ... Buffer Gate 80. .. VDD Supply Ring 81 ... VSS Supply Ring 80A ... VDD Supply Line 81A ... VSS Supply Line 82B1 ... VDD supply line 82B2, 82B3 ... VDD supply line 8361, 8362, 8363 ... 乂 00 supply line 83B1X ... VDD supply Line 83B2X ... V_VDD supply line 84B1, 84A ... VSS supply line 84B2, 84B3 ... VSS supply line 84B2X ... VSS supply line 85B1, 85A1, 85B2, 85A2 ... Control signal line 86A ... V_VDD supply line 87A ... VSS supply line 90 ... Control signal line 91 ... Control signal line 511-513 ... PMOS transistor element 19

Claims (1)

571395 拾、申請專利範圍 1. 10 15 2. 20 3. 4. 一種多臨界MIS積體電路裝置，其係包括·· 第巨,其係包括_帛一内部電路和一連 接至此第-内部電路之第一實質電力供應線，此第一 内部電路，係包括-具有一第一臨界電塵之⑽電晶 體；和 一第一漏電流屏蔽MIS電晶體元件，其係具有一 連接至-第-電力控制線之第一間極線，係具有一與 =第-閘極線相重合之縱長方向，在形成上係沿著其 弟一巨集器之巨集器框的一個邊緣，係具有一不同於 第-臨界電壓之第二臨界電壓，以及係具有一其一端 部和另-端部分別連接至一第一電力供應線和第一實 質電力供應線的電流路徑， 其中之第一巨集器和第一漏電流屏蔽MIS電晶體 兀件，係形成在一基質上面。 如申請專利範圍第1項之多臨界廳積體電路裝置，其 ^弟一MIS電晶體元件’係具有一預定之尺度，其 夕數之第—MIS電晶體元件在佈置上，係沿著其第一 :集器之巨集器框的—個邊緣’以及其第-MIS電晶 體元件之每—相鄰對的閘極線，係彼此相連接。 如申請專利範圍第1項之多臨界MIS積體電路裝置，其 中之第-巨集器的巨集器框，係呈一矩形之外形，以 及其第一 MIS電晶體元件在佈置上，至少係沿著其巨 集器框之二個邊緣。 士申明專利乾圍第1項之多臨界MIS積體電路裝置，其 20 571395 拾、申請專利範圍 中之第一巨集器 係進一步包括一連接至其第一 電路之第二實質電力供應線， 此裝置係進一步包括： 一第二漏電流屏隔MIS電晶體元件，其係具有一571395 Patent application scope 1. 10 15 2. 20 3. 4. A multi-critical MIS integrated circuit device, which includes ... the first giant, which includes _ 帛 an internal circuit and a-internal circuit connected to this The first substantial electric power supply line, the first internal circuit, comprises-a triode with a first critical electric dust; and a first leakage current shielding MIS transistor element, which has a- The first pole line of the power control line has a lengthwise direction that coincides with the = th-gate line, and is formed along one edge of the macro-frame of its brother-magnet, and has A second threshold voltage different from the first threshold voltage, and a current path having one end portion and the other end portion connected to a first power supply line and a first substantial power supply line, respectively, wherein the first The collector and the first leakage current shielding MIS transistor element are formed on a substrate. For example, the multi-threshold integrated circuit device of the patent application No. 1 has a predetermined size of the MIS transistor element. The MIS transistor element in the arrangement is arranged along the MIS transistor element. First: The edge of the collector frame of the collector and the gate lines of adjacent pairs of each of its -MIS transistor elements are connected to each other. For example, the multi-critical MIS integrated circuit device of the first patent application scope, wherein the macro-frame of the first-macro device has a rectangular shape and the arrangement of the first MIS transistor element is at least Along the two edges of its macro box. Shi claimed that the multi-critical MIS integrated circuit device of item 1 of the patent patent, its 20,571,395, the first macro device in the patent application range further includes a second substantial power supply line connected to its first circuit, The device further includes: a second leakage current barrier MIS transistor element, which has a 部和另一端部分別連接至一第二 ’以及係具有一其一端 二電力供應線和第二實 質電力供應線的電流路徑。 5·如申請專利範圍第1項之多臨界MIS積體電路裝置，其 中之第一電力供應線，係連接至一形成在其基質上面 之墊片，此墊片係供外部連接用。 士申明專利範圍第4項之多臨界積體電路裝置，其 中之第二電力供應線，係連接至一形成在其基質上面 之塾片’此墊片係供外部連接用。 1 ·如申晴專利範圍第1項之多臨界MIS積體電路裝置，其 之弟電力供應線，係具有一形成於一包含該等第 巨木态和第一]Vfis電晶體元件之周緣内的電力供應 8·如申請專利範圍第1項之多臨界MIS積體電路裝置，其 中之第一電力控制線，係連接至一形成在其基質上面 之墊片，此墊片係供外部連接用。 9.如申請專利範圍第1項之多臨界MIS積體電路裝置，其 21 571395 拾、申請專利範圍 方法’其t之第-巨集器的巨集器框， 外：’以及其第-_電晶體元件在佈 沿著其巨集器框今二個邊緣。 η.如中請專利範圍㈣項之多臨界廳積體電路之設計 方其中之第一電力供應線，係連接至-形成在其 基質上面之墊片，此墊片係供外部連接用。 14.如中請專利範圍第1G項之多臨界廳積體電路之設計 方法，其中之第-電力供應線，係具有-形成於一包 10 含該等第-巨集器和第—MIS電晶體元件之周緣内的 電力供應環。 15 係呈一矩形之 置上，至少係 15·如申請專利範圍第1〇項之多臨界薦積體電路之設計 方法，其中進一步包括之步驟有：佈置一第二巨集器 此第一巨集器，係包括一可供應一控制信號至其第 電力控制線之第二内部電路，以及係連接至其第二 内邛電路和一形成在其基質上面之墊片，此墊片係供 外部連接用。 23And the other end are respectively connected to a second 'and a current path having one end, two power supply lines, and a second substantial power supply line. 5. The multi-critical MIS integrated circuit device according to item 1 of the scope of patent application, wherein the first power supply line is connected to a gasket formed on the substrate thereof, and this gasket is for external connection. The multi-critical integrated circuit device of item 4 of the patent claim states that the second power supply line is connected to a cymbal formed on the substrate 'and this gasket is for external connection. 1 · The multi-critical MIS integrated circuit device of item 1 of Shen Qing's patent scope, its younger power supply line has a circuit formed in the periphery of the first and the second] Vfis transistor components. Power supply 8. The multi-critical MIS integrated circuit device according to item 1 of the scope of patent application, wherein the first power control line is connected to a gasket formed on the substrate thereof, and this gasket is for external connection. 9. The multi-critical MIS integrated circuit device according to item 1 of the scope of patent application, which 21 571395, applies the method of the scope of patent application 'the macro-frame of the t-macro of the t, outside:' and its -_ The transistor element is on the cloth along two edges of its macro frame. η. The first power supply line in the design of the multi-threshold integrated circuit of the patent scope item No. 1 is connected to a gasket formed on its substrate, and this gasket is for external connection. 14. The method for designing a multi-critical hall integrated circuit as described in item 1G of the patent, wherein the-power supply line has-formed in a pack of 10 including the-macro and the-MIS power Power supply ring in the periphery of the crystal element. 15 is placed on a rectangular shape, at least 15. The design method of a multi-critical recommended integrated circuit such as item 10 of the patent application scope, which further includes the steps of: arranging a second macro device and the first giant The collector includes a second internal circuit capable of supplying a control signal to its first power control line, and is connected to its second internal circuit and a pad formed on its substrate, the pad being provided for external use. For connection. twenty three
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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3986393B2 (en) * 2002-08-27 2007-10-03 富士通株式会社 Integrated circuit device having nonvolatile data storage circuit
US8553113B2 (en) * 2003-08-20 2013-10-08 At&T Intellectual Property I, L.P. Digital image capturing system and method
US6842714B1 (en) * 2003-08-22 2005-01-11 International Business Machines Corporation Method for determining the leakage power for an integrated circuit
US7590962B2 (en) * 2003-12-17 2009-09-15 Sequence Design, Inc. Design method and architecture for power gate switch placement
JP4200926B2 (en) 2004-03-10 2008-12-24 ソニー株式会社 Semiconductor integrated circuit
JP4765259B2 (en) * 2004-03-22 2011-09-07 ソニー株式会社 Semiconductor integrated circuit, design apparatus thereof, design method, and design program
JP2005268694A (en) * 2004-03-22 2005-09-29 Sony Corp Semiconductor integrated circuit and its manufacturing method
CN1950941A (en) * 2004-04-27 2007-04-18 皇家飞利浦电子股份有限公司 Integrated circuit layout for virtual power supply
US7279926B2 (en) * 2004-05-27 2007-10-09 Qualcomm Incoporated Headswitch and footswitch circuitry for power management
EP1638145A1 (en) 2004-09-20 2006-03-22 Infineon Technologies AG Embedded switchable power ring
JP4872264B2 (en) * 2005-08-04 2012-02-08 ソニー株式会社 Semiconductor integrated circuit, power switch cell, and circuit cell with power switch
JP4787592B2 (en) * 2005-10-14 2011-10-05 パナソニック株式会社 System LSI
JP2007266078A (en) * 2006-03-27 2007-10-11 Fujitsu Ltd Semiconductor device, semiconductor device of chip-on-chip structure, and process for manufacturing the semiconductor device
KR100780750B1 (en) * 2006-05-11 2007-11-30 한국과학기술원 Power Network Using Standard Cell and Power Gating Cell, and Semiconductor Device Using a Power Network
US8010317B1 (en) 2007-03-01 2011-08-30 National Semiconductor Corporation System and method for providing hardware performance monitors for adaptive voltage scaling with a plurality of VT logic libraries
JP5198785B2 (en) 2007-03-30 2013-05-15 ルネサスエレクトロニクス株式会社 Semiconductor device
US7868479B2 (en) * 2007-06-27 2011-01-11 Qualcomm Incorporated Power gating for multimedia processing power management
US7921312B1 (en) 2007-09-14 2011-04-05 National Semiconductor Corporation System and method for providing adaptive voltage scaling with multiple clock domains inside a single voltage domain
JP5528662B2 (en) 2007-09-18 2014-06-25 ソニー株式会社 Semiconductor integrated circuit
JP4636077B2 (en) 2007-11-07 2011-02-23 ソニー株式会社 Semiconductor integrated circuit
JP4535136B2 (en) 2008-01-17 2010-09-01 ソニー株式会社 Semiconductor integrated circuit and switch layout and wiring method
US20090224792A1 (en) * 2008-03-04 2009-09-10 International Business Machines Corporation Method to reduce test probe damage from excessive device leakage currents
JP5254093B2 (en) * 2009-03-19 2013-08-07 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit having power controllable region
JP2011114198A (en) * 2009-11-27 2011-06-09 Renesas Electronics Corp Primitive cell and semiconductor device
JP5565456B2 (en) * 2010-02-16 2014-08-06 株式会社デンソー Integrated circuit and method of using the same
US8289051B2 (en) * 2010-11-17 2012-10-16 Lsi Corporation Input/output core design and method of manufacture therefor
JP5549752B2 (en) * 2013-02-18 2014-07-16 ソニー株式会社 Semiconductor integrated circuit
KR102374846B1 (en) * 2015-12-14 2022-03-16 삼성전자주식회사 Method of modifying power mesh
KR102439700B1 (en) * 2018-01-11 2022-09-02 삼성전자주식회사 Semiconductor devices, methods of designing layouts of semiconductor devices and methods of manufacturing semiconductor devices

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2987532B2 (en) 1991-07-22 1999-12-06 ヤマハ発動機株式会社 Transmission control device for motorcycle
JP3112047B2 (en) 1991-11-08 2000-11-27 株式会社日立製作所 Semiconductor integrated circuit
KR100254134B1 (en) 1991-11-08 2000-04-15 나시모토 류우조오 Semiconductor integrated circuit having current reduction circuit in the standby state
JPH06350435A (en) 1993-06-02 1994-12-22 Nippon Telegr & Teleph Corp <Ntt> Power down circuit
JP3245663B2 (en) 1994-01-19 2002-01-15 日本電信電話株式会社 Logic circuit
US5633573A (en) * 1994-11-10 1997-05-27 Duracell, Inc. Battery pack having a processor controlled battery operating system
JPH10125878A (en) 1996-10-21 1998-05-15 Nippon Telegr & Teleph Corp <Ntt> Gate array
JPH10201093A (en) 1997-01-14 1998-07-31 Kawasaki Steel Corp Semiconductor device
US6016277A (en) * 1997-06-27 2000-01-18 Cypress Semiconductor Corporation Reference voltage generator for reading a ROM cell in an integrated RAM/ROM memory device
JPH11145397A (en) 1997-11-11 1999-05-28 Mitsubishi Electric Corp Semiconductor integrated circuit device
TW392307B (en) * 1998-01-13 2000-06-01 Mitsubishi Electric Corp A method of the manufacture and the setup of the semiconductor apparatus
JPH11306754A (en) 1998-04-15 1999-11-05 Nec Corp Semiconductor integrated circuit
WO1999054937A1 (en) * 1998-04-23 1999-10-28 Matsushita Electric Industrial Co., Ltd. Method of designing power supply circuit and semiconductor chip
JP3209972B2 (en) * 1999-01-14 2001-09-17 沖電気工業株式会社 Semiconductor integrated circuit device
WO2000065650A1 (en) * 1999-04-22 2000-11-02 Hitachi, Ltd. Semiconductor device and method of manufacture
JP2000323688A (en) 1999-05-07 2000-11-24 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device

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