JP2001127173A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen a semiconductor integrated circuit device in chip size by a method wherein I/O cells provided in the semiconductor integrated circuit device are reduced in dedicated area. SOLUTION: Boron and phosphorus are injected into the drain diffusion region 20a of a PMOS transistor 20 with pouring rates of 3×1015/cm2 and 3×1014 to 1.5×1015/cm2 respectively. Phosphorus and boron are injected into the drain diffusion region 22a of an NMOS transistor 22 with pouring rates of 6×1015/cm2 and 6×1014 to 3×1015/cm2 respectively. The drain diffusion regions 20a and 20b are enhanced in resistance/cm2 by injection of reverse conductivity impurities, so that a semiconductor integrated circuit device of this constitution can be protected against electrostatic breakdown even if a distance L' between a transistor gate 20c and a substrate contact 28 is lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having an I / O cell (input / output circuit cell) formed on a semiconductor chip and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the improvement of semiconductor manufacturing technology, a semiconductor device is required to have a large scale, a high integration, a large number of pins, a fine structure, and the like. FIG. 1 is a plan view showing an example of a semiconductor integrated circuit device. FIG. 2 is a plan view showing the configuration of the I / O cell region 4 in FIG. Although the chip layout of the semiconductor integrated circuit device varies depending on the product, it generally has a core 2 arranged at the center of the semiconductor chip and an I / O cell region 4 arranged so as to surround the core 2. (See FIG. 1). A bonding pad 6 and an I / O cell 8 are formed in the I / O cell region 4, and a MOS transistor as an input / output buffer is formed in the I / O cell 8 (see FIG. 2). Of the core 2 and the I / O cell 8, the core 2 can be relatively easily reduced in size by using a manufacturing process capable of forming a fine element.

[0003]

Since the I / O cells 8 are directly connected to the IC pins via the bonding pads 6, they receive external static electricity directly. It is necessary to provide a large-sized protection circuit. MO as I / O cell 8 input / output buffer
When a MOS transistor having the function of a protection circuit is used as the S transistor, it is necessary to increase the diffusion resistance value of the diffusion region (drain diffusion region) on the side connected to the bonding pad of the MOS transistor.

FIG. 3 is a plan view showing a configuration of a conventional I / O cell region 4. As shown in FIG. FIG. 4 is an equivalent circuit thereof. I /
The O cell 8 is configured by a CMOS inverter including four PMOS transistors (P-channel MOS transistors) 10 and four NMOS transistors (N-channel MOS transistors) 12.

The drain diffusion region 10a of the PMOS transistor 10 and the drain diffusion region 12a of the NMOS transistor 12
Is connected to the bonding pad 6 via the. P
The source diffusion region 10b of the MOS transistor 10 is connected to a power source 18 (omitted in FIG. 3) via a substrate contact 17.
It is connected to the. The source diffusion region 12b of the NMOS transistor 12 is connected to the GN through the substrate contact 19.
D (omitted in FIG. 3).

[0006] P-type impurities are implanted into the drain diffusion region 10a and the source diffusion region 10b at the same concentration, and the drain diffusion region 10a and the source diffusion region 10b have the same resistance value per unit area. Drain diffusion region 12
N-type impurities are implanted into a and the source diffusion region 12b at the same concentration, and the drain diffusion region 12a and the source diffusion region 12b have the same resistance value per unit area.

The transistor gate 10c of each PMOS transistor 10 and the transistor gate 12c of each NMOS transistor 12 are connected to each other. In this conventional example, the distance L between the transistor gates 10c and 12c and the substrate contact 14 is designed to be large, thereby increasing the diffusion resistance value of the drain diffusion regions 10a and 12a to prevent electrostatic breakdown. As mentioned above,
It is more difficult to reduce the space for arranging the I / O cell 8 than to reduce the space for the core 2, and in the worst case, the I / O cell 8 becomes a bottleneck to reduce the chip size. A situation arises in which it is not possible.

As means for solving the above-mentioned problem, Japanese Patent Laid-Open Publication No. Hei 6-232267 discloses a method of arranging divided basic cells outside each I / O cell and reducing the remaining area to reduce the number of I / O cells. By reducing the area occupied by the O cell, the area occupied by the I / O cell of the logic LSI is reduced, and
Although it is intended to facilitate the multi-pin structure of the I package, the cell size of the MOS transistor constituting the I / O cell is not reduced.

As another means, Japanese Patent Application Laid-Open No. 9-232507
In order to increase the density of an IC core and improve electrostatic withstand voltage, the core chip and the I / O chip are separated, and the core chip and the I / O chip are manufactured separately. Manufacturing process, core chip and I /
Although wire bonding is performed after an O chip is placed in an IC package, the cell size of a MOS transistor constituting the I / O chip has not been reduced.

Therefore, the present invention reduces the cell size of the MOS transistor of the input / output buffer and the protection circuit constituting the I / O cell, thereby reducing the area occupied by the I / O cell in the semiconductor integrated circuit device. It is an object of the present invention to reduce the chip size of a semiconductor integrated circuit device.

[0011]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having an input / output circuit constituted by MOS transistors, wherein the bonding pad is connected in the input / output circuit. The drain diffusion region of the transistor has a higher diffusion resistance value than the source diffusion region because the impurity concentration is controlled.

By increasing the diffusion resistance value of the drain diffusion region, the electrostatic breakdown voltage can be maintained even if the distance between the substrate contact connecting the drain diffusion region to the bonding pad and the transistor gate is reduced. . As a result, the MOS transistors can be arranged with a reduced cell size, the area occupied by the input / output circuits can be reduced, and the chip size of the semiconductor integrated circuit device can be reduced.

A first aspect of a method of manufacturing a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit having an input / output circuit configured by connecting a drain diffusion region of a MOS transistor to a bonding pad for external connection. A method of manufacturing a device, which includes the following steps (A) and (B) regardless of order. (A) a step of injecting a first conductivity type impurity into a region where a source / drain diffusion region of a first conductivity type MOS transistor is to be formed, and (B) an opening only in a drain diffusion region of a MOS transistor constituting an input / output circuit. Forming a resist pattern having the following characteristics, and using the mask as a mask to implant a second conductivity type impurity into the drain diffusion region.

A second aspect of the method for manufacturing a semiconductor integrated circuit device according to the present invention is directed to a semiconductor integrated circuit having an input / output circuit formed by connecting a drain diffusion region of a MOS transistor to a bonding pad for external connection. A method of manufacturing a device, which includes the following steps (A) and (B) regardless of order. (A) Of the regions where the source and drain diffusion regions of the first conductivity type MOS transistor are to be formed,
Forming a first resist pattern having an opening in a region other than a region where a drain diffusion region of a MOS transistor constituting an input / output circuit is to be formed, and using the mask as a mask to implant a first conductivity type impurity; A) forming a second resist pattern having an opening only in a region where a drain diffusion region of a MOS transistor constituting an input / output circuit is to be formed;
A step of injecting the first conductivity type impurity at a lower concentration than in the step (A) using the mask as a mask.

According to these manufacturing methods, the diffusion resistance value of the drain diffusion region connected to the bonding pad is determined by
The impurity concentration can be controlled to be larger than the source diffusion region, and the electrostatic breakdown voltage can be improved. By reducing the distance between the substrate contact connecting the drain diffusion region to the bonding pad and the transistor gate of the MOS transistor within the allowable range of the electrostatic withstand voltage, the MOS transistor can be arranged with a small cell size. , The occupied area of the input / output circuit can be reduced,
As a result, the chip size of the semiconductor integrated circuit device can be reduced.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A MOS transistor constituting an input / output circuit of a semiconductor integrated circuit according to the present invention comprises a PMOS transistor and an NMOS transistor, and
It is preferable to constitute a MOS inverter. M constituting the input / output circuit of the semiconductor integrated circuit of the present invention
Preferably, the OS transistor is a PMOS transistor. It is preferable that the MOS transistors constituting the input / output circuit of the semiconductor integrated circuit of the present invention are NMOS transistors.

In the first and second aspects of the method of manufacturing a semiconductor device according to the present invention, the step (A) includes the steps of: (B) is preferably performed for each of a P-channel MOS transistor and an N-channel MOS transistor.

[0018]

FIG. 5 is a plan view showing an I / O cell region of a semiconductor integrated circuit device as one embodiment. The configuration of the semiconductor integrated circuit device is the same as that of FIG. 1, and the configuration of the I / O cell region is the same as that of FIG. However, this embodiment does not limit the mode of the semiconductor integrated circuit device according to the present invention, and various changes can be made within the scope of the present invention described in the claims.

The I / O cell 8a is constituted by a CMOS inverter including four PMOS transistors 20 and four NMOS transistors 22. PMOS
Drain diffusion region 20a of transistor 20 and NMOS
The drain diffusion region 22a of the transistor 22 is connected to the bonding pad 6 via the substrate contact 24 and the metal wiring 26.

The source diffusion region 20b of the PMOS transistor 20 is connected to a power supply (not shown) via a substrate contact 27. NMOS transistor 22
The source diffusion region 22b is connected to GND (not shown) via the substrate contact 29. Each PMO
The transistor gate 20c of the S transistor 20 and the transistor gate 22c of each NMOS transistor 22
Are connected to each other. The transistor gate 20c,
22c is formed of, for example, polysilicon.

In the drain diffusion region 20a of the PMOS transistor 20, boron as a P-type impurity is 3 × 10
An implantation amount of ¹⁵ / cm ² and phosphorus as an N-type impurity are implanted at an implantation amount of 3 × 10 ^{14 to} 1.5 × 10 ¹⁵ / cm ² . In the drain diffusion region 20a, the resistance value per unit area is increased by implanting phosphorus as compared with the case where only boron is implanted. Boron as a P-type impurity is 3 × 10 3 in source diffusion region 20b.
It is implanted at a dose of ¹⁵ / cm ² .

The drain diffusion region 22a of the NMOS transistor 22 contains 6 × 10 ¹⁵ phosphorus as an N-type impurity.
In the injection amount of pieces / cm ^2, and boron as a P-type impurity is implanted at the amount of 6 × 10 ¹⁴ ~3 × 10 ¹⁵ pieces / cm ^2. In the drain diffusion region 22a, the resistance value per unit area is increased by implanting boron as compared with the case where only phosphorus is implanted. Phosphorus as an N-type impurity is 6 × 10 ¹⁵ /
It is implanted at a dose of cm ² .

In the drain diffusion regions 20a and 22a, the resistance per unit area is increased by implanting impurities of the opposite conductivity type. Drain diffusion region 10
Even if the distance L 'between the transistor gate 20c and the substrate contact 28 is smaller than that of the transistors a and 12a, electrostatic breakdown can be prevented. Drain diffusion regions 20a, 2
The amount of the impurity of the opposite conductivity type implanted into 2a is preferably one-tenth to one-half of the impurity of the original conductivity type.

By reducing the distance L 'within the allowable range of the electrostatic withstand voltage of the drain diffusion regions 20a and 22a,
The MOS transistors 20 and 22 can be arranged with a reduced cell size, the I / O cell 8a can be reduced, and the semiconductor chip area can be reduced. Further, as the chip area is reduced, the number of chips per wafer is increased, and the yield is improved, so that the production cost per chip can be reduced.

The method of manufacturing a semiconductor integrated circuit device for forming the I / O cell shown in FIG. 5 is described as an example (manufacturing method 1) of the first embodiment of the method of manufacturing a semiconductor integrated circuit device according to the present invention. This will be described with reference to FIGS. However, the embodiments of the manufacturing method described below do not limit the manufacturing method of the semiconductor integrated circuit device according to the present invention, and various modifications can be made within the scope of the claims.

(Manufacturing Method 1) (A) On a semiconductor substrate, a region where a drain diffusion region 20a of a PMOS transistor 20 is to be formed, a region where a source diffusion region 20b is to be formed, and a PMOS which forms a core 2
A first resist pattern having an opening in a region where a diffusion region of a transistor is to be formed is formed. Using the first resist pattern as a mask, a region where a drain diffusion region 20a is to be formed, a region where a source diffusion region 20b is to be formed, and a PMO constituting a core 2 of the PMOS transistor 20 are formed.
Boron is implanted into a region where the diffusion region of the S transistor is to be formed.

(B) After removing the first resist pattern, a second resist pattern having an opening only in the drain diffusion region 20a is formed on the semiconductor substrate. The second
Using the resist pattern as a mask, phosphorus is implanted into the drain diffusion region 20a.

(C) After removing the second resist pattern, a region where the drain diffusion region 22a of the NMOS transistor 22 is to be formed and the source diffusion region 2 are formed on the semiconductor substrate.
3b having an opening in the formation region of the NMOS transistor constituting the core 2b and the formation region of the diffusion region of the NMOS transistor forming the core 2.
Is formed. Using the third resist pattern as a mask, a region where the drain diffusion region 22a is to be formed, a region where the source diffusion region 22b is to be formed, and the NMOS that constitutes the core 2 of the NMOS transistor 22
Phosphorus is implanted into a region where a transistor diffusion region is to be formed. (D) After removing the third resist pattern, a fourth resist pattern having an opening only in the drain diffusion region 22a is formed on the semiconductor substrate.
Is formed. Using the fourth resist pattern as a mask, boron is implanted into the drain diffusion region 22a. (E) After removing the fourth resist pattern, the transistor gate 20c, the interlayer insulating film, the substrate contact 27,
28 and 29 are formed, and the bonding pad 6 and the metal wiring 26 are further formed.

Another method for manufacturing a semiconductor integrated circuit device for forming the I / O cell shown in FIG. 5 is described in another embodiment of the first embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention (manufacturing method 2). ) Will be described with reference to FIGS.

(Manufacturing Method 2) (A) A first resist pattern having an opening only in the drain diffusion region 20a is formed on a semiconductor substrate. Using the first resist pattern as a mask, phosphorus is implanted into the drain diffusion region 20a. (B) After removing the first resist pattern, the diffusion region of the PMOS transistor constituting the drain diffusion region 20a, the source diffusion region 20b, and the core 2 of the PMOS transistor 20 is formed on the semiconductor substrate. A second resist pattern having an opening in a region where a region is to be formed is formed. Using the second resist pattern as a mask, boron is added to the region where the drain diffusion region 20a of the PMOS transistor 20 is to be formed, the region where the source diffusion region 20b is to be formed, and the region where the diffusion region of the PMOS transistor constituting the core 2 is to be formed. Inject.

(C) After removing the second resist pattern, a third resist pattern having an opening only in the drain diffusion region 22a is formed on the semiconductor substrate. The third
Using the resist pattern as a mask, boron is implanted into the drain diffusion region 22a. (D) After removing the third resist pattern, the diffusion region of the NMOS transistor 22, the region where the drain diffusion region 22 a is to be formed, the source diffusion region 22 b, and the NMOS transistor forming the core 2 are formed on the semiconductor substrate. A fourth resist pattern having an opening in a region where a region is to be formed is formed. Using the fourth resist pattern as a mask, phosphorous is added to the region where the drain diffusion region 22a of the NMOS transistor 22 is to be formed, the region where the source diffusion region 22b is to be formed, and the region where the diffusion region of the NMOS transistor forming the core 2 is to be formed. Inject. (E) After removing the fourth resist pattern, the transistor gate 20c, the interlayer insulating film, the substrate contact 27,
28 and 29 are formed, and the bonding pad 6 and the metal wiring 26 are further formed.

In the embodiment shown in FIG. 5, as means for increasing the diffusion resistance value of the drain diffusion regions 20a, 22a as compared with other diffusion regions including the source diffusion regions 20b, 22b, the drain diffusion regions 20a, 22a A method of reducing the impurity concentration may be used. In this case, it is not necessary to implant the impurity of the opposite conductivity type into the drain diffusion regions 20a and 22a.

According to the present invention, a method of manufacturing a semiconductor integrated circuit device for forming such an I / O cell having the drain diffusion regions 20a and 22a into which only one type of impurity is implanted (manufacturing method 3) is provided according to the present invention. An example of the second embodiment of the method for manufacturing a semiconductor integrated circuit device will be described with reference to FIGS.

(Manufacturing Method 3) (A) A first region having an opening in a region where a source diffusion region 20b of a PMOS transistor 20 is to be formed and a region where a diffusion region of a PMOS transistor forming a core 2 is to be formed are formed on a semiconductor substrate. Is formed. Using the first resist pattern as a mask, a region where a source diffusion region 20b is to be formed, and a PMOS that forms the core 2
Boron is implanted into a region where a diffusion region of a transistor is to be formed, so that a source diffusion region 20 b and P
A diffusion region of a MOS transistor is formed.

(B) After removing the first resist pattern, a second resist pattern having an opening only in a region where the drain diffusion region 20a is to be formed is formed on the semiconductor substrate. Using the second resist pattern as a mask, the drain diffusion region 2b and the drain diffusion region 2b have a lower concentration than the diffusion region of the PMOS transistor forming the core 2.
Boron is implanted into the region where Oa is to be formed to form a drain diffusion region 20a. Thereby, the diffusion resistance value of the drain diffusion region 20a is made larger than the diffusion resistance values of the diffusion region of the source diffusion region 20b and the diffusion region of the PMOS transistor forming the core 2.

(C) After the removal of the second resist pattern, a region where the source diffusion region 22b of the NMOS transistor 22 is to be formed and a region where the diffusion region of the NMOS transistor forming the core 2 is to be formed are formed on the semiconductor substrate. A third resist pattern having an opening is formed. The third
Using the resist pattern as a mask, the source diffusion region 2
2b and the diffusion region of the NMOS transistor forming the core 2 are implanted with phosphorus to form the source diffusion region 22b and the NM forming the core 2.
A diffusion region of the OS transistor is formed.

(D) After removing the third resist pattern, a fourth resist pattern having an opening only in a region where the drain diffusion region 22a is to be formed is formed. Using the fourth resist pattern as a mask, source diffusion region 22b
Then, phosphorus is implanted into the region where the drain diffusion region 22a is to be formed at a concentration lower than that of the diffusion region of the NMOS transistor forming the core 2, thereby forming the drain diffusion region 22a. As a result, the diffusion resistance value of the drain diffusion region 22a is reduced by the PM forming the source diffusion region 22b and the core 2.
The diffusion resistance is made larger than the diffusion resistance value of the diffusion region of the OS transistor. (E) After removing the fourth resist pattern, the transistor gate 20c, the interlayer insulating film, the substrate contact 27,
28 and 29 are formed, and the bonding pad 6 and the metal wiring 26 are further formed.

Another method for manufacturing a semiconductor integrated circuit device in which the drain diffusion regions 20a and 22a into which only one type of impurity is implanted is different from the second embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention. An example (manufacturing method 4) will be described with reference to FIGS.

(Manufacturing Method 4) (A) A first resist pattern having an opening only in a region where a drain diffusion region 20a of a PMOS transistor 20 is to be formed is formed on a semiconductor substrate. Using the first resist pattern as a mask, boron is implanted into a region where the drain diffusion region 20a is to be formed at a lower concentration than in the next step (B) to form the drain diffusion region 20a. (B) After removing the first resist pattern, a second resist pattern having an opening in the semiconductor substrate on which the source diffusion region 20b is to be formed and the diffusion region of the PMOS transistor forming the core 2 is to be formed To form By using the second resist pattern as a mask, boron is implanted into the region where the source diffusion region 20b is to be formed and the region where the diffusion region of the PMOS transistor forming the core 2 is to be formed at a higher concentration than the drain diffusion region 20a. , PMO forming source diffusion region 20b and core 2
A diffusion region of the S transistor is formed. by this,
The diffusion resistance value of the drain diffusion region 20a is made larger than that of the source diffusion region 20b and the diffusion region of the PMOS transistor forming the core 2.

(C) After removing the third resist pattern, a third resist pattern having an opening only in a region where the drain diffusion region 22a of the NMOS transistor 22 is to be formed is formed on the semiconductor substrate. Using the third resist pattern as a mask, phosphorus is implanted into a region where the drain diffusion region 22a is to be formed at a lower concentration than in the next step (D) to form the drain diffusion region 22a.

(D) After removing the third resist pattern, a fourth region having an opening in the region where the source diffusion region 22b is to be formed and the region where the diffusion region of the PMOS transistor forming the core 2 is to be formed are formed on the semiconductor substrate. Is formed. Using the fourth resist pattern as a mask, a region where the source diffusion region 22b is to be formed and the core 2
Is implanted at a higher concentration than the drain diffusion region 22a into the region where the diffusion region of the PMOS transistor constituting the PMOS transistor is formed, thereby forming the diffusion region of the PMOS transistor constituting the source diffusion region 22b and the core 2. As a result, the diffusion resistance value of the drain diffusion region 22a is made larger than that of the PMOS transistor constituting the source diffusion region 22b and the core 2. (E) After removing the fourth resist pattern, the transistor gate 20c, the interlayer insulating film, the substrate contact 27,
28 and 29 are formed, and the bonding pad 6 and the metal wiring 26 are further formed.

In the above-described embodiment of the method of manufacturing a semiconductor integrated circuit device, after the diffusion region of the PMOS transistor is formed, the diffusion region of the NMOS transistor is formed. However, the present invention is not limited to this. Instead, for example, after forming the diffusion region of the NMOS transistor, P
PMO such as forming diffusion region of MOS transistor
The order in which the diffusion regions of the S transistor and the NMOS transistor are formed may be any order.

In the above-described embodiments of the semiconductor integrated circuit device and the method of manufacturing the same, a CMOS inverter is used as an I / O cell. However, the present invention is not limited to this. NMOS
The present invention can also be applied to a semiconductor integrated circuit device in which an I / O cell including only a transistor is arranged and a method of manufacturing the same.

[0044]

According to the semiconductor integrated circuit device of the present invention, the drain diffusion region of the MOS transistor to which the bonding pad is connected in the input / output circuit is controlled in impurity concentration and has a higher diffusion resistance than the source diffusion region. Since the value is made large, the distance between the substrate contact connecting the drain diffusion region to the bonding pad and the transistor gate of the MOS transistor can be formed small,
The OS transistor can be arranged with a small cell size, the area occupied by the input / output circuit can be reduced, and the chip size of the semiconductor integrated circuit device can be reduced.

In the method of manufacturing a semiconductor integrated circuit device according to claim 5 or 7, a step of implanting a first conductivity type impurity into a region where a source / drain diffusion region of a first conductivity type MOS transistor is to be formed (A). And a resist pattern having an opening only in the drain diffusion region of the MOS transistor constituting the input / output circuit, and using this as a mask,
Since the step (B) of injecting impurities of the second conductivity type into the drain diffusion region is performed regardless of the order, the diffusion resistance value of the drain diffusion region connected to the bonding pad is controlled by controlling the impurity concentration. It can be made larger than the source diffusion region to improve the electrostatic withstand voltage. Within the allowable range of the electrostatic withstand voltage, the distance between the substrate contact connecting the drain diffusion region to the bonding pad and the transistor gate of the MOS transistor can be increased. By making it smaller,
The MOS transistor can be arranged with a small cell size, the area occupied by the input / output circuit can be reduced, and the chip size of the semiconductor integrated circuit device can be reduced.

In the method of manufacturing a semiconductor integrated circuit device according to the sixth or seventh aspect, the drain diffusion region of the MOS transistor constituting the input / output circuit is formed in the region where the source / drain diffusion region of the first conductivity type MOS transistor is to be formed. Forming a first resist pattern having an opening in a region other than a region where a region is to be formed, using the mask as a mask to implant a first conductivity type impurity (A), A step (B) of forming a second resist pattern having an opening only in a region where a drain diffusion region is to be formed and using the mask as a mask to inject a first conductivity type impurity at a lower concentration than the step (A) is performed. The diffusion resistance value of the drain diffusion region connected to the bonding pad is controlled by controlling the impurity concentration. Can also improve the electrostatic withstand voltage was increased, within a tolerance of the electrostatic breakdown voltage, a substrate contact for connecting the drain diffusion region to the bonding pad,
By reducing the distance between the MOS transistor and the transistor gate, the cell size of the MOS transistor can be reduced, and the area occupied by the input / output circuit can be reduced, and the chip size of the semiconductor integrated circuit device can be reduced. .

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a semiconductor integrated circuit device.

FIG. 2 is a plan view showing a configuration of an I / O cell region 4 of FIG.

FIG. 3 is a plan view showing a configuration of a conventional I / O cell region 4.

FIG. 4 is an equivalent circuit of the I / O cell region shown in FIG.

FIG. 5 shows an I / O of a semiconductor integrated circuit device as one embodiment.
It is a top view which shows an O cell area.

[Explanation of symbols]

2 Core chip 4 I / O cell area 6 Bonding pad 8, 8a I / O cell 10, 20 P channel type MOS transistor 10a, 20a Drain diffusion area 10b, 20b Source diffusion area 10c, 20c Transistor gate 12, 22 P channel type MOS Transistors 12a, 22a Drain diffusion regions 12b, 22b Source diffusion regions 12c, 22c Transistor gates 14, 17, 19, 24, 27, 29 Substrate contacts 16, 26 Metal wiring 18 Power supply

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 BE07 BH07 BH13 EZ13 EZ20 5F040 DA24 DB03 DB10 DC01 EF11 EF18 EM01 EM03 FC11 5F048 AA01 AA02 AB02 AB04 AB06 AB07 AC03 BB01 BB05 BC03 BC20 CC01 CC02 CC09 CC13 CC15 CC16

Claims (7)

[Claims] 1. A semiconductor integrated circuit device having an input / output circuit composed of MOS transistors, wherein the M is connected to a bonding pad in the input / output circuit.
A semiconductor integrated circuit device, wherein a drain diffusion region of an OS transistor has a higher diffusion resistance value than a source diffusion region by controlling an impurity concentration. 2. The semiconductor integrated circuit according to claim 1, further comprising a P-channel MOS transistor and an N-channel MOS transistor as said MOS transistors, wherein said input / output circuit forms a CMOS inverter. 3. The semiconductor integrated circuit according to claim 1, wherein said MOS transistor is a P-channel MOS transistor. 4. The semiconductor integrated circuit according to claim 1, wherein said MOS transistor is an N-channel MOS transistor. 5. A method of manufacturing a semiconductor integrated circuit device having an input / output circuit configured by connecting a drain diffusion region of a MOS transistor to a bonding pad for external connection, comprising the following steps (A) and (B). Irrespective of the order of the semiconductor integrated circuit device. (A) a step of injecting a first conductivity type impurity into a region where a source / drain diffusion region of a first conductivity type MOS transistor is to be formed; and (B) an opening only in a drain diffusion region of a MOS transistor constituting an input / output circuit. Forming a resist pattern having
A step of implanting impurities of a conductivity type; 6. A method of manufacturing a semiconductor integrated circuit device having an input / output circuit configured by connecting a drain diffusion region of a MOS transistor to a bonding pad for external connection, comprising the following steps (A) and (B). Irrespective of the order of the semiconductor integrated circuit device. (A) A first resist having an opening in a region where a source / drain diffusion region of a first conductivity type MOS transistor is to be formed, except for a region where a drain diffusion region of a MOS transistor constituting an input / output circuit is to be formed. Forming a pattern and using the mask as a mask to implant a first conductivity type impurity; (B) a second resist pattern having an opening only in a region where a drain diffusion region of a MOS transistor constituting an input / output circuit is to be formed And implanting the first conductivity type impurity at a lower concentration than in the step (A) using the mask as a mask. 7. A P-channel MOS transistor and an N-channel MOS transistor as MOS transistors for an input / output circuit.
The steps (A) and (B) including an S-transistor and a P-channel MOS transistor and an N-channel MOS transistor
7. The method for manufacturing a semiconductor integrated circuit according to claim 5, wherein the method is performed for each of the transistors.