TW571206B - Automated processor generation system for designing a configurable processor and method for the same - Google Patents

Automated processor generation system for designing a configurable processor and method for the same Download PDF

Info

Publication number
TW571206B
TW571206B TW090103671A TW90103671A TW571206B TW 571206 B TW571206 B TW 571206B TW 090103671 A TW090103671 A TW 090103671A TW 90103671 A TW90103671 A TW 90103671A TW 571206 B TW571206 B TW 571206B
Authority
TW
Taiwan
Prior art keywords
processor
instruction
register
instructions
tie
Prior art date
Application number
TW090103671A
Other languages
English (en)
Chinese (zh)
Inventor
Albert R Wang
Richard Ruddell
David W Goodwin
Earl A Killian
Rangarajan Srinivasan
Original Assignee
Tensilica Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tensilica Inc filed Critical Tensilica Inc
Application granted granted Critical
Publication of TW571206B publication Critical patent/TW571206B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Stored Programmes (AREA)
  • Devices For Executing Special Programs (AREA)
TW090103671A 2000-02-17 2001-05-11 Automated processor generation system for designing a configurable processor and method for the same TW571206B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/506,502 US7036106B1 (en) 2000-02-17 2000-02-17 Automated processor generation system for designing a configurable processor and method for the same

Publications (1)

Publication Number Publication Date
TW571206B true TW571206B (en) 2004-01-11

Family

ID=24014856

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090103671A TW571206B (en) 2000-02-17 2001-05-11 Automated processor generation system for designing a configurable processor and method for the same

Country Status (8)

Country Link
US (4) US7036106B1 (ko)
JP (1) JP4619606B2 (ko)
KR (1) KR100589744B1 (ko)
CN (1) CN1288585C (ko)
AU (1) AU2001238403A1 (ko)
GB (1) GB2376546B (ko)
TW (1) TW571206B (ko)
WO (1) WO2001061576A2 (ko)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381309B (en) * 2006-11-21 2013-01-01 Nec Corp Instruction operation code generation system
TWI406148B (zh) * 2008-11-14 2013-08-21 Synopsys Inc 提供在多取樣率系統摺疊中的展開演算法之方法、非暫時之機器可讀媒體及資料處理系統
TWI481992B (zh) * 2011-03-25 2015-04-21 Intel Corp 位準移位資料信號的方法與使用該方法的積體電路及系統
TWI505636B (zh) * 2012-04-10 2015-10-21 Univ Lunghwa Sci & Technology 具有最佳多重取樣率之有限脈衝濾波器及其製造方法
TWI507990B (zh) * 2011-01-24 2015-11-11 Nat Univ Tsing Hua 多核心指令集模擬之高平行化同步方法

Families Citing this family (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1378665A (zh) 1999-06-10 2002-11-06 Pact信息技术有限公司 编程概念
WO2001069411A2 (en) * 2000-03-10 2001-09-20 Arc International Plc Memory interface and method of interfacing between functional entities
FR2811093A1 (fr) * 2000-06-30 2002-01-04 St Microelectronics Sa Dispositif et procede d'evaluation d'algorithmes
DE10034869A1 (de) * 2000-07-18 2002-02-07 Siemens Ag Verfahren zum automatischen Gewinnen einer funktionsfähigen Reihenfolge von Prozessen und Werkzeug hierzu
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
GB0028079D0 (en) * 2000-11-17 2001-01-03 Imperial College System and method
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9411532B2 (en) 2001-09-07 2016-08-09 Pact Xpp Technologies Ag Methods and systems for transferring data between a processing device and external devices
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US6941548B2 (en) 2001-10-16 2005-09-06 Tensilica, Inc. Automatic instruction set architecture generation
DE10305584A1 (de) * 2002-02-04 2003-08-07 Arthrex Inc Knotenschieber und Fadengreifer
DE10205523A1 (de) * 2002-02-08 2003-08-28 Systemonic Ag Verfahren zum Bereitstellen einer Entwurfs-, Test- und Entwicklungsumgebung sowie ein System zur Ausführung des Verfahrens
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
JP2003316838A (ja) * 2002-04-19 2003-11-07 Nec Electronics Corp システムlsiの設計方法及びこれを記憶した記録媒体
JP4202673B2 (ja) * 2002-04-26 2008-12-24 株式会社東芝 システムlsi開発環境生成方法及びそのプログラム
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7346881B2 (en) 2002-05-13 2008-03-18 Tensilica, Inc. Method and apparatus for adding advanced instructions in an extensible processor architecture
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
GB0215033D0 (en) * 2002-06-28 2002-08-07 Critical Blue Ltd Instruction set translation method
GB0215034D0 (en) * 2002-06-28 2002-08-07 Critical Blue Ltd Architecture generation method
FR2843214B1 (fr) * 2002-07-30 2008-07-04 Bull Sa Procede de verification fonctionnelle d'un modele de circuit integre pour constituer une plate-forme de verification, equipement emulateur et plate-forme de verification.
EP1537486A1 (de) 2002-09-06 2005-06-08 PACT XPP Technologies AG Rekonfigurierbare sequenzerstruktur
US7228531B1 (en) * 2003-02-03 2007-06-05 Altera Corporation Methods and apparatus for optimizing a processor core on a programmable chip
US7305391B2 (en) * 2003-02-07 2007-12-04 Safenet, Inc. System and method for determining the start of a match of a regular expression
US7194705B1 (en) * 2003-03-14 2007-03-20 Xilinx, Inc. Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions
ATE409904T1 (de) * 2003-04-09 2008-10-15 Jaluna Sa Betriebssysteme
US8612992B2 (en) * 2003-04-09 2013-12-17 Jaluna Sa Operating systems
EP1503286B1 (en) * 2003-07-30 2014-09-03 Jaluna SA Multiple operating system networking
KR20070005917A (ko) * 2003-09-30 2007-01-10 쟈루나 에스에이 운영체제
US7290174B1 (en) * 2003-12-03 2007-10-30 Altera Corporation Methods and apparatus for generating test instruction sequences
US7770147B1 (en) * 2004-03-08 2010-08-03 Adaptec, Inc. Automatic generators for verilog programming
US20050216900A1 (en) * 2004-03-29 2005-09-29 Xiaohua Shi Instruction scheduling
US7398492B2 (en) 2004-06-03 2008-07-08 Lsi Corporation Rules and directives for validating correct data used in the design of semiconductor products
US7404156B2 (en) * 2004-06-03 2008-07-22 Lsi Corporation Language and templates for use in the design of semiconductor products
US7334201B1 (en) * 2004-07-02 2008-02-19 Tensilica, Inc. Method and apparatus to measure hardware cost of adding complex instruction extensions to a processor
US7324106B1 (en) * 2004-07-27 2008-01-29 Nvidia Corporation Translation of register-combiner state into shader microcode
US7389490B2 (en) * 2004-07-29 2008-06-17 International Business Machines Corporation Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities
US7386825B2 (en) 2004-07-29 2008-06-10 International Business Machines Corporation Method, system and program product supporting presentation of a simulated or hardware system including configuration entities
EP1806847B1 (en) * 2004-10-28 2010-02-17 IP Flex Inc. Data processing device having reconfigurable logic circuit
CN100389419C (zh) * 2004-12-11 2008-05-21 鸿富锦精密工业(深圳)有限公司 系统设定档案储存系统及方法
US7664928B1 (en) * 2005-01-19 2010-02-16 Tensilica, Inc. Method and apparatus for providing user-defined interfaces for a configurable processor
US7712081B2 (en) * 2005-01-19 2010-05-04 International Business Machines Corporation Using code motion and write and read delays to increase the probability of bug detection in concurrent systems
US7386814B1 (en) * 2005-02-10 2008-06-10 Xilinx, Inc. Translation of high-level circuit design blocks into hardware description language
JP4342464B2 (ja) * 2005-03-29 2009-10-14 富士通マイクロエレクトロニクス株式会社 マイクロコントローラ
JP2009505171A (ja) * 2005-06-27 2009-02-05 イコア コーポレイション ステートフルなトランザクション指向のシステムを指定する方法、及び半導体デバイスの構造的に構成可能なイン・メモリ処理へ柔軟にマッピングする装置
DE102005041312A1 (de) * 2005-08-31 2007-03-15 Advanced Micro Devices, Inc., Sunnyvale Speicherzugriff auf virtuelles Targetgerät
US7523434B1 (en) * 2005-09-23 2009-04-21 Xilinx, Inc. Interfacing with a dynamically configurable arithmetic unit
US20070074078A1 (en) * 2005-09-23 2007-03-29 Potts Matthew P Test replication through revision control linking
US7478356B1 (en) * 2005-09-30 2009-01-13 Xilinx, Inc. Timing driven logic block configuration
US7366998B1 (en) * 2005-11-08 2008-04-29 Xilinx, Inc. Efficient communication of data between blocks in a high level modeling system
JP2009524134A (ja) * 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト ハードウェア定義方法
US7757224B2 (en) 2006-02-02 2010-07-13 Microsoft Corporation Software support for dynamically extensible processors
JP2007272797A (ja) * 2006-03-31 2007-10-18 Toshiba Corp パイプライン高位合成システム及び方法
US7827517B1 (en) * 2006-05-19 2010-11-02 Altera Corporation Automated register definition, builder and integration framework
JP4707191B2 (ja) * 2006-09-26 2011-06-22 富士通株式会社 検証支援プログラム、該プログラムを記録した記録媒体、検証支援装置、および検証支援方法
US7529909B2 (en) * 2006-12-28 2009-05-05 Microsoft Corporation Security verified reconfiguration of execution datapath in extensible microcomputer
US7971132B2 (en) * 2007-01-05 2011-06-28 Dialogic Corporation Universal multimedia engine and method for producing the same
JP2008176453A (ja) * 2007-01-17 2008-07-31 Nec Electronics Corp シミュレーション装置
US8726241B1 (en) * 2007-06-06 2014-05-13 Rockwell Collins, Inc. Method and system for the development of high-assurance computing elements
US7873934B1 (en) 2007-11-23 2011-01-18 Altera Corporation Method and apparatus for implementing carry chains on field programmable gate array devices
US7913203B1 (en) 2007-11-23 2011-03-22 Altera Corporation Method and apparatus for designing a system on multiple field programmable gate array device types
US8176406B2 (en) * 2008-03-19 2012-05-08 International Business Machines Corporation Hard error detection
US7974967B2 (en) * 2008-04-15 2011-07-05 Sap Ag Hybrid database system using runtime reconfigurable hardware
US8429472B2 (en) * 2008-08-20 2013-04-23 National University Corporation Kyushu University Institute of Technology Generating device, generating method, and program
US8843862B2 (en) * 2008-12-16 2014-09-23 Synopsys, Inc. Method and apparatus for creating and changing logic representations in a logic design using arithmetic flexibility of numeric formats for data
US8127262B1 (en) * 2008-12-18 2012-02-28 Xilinx, Inc. Communicating state data between stages of pipelined packet processor
KR101553652B1 (ko) * 2009-02-18 2015-09-16 삼성전자 주식회사 이종 프로세서에 대한 명령어 컴파일링 장치 및 방법
EP2473918B1 (en) * 2009-09-04 2019-05-08 Intel Corporation Method for generating a set of instruction compaction schemes, method for compacting a program according to the generated set, and programmable processor capable of executing a program thus compacted
US8156459B1 (en) * 2009-11-10 2012-04-10 Xilinx, Inc. Detecting differences between high level block diagram models
US8548798B2 (en) * 2010-02-26 2013-10-01 International Business Machines Corporation Representations for graphical user interfaces of operators, data types, and data values in a plurality of natural languages
US8972953B2 (en) * 2010-04-16 2015-03-03 Salesforce.Com, Inc. Methods and systems for internally debugging code in an on-demand service environment
US8839214B2 (en) * 2010-06-30 2014-09-16 Microsoft Corporation Indexable type transformations
US8358653B1 (en) * 2010-08-17 2013-01-22 Xilinx, Inc. Generating a pipeline of a packet processor from a parsing tree
US8385340B1 (en) * 2010-08-17 2013-02-26 Xilinx, Inc. Pipeline of a packet processor programmed to concurrently perform operations
JP2012099035A (ja) * 2010-11-05 2012-05-24 Fujitsu Ltd プロセッサの動作検証方法、プロセッサの動作検証装置、及びプロセッサの動作検証プログラム
CN102567149B (zh) * 2010-12-09 2016-03-23 上海华虹集成电路有限责任公司 Soc系统验证方法
US8392866B2 (en) * 2010-12-20 2013-03-05 International Business Machines Corporation Task-based multi-process design synthesis with notification of transform signatures
US8341565B2 (en) 2010-12-20 2012-12-25 International Business Machines Corporation Task-based multi-process design synthesis with reproducible transforms
US8407652B2 (en) 2010-12-20 2013-03-26 International Business Machines Corporation Task-based multi-process design synthesis
US8707266B2 (en) * 2011-03-21 2014-04-22 Cisco Technology, Inc. Command line interface robustness testing
CN102521011B (zh) * 2011-11-18 2014-08-06 华为技术有限公司 一种模拟器的生成方法及装置
CN103543983B (zh) * 2012-07-11 2016-08-24 世意法(北京)半导体研发有限责任公司 用于提高平衡吞吐量数据路径架构上的fir操作性能的新颖数据访问方法
GB2508233A (en) 2012-11-27 2014-05-28 Ibm Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design
US9696998B2 (en) * 2013-08-29 2017-07-04 Advanced Micro Devices, Inc. Programmable substitutions for microcode
US9811335B1 (en) 2013-10-14 2017-11-07 Quicklogic Corporation Assigning operational codes to lists of values of control signals selected from a processor design based on end-user software
US9336072B2 (en) * 2014-02-07 2016-05-10 Ralph Moore Event group extensions, systems, and methods
US9660650B1 (en) * 2014-03-13 2017-05-23 Altera Corporation Integrated circuits with improved register circuitry
US9268597B2 (en) * 2014-04-01 2016-02-23 Google Inc. Incremental parallel processing of data
JP2017525272A (ja) * 2014-07-07 2017-08-31 トムソン ライセンシングThomson Licensing メタデータに従ったビデオコンテンツの拡張
CN105279062A (zh) * 2014-07-24 2016-01-27 上海华虹集成电路有限责任公司 调整随机权重的方法
US9250900B1 (en) 2014-10-01 2016-02-02 Cadence Design Systems, Inc. Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network
US10528443B2 (en) * 2015-01-30 2020-01-07 Samsung Electronics Co., Ltd. Validation of multiprocessor hardware component
US9507891B1 (en) 2015-05-29 2016-11-29 International Business Machines Corporation Automating a microarchitecture design exploration environment
US10642617B2 (en) * 2015-12-08 2020-05-05 Via Alliance Semiconductor Co., Ltd. Processor with an expandable instruction set architecture for dynamically configuring execution resources
US9542290B1 (en) 2016-01-29 2017-01-10 International Business Machines Corporation Replicating test case data into a cache with non-naturally aligned data boundaries
CN105912264A (zh) * 2016-04-01 2016-08-31 浪潮电子信息产业股份有限公司 一种升级硬盘扩展器的方法及系统、一种硬盘扩展器
US10169180B2 (en) 2016-05-11 2019-01-01 International Business Machines Corporation Replicating test code and test data into a cache with non-naturally aligned data boundaries
US10055320B2 (en) 2016-07-12 2018-08-21 International Business Machines Corporation Replicating test case data into a cache and cache inhibited memory
US10223225B2 (en) 2016-11-07 2019-03-05 International Business Machines Corporation Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries
US10261878B2 (en) 2017-03-14 2019-04-16 International Business Machines Corporation Stress testing a processor memory with a link stack
CN108920232B (zh) * 2018-06-20 2021-06-22 维沃移动通信有限公司 一种目标对象的处理方法及终端设备
CN109101239B (zh) * 2018-08-30 2021-09-14 杭州电子科技大学 一种在线Verilog代码自动判决系统的标准答案生成方法
CN111814093A (zh) * 2019-04-12 2020-10-23 杭州中天微系统有限公司 一种乘累加指令的处理方法和处理装置
CN111523283B (zh) * 2020-04-16 2023-05-26 北京百度网讯科技有限公司 一种验证处理器的方法、装置、电子设备及存储介质
US11662988B2 (en) * 2020-09-29 2023-05-30 Shenzhen GOODIX Technology Co., Ltd. Compiler for RISC processor having specialized registers
TWI783310B (zh) * 2020-11-26 2022-11-11 華邦電子股份有限公司 計數方法以及計數裝置
CN113392603B (zh) * 2021-08-16 2022-02-18 北京芯愿景软件技术股份有限公司 门级电路的rtl代码生成方法、装置和电子设备

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5867399A (en) 1990-04-06 1999-02-02 Lsi Logic Corporation System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description
US5623418A (en) 1990-04-06 1997-04-22 Lsi Logic Corporation System and method for creating and validating structural description of electronic system
US5555201A (en) 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5572437A (en) 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US5544067A (en) 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5613098A (en) 1991-03-07 1997-03-18 Digital Equipment Corporation Testing and debugging new Y architecture code on existing X architecture system by using an environment manager to switch between direct X code execution and simulated Y code execution
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5918035A (en) 1995-05-15 1999-06-29 Imec Vzw Method for processor modeling in code generation and instruction set simulation
EP0772140B1 (en) 1995-10-23 2004-01-07 Interuniversitair Micro-Elektronica Centrum Vzw A design environment and a design method for hardware/software co-design
US5696956A (en) 1995-11-08 1997-12-09 Digital Equipment Corporation Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents
US6035123A (en) 1995-11-08 2000-03-07 Digital Equipment Corporation Determining hardware complexity of software operations
US5819064A (en) 1995-11-08 1998-10-06 President And Fellows Of Harvard College Hardware extraction technique for programmable reduced instruction set computers
US5887169A (en) 1996-03-15 1999-03-23 Compaq Computer Corporation Method and apparatus for providing dynamic entry points into a software layer
JP2869379B2 (ja) * 1996-03-15 1999-03-10 三菱電機株式会社 プロセッサ合成システム及びプロセッサ合成方法
US5857106A (en) 1996-05-31 1999-01-05 Hewlett-Packard Company Runtime processor detection and installation of highly tuned processor specific routines
US5748875A (en) 1996-06-12 1998-05-05 Simpod, Inc. Digital logic simulation/emulation system
US6031992A (en) 1996-07-05 2000-02-29 Transmeta Corporation Combining hardware and software to provide an improved microprocessor
US5693956A (en) * 1996-07-29 1997-12-02 Motorola Inverted oleds on hard plastic substrate
US5832205A (en) 1996-08-20 1998-11-03 Transmeta Corporation Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed
US5889990A (en) 1996-11-05 1999-03-30 Sun Microsystems, Inc. Information appliance software architecture with replaceable service module providing abstraction function between system library and platform specific OS
US6006022A (en) 1996-11-15 1999-12-21 Microsystem Synthesis, Inc. Cross-linked development and deployment apparatus and method
US6028996A (en) 1997-03-18 2000-02-22 Ati Technologies, Inc. Method and apparatus for virtualizing system operation
US6075938A (en) 1997-06-10 2000-06-13 The Board Of Trustees Of The Leland Stanford Junior University Virtual machine monitors for scalable multiprocessors
US6058466A (en) * 1997-06-24 2000-05-02 Sun Microsystems, Inc. System for allocation of execution resources amongst multiple executing processes
US6321323B1 (en) 1997-06-27 2001-11-20 Sun Microsystems, Inc. System and method for executing platform-independent code on a co-processor
US5995736A (en) 1997-07-24 1999-11-30 Ati Technologies, Inc. Method and system for automatically modelling registers for integrated circuit design
US6078736A (en) 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
US6269409B1 (en) 1997-09-02 2001-07-31 Lsi Logic Corporation Method and apparatus for concurrent execution of operating systems
US5999730A (en) 1997-10-27 1999-12-07 Phoenix Technologies Limited Generation of firmware code using a graphic representation
US6230307B1 (en) 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
US6052524A (en) 1998-05-14 2000-04-18 Software Development Systems, Inc. System and method for simulation of integrated hardware and software components
US6496847B1 (en) 1998-05-15 2002-12-17 Vmware, Inc. System and method for virtualizing computer systems
US6275893B1 (en) 1998-09-14 2001-08-14 Compaq Computer Corporation Method and apparatus for providing seamless hooking and intercepting of selected kernel and HAL exported entry points in an operating system
EP0992916A1 (en) * 1998-10-06 2000-04-12 Texas Instruments Inc. Digital signal processor
US6216216B1 (en) 1998-10-07 2001-04-10 Compaq Computer Corporation Method and apparatus for providing processor partitioning on a multiprocessor machine
US6282633B1 (en) 1998-11-13 2001-08-28 Tensilica, Inc. High data density RISC processor
US6477683B1 (en) 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6477697B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
US6295571B1 (en) 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems
US6385757B1 (en) * 1999-08-20 2002-05-07 Hewlett-Packard Company Auto design of VLIW processors
US6640238B1 (en) * 1999-08-31 2003-10-28 Accenture Llp Activity component in a presentation services patterns environment
US6415379B1 (en) 1999-10-13 2002-07-02 Transmeta Corporation Method and apparatus for maintaining context while executing translated instructions
US6615167B1 (en) 2000-01-31 2003-09-02 International Business Machines Corporation Processor-independent system-on-chip verification for embedded processor systems

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI381309B (en) * 2006-11-21 2013-01-01 Nec Corp Instruction operation code generation system
US8935512B2 (en) 2006-11-21 2015-01-13 Nec Corporation Instruction operation code generation system
TWI406148B (zh) * 2008-11-14 2013-08-21 Synopsys Inc 提供在多取樣率系統摺疊中的展開演算法之方法、非暫時之機器可讀媒體及資料處理系統
TWI507990B (zh) * 2011-01-24 2015-11-11 Nat Univ Tsing Hua 多核心指令集模擬之高平行化同步方法
TWI481992B (zh) * 2011-03-25 2015-04-21 Intel Corp 位準移位資料信號的方法與使用該方法的積體電路及系統
TWI505636B (zh) * 2012-04-10 2015-10-21 Univ Lunghwa Sci & Technology 具有最佳多重取樣率之有限脈衝濾波器及其製造方法

Also Published As

Publication number Publication date
KR20030016226A (ko) 2003-02-26
JP2004502990A (ja) 2004-01-29
CN1288585C (zh) 2006-12-06
WO2001061576A2 (en) 2001-08-23
US7036106B1 (en) 2006-04-25
US20090172630A1 (en) 2009-07-02
US20060101369A1 (en) 2006-05-11
AU2001238403A1 (en) 2001-08-27
US20090177876A1 (en) 2009-07-09
GB2376546A (en) 2002-12-18
WO2001061576A3 (en) 2003-03-27
KR100589744B1 (ko) 2006-06-15
US8161432B2 (en) 2012-04-17
GB0217221D0 (en) 2002-09-04
CN1436335A (zh) 2003-08-13
JP4619606B2 (ja) 2011-01-26
GB2376546B (en) 2004-08-04
US9582278B2 (en) 2017-02-28
US7437700B2 (en) 2008-10-14

Similar Documents

Publication Publication Date Title
TW571206B (en) Automated processor generation system for designing a configurable processor and method for the same
US6477697B1 (en) Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
US7168060B2 (en) Method of generating development environment for developing system LSI and medium which stores program therefor using VLIW designating description
US8601413B2 (en) High-level synthesis device, high-level synthesis method, high-level synthesis program, and integrated circuit design method
Qin et al. Architecture Description Languages for Retargetable Compilation.
Gyllenhaal A machine description language for compilation
Leupers et al. Instruction set extraction from programmable structures
Moreno et al. Simulation/evaluation environment for a VLIW processor architecture
Karuri et al. Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Dalinger Formal verification of a processor with memory management units
Borriello et al. Special or general-purpose hardware for Prolog: a comparison
Friedman A characterization of Prolog execution
Sutarwala et al. Flexible modeling environment for embedded systems design
Goossens A Multicore RISC-V Processor with Multihart Cores
Himmelbauer et al. The Vienna Architecture Description Language
Yanagisawa et al. ISA based system design language in HW/SW co-design environment
Boyce Topological reorganization as an aid to program simplification
Zhang et al. Trilobite: A Natural Modeling Framework for Processor Design Automation System
Mountjoy et al. Modular operational semantic specification of transport triggered architectures
Manickavasagam " a+ b" arithmetic-Theory and implementation
Järvelä Vector operation support for transport triggered architectures
Dahra Disassembly and Parsing Support for Retargetable Tools Using Sim-nML
US8495539B1 (en) Scheduling processes in simulation of a circuit design
Moreno et al. ForestaPC (Scalable-VLIW) User Instruction Set Architecture
Milner Pipeline descriptions for retargetable compilers

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees