562938 五、發明說明（1) 指所應用於高頻1c測5IC測試處理機，尤 Γ製作之所搭配之測試頭因f用的頻-率過高而不 π从西古售價昂貴而難以接受、甚至測試頭無法商品 、&巧速頻率時，即是本發明之應用領城。 Μ先參照第~圖所示，目前所普遍存在的I C測試處理 ^要係利用一機台1，與一由廠商發售之測試頭1 2，測試 ^，所、、且成’該機台1，至少應具備有得难待測I c預排入的 供料機構11 ’，及可運送該IC到各站之送測IC/完測Ic輸送 機構j2 ’利用送測Ic/完測1(：輸送機構12,將1(：送到待測 =/元測I C緩衝區丨2丨，上，並將丨c移入測試區2，後，由測 试I C輸，臂i 3 ’上之測試夾頭丨3丨，吸取丨c並壓入測試頭2 J， 進行測試，測試頭2 Γ並產生測試數據給機台1，，之後再 同樣以測武IC輸送臂13,將1C搬至待測IC /完測1C緩衝區 12\ ’再由送測IC/完測1C輸送機構12,將1C依測試數據配 的等級内者。惟，- 1 而ί1 現於模擬環境測試， 得到，亦即以測試頭作測；擬的功能就無法測試 2 ·該測試頭之成本屬 、；的功月b ’則试。 份，而一般的測試頭又二二^武處理機之高成本的部562938 V. Description of the invention (1) Refers to the high-frequency 1c test 5IC test processor, especially the test head made by Γ is too expensive to use because of the high frequency-rate of f. When accepting or even testing heads that are not available for commercial use, & smart frequency is the application leader of the present invention. Μ Refer to Figures ~. As shown in the figure, the current IC test processing commonly used is to use a machine 1 and a test head 12 sold by the manufacturer to test the machine. Therefore, the machine 1 , At least it should have a supply mechanism 11 ′ that is difficult to test I c pre-injected, and a test IC / complete test Ic transport mechanism j2 that can transport the IC to each station. : Conveying mechanism 12, will send 1 (: to the IC buffer to be tested = / meta-tested 丨 2 丨, and move 丨 c into the test area 2, and then, the test IC will lose the test on the arm i 3 ′ Chuck 丨 3 丨, suck 丨 c and press it into test head 2 J, carry out the test, test head 2 Γ and generate test data to machine 1, and then use the test IC transfer arm 13 to move 1C to Test IC / complete test 1C buffer 12 \ 'Then send IC / complete test 1C conveying mechanism 12 to 1C according to the level of test data. However, -1 and ί1 are now tested in the simulated environment. That is, the test head is used for testing; the proposed function cannot be tested2. The cost of the test head belongs to; the work month b 'is tested. The general test head is the high-cost part of the processor.
562938 五、發明說明（2) 存 與 ，至於可以對極高頻I C進行測試的測試頭所費不 相對的I C測試處理機一搭配下來，整台機器的費 ’其 又非一般廠商所能接受，故長期以來，超高頻:丨C的用▲’卻 限於少數大廠進行，一般規模的測試廠根本無法鈣^試只 塊市場。 、！ S這一 3·由於近年來晶片技術的突飛猛進，其製程與逮度 新（尤其是中央處理器CPU或繪圖處理器FPU晶片）Γ不，翻 用於該I C的測試器愈來愈難開發，愈來愈晚推出=能適 測試器研發的速度已然跟不上新丨c的速度，將來更^ ’其 空有新I C而無適用的測試頭來測試之情形。 發生 為解決上述習用丨c測試處理器之問題，本 電源供應器、測試公板與基本開機啟動環境（ 一 M a i n b 〇 a r d )組忐一、日,4 τ /七认 機板 工作型態屬於來替代習用的測試頭部份，此 業，可提高dr::: 對該IC作最詳'細的測試作 板 '測試公板為:=f性。而尤於該測試平台之主機 產品，該受消I Ic二ΐ = C製造商或其合作認證廠商之支援 場，故可以报你& 馬上會有供應商研發並推出市 的成本亦可大幅㊁二價格取得，且供貨無纟，對整體機台 ΐΪίΚ將本發明較佳實施例詳細說明如下。 平台2所組成，复圖/斤不 '本爹明主要由一機台1與一測試 一機口 1 ·該機台i提供一 = · 1其他機構之動祚、a、t 央控制早疋11以控制協調機台 、又測1C之供料機構12、受測IC/完測Ic 562938 五、發明説明（3) 之送料機構1 3、待測丨c/完測丨c緩衝承座丨4及至少一丨c測 試吸嘴1 5及測試淳口 1 6以銜接測試平台2、完測丨c測試級 別分選承置盤1 7，· 一測試平台2 (如第三圖示出）：該測試平台2係設i於前 述機台1之測試埠口 1 6内的組裝架1 6丨上，g含一電源供應 器2 1、一測試公板2 2與基本開機啟動環境2 3，其測試公板 2 2為該受測I C製造商或其合作廠商之支援產品，並在該產 品之I C解知後，在其接合位置另焊設一 I c測試插合座 221，以插入受測1C ;電源供應器21及基本開機啟動環境 2 3 (即主機板）為提供該測試公板2 2 (插入受測丨c後）可維 持系統正常運作之元件，該基本開機啟動環境2 3内含一輸 出/輸入系統2 3 1，可由機台丨.中央控制單元丨丨外接排線3至 輸出/輸入系統231，φ中央控制單元n適時發出控制訊鷺 給測試平台2及由測試平台2讀取測試結果之訊號至中央於 制單元1 1者。 ' = 根據上述各構件，並參照第四圖所示，其運作流程為 先將待測試ic放入機台i上的受測IC之供料機構12，並利^ 用受測IC/完測1C之送料機構13將待測試1(：送到待測IC/完 測I C緩衝承座1 4内，續由I c測試吸嘴1 5由待測丨c/完測J c 緩衝承座14内將待測IC置入測試公板22上之κ測試~插合座 2 2 1内進行真實環境測試，測完後覆置入待測！ 完測I c緩 衝承座14内，並由受測IC/完測IC之送料機構13送 並 依中央控制單元11讀取自輸出/輸入系統2 3丨的 斷等級，並置入適當的完測1C測試級別分選承置盤17内 562938 ^ -------- 一 五、發明說明（4) 者。 上述之機台1的測試埠口 1 6内的組裝架1 6 1係可因應不 同規袼（各家廠商可能在同一支援的規格上有不同的元件 佈局位置）的測試公板2 2及基本開機啟動環境（主機& ) 2 3 而能作架體位置的調整而仍得以固定該機^。 又，本發明之測試平台2亦可依機台1的需要，增設為 多組測試平台2並存，當然，機台1之承置測試平台2的測 試埠口 1 6及組裝架1 6 1、待測I C/完測I C綠衝承座1 4等都需 相對增加組數。 另外’該測試平台2亦可由機台1提供其直流電源者。 綜上所述，本案所發明之應用於高頻丨c測試之丨c測試 處理機於申凊則並未公開’已具有其新賴性，而其可解決 傳統I C測試處理機對高頻I c測試上的造價昂貴、甚至無機 可用的問題’其發明已具備進步性，符合發明專利要件， 爰依法提出專利申請。惟以上所述者，僅為本發明之較隹 實施例而已，並非用來限定本發明實施之範圍，即凡依本 發明申請專利範圍所做的均等變化與修飾，皆為本發明專 利範圍所涵蓋。562938 V. Description of the invention (2) Save and, as for the test head that can test the very high frequency IC, the cost of the IC test processor is not the same as that of the general manufacturer. Therefore, for a long time, the use of UHF: 丨 'has been limited to a few large factories, and a general-scale test factory cannot test the calcium market at all. ,! S3. Due to the rapid advancement of chip technology in recent years, its process and accuracy are new (especially the central processing unit CPU or graphics processor FPU chip). No, it is increasingly difficult to develop testers for this IC. More and more late launches = the speed of the R & D tester has been unable to keep up with the speed of the new 丨 c. In the future, it will be more and more ^ 'there is a new IC without a suitable test head to test. In order to solve the above-mentioned problems in the conventional test processor, the power supply unit, the test public board, and the basic startup environment (one main board), the first and the day, the 4 τ / seven identification machine board working type belongs to To replace the conventional test head part, this industry can improve dr ::: The most detailed 'thin test board' for this IC. The test board is: = f. And especially for the mainframe products of the test platform, the depleted I Ic IIΐ = C manufacturer or its cooperative certification manufacturer's support field, so it can be reported to you & there will be a supplier R & D and the cost of launching the market can also be significant Second, the price is obtained, and the supply is free. The overall embodiment of the present invention will be described in detail below. The platform 2 is composed of a complex picture / jinbu 'Ben Daming is mainly composed of a machine 1 and a test port 1 · This machine i provides a = · 1 other organizations' movement, a, t central control early morning 11 The feeding mechanism for controlling and coordinating the machine, and measuring 1C again 12. The IC under test / Ic 562938 5. The feeding mechanism of the invention description (3) 1 3. To be tested 丨 c / Complete testing 丨 c buffer socket 丨4 and at least one 丨 c test nozzle 15 and test spring 16 to connect to the test platform 2 and complete the test 丨 c test level sorting of the mounting plate 1 7, a test platform 2 (as shown in the third figure): The test platform 2 is located on the assembly rack 16 in the test port 16 of the aforementioned machine 1. The g includes a power supply 2 1, a test public board 2 2, and a basic startup environment 2 3. The test board 22 is a support product of the tested IC manufacturer or its partner, and after the IC of the product is known, an I c test socket 221 is additionally welded at its joint position to insert the test socket. Test 1C; the power supply 21 and the basic boot environment 2 3 (ie, the motherboard) are the components that provide the test public board 2 2 (after being inserted into the test) to maintain the normal operation of the system. The basic start-up environment 2 3 contains an output / input system 2 3 1 and can be used by the machine 丨. Central control unit 丨 丨 external cable 3 to the output / input system 231, φ central control unit n sends a control signal to the test in time The platform 2 and the signal from which the test result is read by the test platform 2 are sent to the central processing unit 11. '= According to the above components and referring to the fourth figure, the operation process is to first put the IC to be tested into the supply mechanism 12 of the IC under test on the machine i, and use the IC under test / final test The feeding mechanism 13 of 1C will send the test 1 (: to the IC under test / completed IC buffer socket 1 4 and continued by I c test nozzle 1 5 by the test 丨 c / completed J c buffer socket 14 The IC under test is placed in the κ test on the test public board 22-the real environment test is performed in the socket 2 2 1 and after the test is completed, the test IC is placed in the test socket! The test IC / test IC's feeding mechanism 13 sends and reads the interruption level from the output / input system 2 3 丨 according to the central control unit 11 and puts it in the appropriate completion test 1C test level sorting tray 17 562938 ^ ---- 15. Invention description (4). The assembly rack 16 in the test port 16 of the machine 1 mentioned above can meet different regulations (each manufacturer may support the same The specifications have different component layout positions) of the test male board 2 2 and the basic boot environment (host &) 2 3 so that the position of the frame can be adjusted and the machine can still be fixed. The test platform 2 can also be added to multiple sets of test platforms 2 to coexist according to the needs of the machine 1. Of course, the test port 1 6 and the assembly rack 1 6 of the machine 1 are installed on the test platform 1. IC to be tested / finished It is necessary to relatively increase the number of test sets for IC green punch sockets 1, 4, etc. In addition, 'the test platform 2 can also be provided with its DC power source by machine 1. In summary, the invention in this case is applied to high frequency 丨 c test丨 c test processor Yu Shenyu did not disclose 'it has its new nature, and it can solve the traditional IC test processor for high-frequency I c test costly and even inorganic availability problems' its invention has Progressiveness, in line with the requirements of the invention patent, and file a patent application in accordance with the law. However, the above are only comparative examples of the present invention, and are not intended to limit the scope of implementation of the present invention. Equal changes and modifications made are covered by the scope of the present invention patent.
562938 圖式簡單說明 圖式簡單說明： 第一圖係習見之内含測試器之I c測試處理機結構示意圖。 第二圖係本發明之I C測試處理機機台台面結構立體示意 圖。 第三圖係本發明之測試平台設置於機台測咸埠口之立體圖 分解圖。 第四圖係本發明之測試平台設置於機台測試埠口之另一角 度立體組合圖。 習用技術部份： Γ ·機台 Η ’ ·供料機構 1 2 送測I C /完測I C承4置盤及輸送機構 1 3 ’ .測試I C輸送臂 1 3 1 ,·測試夾頭 1 4 ’ .完測I C放置盤 1 5 ’ · I C輸送機構 1 5 Γ .測試夾頭 2’ .測試區 2 Γ .測試頭 本發明部份： 1.機台 1 1.中央控制單元 12.受測1C之供料機構 1 3.受測I C/完測I C之送料機構562938 Brief description of the diagram Brief description of the diagram: The first diagram is a schematic diagram of the structure of the I c test handler that includes a tester. The second figure is a schematic perspective view of the table structure of the IC test processor of the present invention. The third figure is an exploded perspective view of the test platform of the present invention installed at the test port of the machine. The fourth figure is another perspective three-dimensional combination diagram of the test platform of the present invention set at the test port of the machine. Conventional technical parts: Γ · Machine · '· Feeding mechanism 1 2 Sending IC / Complete testing IC bearing 4 tray and conveying mechanism 1 3' .Test IC conveying arm 1 3 1, · Test chuck 1 4 ' Finished IC placement plate 15 '· IC conveying mechanism 15 Γ. Test chuck 2'. Test area 2 Γ. Test head Part of the invention: 1. Machine 1 1. Central control unit 12. Tested 1C Feeding mechanism 1 3. Feeding mechanism of tested IC / completed IC
第9頁 562938 圖式簡單說明 1 4.待測I C/完測I C緩衝承座 1 5 . I C測試吸嘴 1 6 .測試埠口 1 6 1.組裝架 1 7 .完測I C測試級別分選承置盤 2.測試平台 21 .電源供應 器 22 .測試公板 2 2 1 · I C 測 試 插 合 座 23 .基本開機 啟 動 環 境 231.輸出/ 輸 入 系 統 3.排線Page 9 562938 Schematic description 1 4. IC to be tested / IC buffer socket to be tested 1 5. IC test nozzle 1 6. Test port 1 6 1. Assembly rack 1 7. IC test level sorting after test Mounting plate 2. Test platform 21. Power supply 22. Test male board 2 2 1 · IC test socket 23. Basic startup environment 231. Output / input system 3. Cable
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