WO2023225772A1

WO2023225772A1 - Fully automatic method and system for testing read and write functions of dram storage cell

Info

Publication number: WO2023225772A1
Application number: PCT/CN2022/094352
Authority: WO
Inventors: 陈焕君; 牟炳叡; 王自鑫; 胡炳翔; 杨锐佳
Original assignee: 中山大学
Priority date: 2022-05-23
Filing date: 2022-05-23
Publication date: 2023-11-30
Also published as: WO2023225772A9

Abstract

The present invention relates to the technical field of integrated circuit testing. Provided are a fully automatic method and system for testing read and write functions of a DRAM storage cell. The method comprises the following steps: acquiring a silk screen image of a chip to be tested, and performing recognition on the silk screen image using a ResNet, so as to obtain silk screen information; reading, according to the silk screen information and from a preset database, a read and write function test method that matches the silk screen information, and transmitting the read and write function test method to an ATE; and electrically connecting the ATE to said chip, and the ATE performing a read and write function test on said chip according to the received read and write function test method. In the present invention, the automation of the read and write function test work for a DRAM storage cell is realized, the efficiency of the read and write function test work is effectively increased, and a relatively high accuracy rate of the read and write function test is also ensured.

Description

A fully automatic DRAM memory unit read and write function testing method and system

Technical field

The present invention relates to the technical field of integrated circuit testing, and more specifically, to a fully automatic DRAM storage unit read and write function testing method and system.

Background technique

DRAM storage unit read and write function testing is usually based on the fault model of the DRAM storage unit. Common fault models mainly include: (1) Fixed unit-based fault model; (2) Memory test fault model based on bridge defects; (3) ) Memory test fault model based on correlation defects; (4) Data storage fault model, etc. The failure modes shown by these fault models mainly include: (1) hard failure or soft effect fixed as "1"/"0"; (2) open circuit or short circuit failure; (3) address decoder failure; (4) Graphics sensitivity failure: The memory cannot work reliably when testing certain graphics.

Testing the read and write functions of DRAM chip memory cells requires a lot of time and manpower and material resources. Even so, the possibility of manual errors is still high. Currently, test staff are committed to automating the test process and propose using ATE (Automatic Test Equipment, integrated circuit automatic test machine) to test the chip by setting the device operating power supply, input level, output level, reference level, and load. The value of the current, sets the power-on sequence of the device, sets the data format, timing, channel and control register allocation of the device's address signal, control signal and data signal, and performs full chip erasure and verification, single sector respectively Erase and verification, write status register verification, read chip ID verification, full chip memory unit read and write function verification, write protection verification, DC parameter verification and AC parameter verification. However, this method still requires the full participation of test staff, and there are still problems with low efficiency and high error probability in testing the read and write functions of DRAM memory cells.

Contents of the invention

The present invention provides a fully automatic DRAM storage unit read and write function test method and system to overcome the shortcomings of low efficiency and high error probability in the current DRAM storage unit read and write function testing work.

In order to solve the above technical problems, the technical solutions of the present invention are as follows:

A fully automatic DRAM storage unit read and write function testing method, including the following steps:

Collect the silk screen image of the chip under test, use ResNet neural network to identify the silk screen image, and obtain the silk screen information;

According to the silk screen information, read the read and write function test method matching the screen screen information from the preset database, and transmit the read and write function test method to the ATE equipment;

The ATE device is electrically connected to the chip under test, and the ATE device performs a read and write function test on the chip under test according to the received read and write function test method.

As a preferred solution, the step of the ATE device testing the read and write function of the chip under test according to the received read and write function test method includes: the ATE device respectively sets the values applied to the chip under test according to the received read and write function test method. Values of working power supply, input level, output level, reference level and load current; set the power-on sequence of the chip under test; set the data format, timing and channel of the control signal, address signal and data signal of the chip under test and the allocation of control registers; call the preset test patterns in sequence, write data to the chip under test, and read the output data of the chip under test; compare the output data of the chip under test with the corresponding expected readout data Comparison and verification are performed. If the comparison is consistent, it is judged that the read and write functions of the chip under test are normal; otherwise, it is judged that the read and write functions of the chip under test are abnormal.

As a preferred solution, the preset test pattern includes one or more of a "0" pattern, a writing all "1" reading all "1" pattern, a walking pattern, and a checkerboard pattern.

As a preferred solution, the method also includes the following steps: classifying the chips to be tested based on comparison and verification, transporting the chips judged to have normal reading and writing functions to the first classification through a conveyor belt, and transporting the chips judged to have abnormal reading and writing functions to the first classification through a conveyor belt The second classification is to make statistics on the normal rate of the chip.

As a preferred solution, according to the silk screen information, the step of reading the reading and writing function test method matching the silk screen information from a preset database includes: the silk screen information includes a chip model; according to the chip in the silk screen information model, retrieve the reading and writing function test method with the chip model tag from the preset database, and transmit it to the ATE equipment.

Furthermore, the present invention also proposes a fully automatic DRAM storage unit read and write function testing system, applying the method proposed in any of the above technical solutions. Among them, the system of the present invention includes an image acquisition module, an identification module, a reading module for reading and writing function test methods, ATE equipment, a conveyor belt and a power mechanism.

Among them, the image acquisition module is used to collect the silk screen image of the chip under test; the recognition module is used to use ResNet neural network to identify the silk screen image of the chip under test, and output the silk screen information of the chip under test; the read and write function test method reading module includes A database, in which a reading and writing function test method with a chip model tag is preset; the reading module of the reading and writing function testing method is used to read from the database the data matching the silk screen information according to the silk screen information. The reading and writing function test method; the ATE equipment is used to test the reading and writing function of the chip under test according to the received reading and writing function testing method; the conveyor belt is used to sequentially transport the chip under test through the image acquisition module and ATE under the action of the power mechanism equipment.

As a preferred solution, the system further includes an electrostatic shielding cover. The electrostatic shielding cover is used to cover the periphery of the ATE equipment and the chip to be tested when the chip to be tested is transferred to the location of the ATE equipment.

As a preferred solution, the system also includes a transmission control module, which is connected to the ATE equipment and the power mechanism; the transmission control module controls the start and stop of the conveyor belt and the transmission speed by controlling the start and stop of the power mechanism; When the conveyor belt transmits the chip under test to the position of the ATE equipment, the transmission control module controls the conveyor belt to stop working; when the ATE equipment completes the read and write function test, the ATE equipment sends a test result signal to the transmission control module, and the transmission control module The module controls the conveyor belt to transport the chip under test to the first classification port or the second classification port according to the test result signal.

As a preferred solution, the ATE equipment is preset with test patterns for testing and verifying the reading and writing functions of the chip under test; the test patterns include a "0" pattern, a write all "1" pattern, a read all "1" pattern, and a walking pattern. One or more of graphics and checkerboard graphics.

Further, the present invention also proposes a fully automatic DRAM storage unit read and write function test system, including a memory and a processor. The memory stores a computer program. When the processor executes the computer program, any of the above technical solutions can be implemented. The steps of the proposed fully automatic DRAM memory cell read and write function testing method.

Furthermore, the present invention also proposes a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the fully automatic DRAM storage unit read and write function testing method proposed in any of the above technical solutions are implemented.

Compared with the existing technology, the beneficial effects of the technical solution of the present invention are: the present invention uses ResNet neural network to identify the silk screen image of the DRAM memory unit chip to be tested, and reads and calls the corresponding read and write functions from the database based on the identification results. Functional test method, and then use ATE equipment to test the read and write function of the chip under test according to the received read and write function test method, to realize the automation of the read and write function test of the DRAM storage unit, effectively improve the efficiency of the read and write function test, and at the same time ensure a high The reading and writing function test accuracy rate.

Description of the drawings

Figure 1 is a flow chart of a fully automatic DRAM memory unit read and write function testing method according to an embodiment of the present invention.

FIG. 2 is a flow chart for testing the read and write functions of the ATE equipment according to the embodiment of the present invention.

Figure 3 is an architectural diagram of a fully automatic DRAM memory unit read and write function test system according to an embodiment of the present invention.

Detailed ways

The drawings are for illustrative purposes only and should not be construed as limitations of this patent;

In order to better illustrate this embodiment, some components in the drawings will be omitted, enlarged or reduced, which does not represent the size of the actual product;

It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

The technical solution of the present invention will be further described below with reference to the accompanying drawings and examples.

Example 1

This embodiment proposes a fully automatic DRAM storage unit read and write function testing method. As shown in Figure 1, it is a flow chart of the fully automatic DRAM storage unit read and write function testing method in this embodiment.

This embodiment proposes a fully automatic DRAM storage unit read and write function test method, which includes the following steps:

S1. Collect the silk screen image of the chip to be tested, and use the ResNet neural network to identify the silk screen image to obtain the silk screen information.

S2. According to the silk screen information, read the read and write function test method that matches the screen screen information from the preset database 310, and transmit the read and write function test method to the ATE device 400.

S3. Electrically connect the ATE device 400 to the chip under test. The ATE device 400 performs a read and write function test on the chip under test according to the received read and write function test method.

In a specific implementation process, several DRAM memory unit chips to be tested are placed on a conveyor belt and pass through the OpenMV camera and the J750-EX series ATE equipment 400 in sequence.

Among them, the OpenMV camera collects the silk screen image of the chip to be tested, and identifies the silk screen image through the trained ResNet neural network called in the MicroPython language to obtain the silk screen information, and retrieves the DRAM storage unit chip to be tested corresponding to the silk screen information. Read and write function test methods, and send them to the ATE device 400 through the wireless transmission protocol.

The conveyor belt transports the DRAM memory unit chip to be tested to the position of the ATE equipment 400. The ATE equipment 400 is electrically connected to the chip to be tested. At this time, the ATE equipment 400 performs a read and write function test on the chip to be tested according to the received read and write function test method.

J750-EX is a very large scale integrated circuit (VLSI) test system with rich and powerful testing resources that can be used to meet the testing needs of the new generation of VLSI storage products. Set test-related parameters on J750-EX and The execution program can well meet the read and write test requirements of DRAM storage cells.

In this embodiment, the ResNet neural network is used to identify the silk screen image of the DRAM memory unit chip to be tested, and the corresponding read and write function test method is read from the database 310 according to the identification result, and then the ATE device 400 is used according to the received The read and write function test method tests the read and write function of the chip under test to realize the automation of the read and write function test of the DRAM memory unit, effectively improves the efficiency of the read and write function test, and at the same time ensures a high read and write function test accuracy.

In an optional embodiment, the step of the ATE device 400 performing the read and write function test on the chip under test according to the received read and write function test method includes:

S3.1. The ATE equipment 400 sets respectively according to the received reading and writing function test method:

(1) The values of the operating power supply, input level, output level, reference level and load current applied to the chip under test;

(2) The power-on sequence of the chip under test;

(3) The data format, timing, channel and control register allocation of the control signals, address signals and data signals of the chip under test.

S3.2. Call the preset test patterns in sequence, write data to the chip under test, and read the output data of the chip under test.

S3.3. Compare and verify the output data of the chip under test with the corresponding expected readout data: if the comparison is consistent, it is judged that the read and write function of the chip under test is normal; otherwise, the read and write function of the chip under test is judged. abnormal.

As shown in Figure 2, it is a flow chart for testing the read and write functions of the ATE device 400 in this embodiment.

Aiming at the failure modes shown by the common failure models of DRAM storage cells, test pictures are used to test the read and write functions. Common failure modes include: (1) hard failure or soft effect fixed to "1"/"0"; (2) open circuit or short circuit failure; (3) address decoder failure; (4) graphics sensitivity failure.

When testing the full-chip storage unit read and write functions of DRAM storage units, the above fault modes are mainly tested by setting different test patterns.

In an optional embodiment, the test patterns used include a “0” pattern (writeall_00_readall_00.pat), a write all “1” read all “1” pattern (writeall_ff_readall_ff.pat), a walking pattern (walking.pat), and a chessboard One or more types of grid graphics (checkboard.pat).

Further, in an optional embodiment, the method also includes the following steps: classifying the chips to be tested based on comparison verification, transporting the chips judged to have normal reading and writing functions to the first classification through a conveyor belt, and classifying the chips judged to have read and write functions. Chips with abnormal write functions are transported to the second classification via a conveyor belt, and the normal rate of the chips is counted.

In this embodiment, the chips are classified according to the read and write function test results of the DRAM memory unit chips to be tested.

In a specific implementation process, it is judged based on the DRAM chip read and write function test results of J750-EX whether all test items have passed, and classified through a dual conveyor belt; if so, the chip under test is directly conveyed by the first conveyor belt to the first classification box, and store it as a qualified chip; if not, the chip to be tested is transported to the second classification box by the second conveyor belt, and is stored as an unqualified chip, and the pass rate of the current read and write function test is Make statistics.

Further, in an optional embodiment, the silk screen information includes the chip model.

In this embodiment, according to the silk screen information, the step of reading the reading and writing function testing method matching the silk screen information from the preset database 310 includes: according to the chip model in the silk screen information, from the preset database 310 The reading and writing function test method with the chip model tag is retrieved from the database 310 and transmitted to the ATE equipment 400 .

The database 310 in this embodiment stores reading and writing function test methods corresponding to different chip models. This embodiment uses ResNet neural network to identify the silk screen image of the chip under test to obtain the silk screen information with the chip model, and based on the chip under test Call up the matching read and write function test method based on the chip model to achieve high test accuracy while automating the read and write function test.

Example 2

This embodiment proposes a fully automatic DRAM storage unit read and write function test system. As shown in Figure 3, it is an architecture diagram of the fully automatic DRAM storage unit read and write function test system of this embodiment.

The fully automatic DRAM storage unit read and write function test system proposed in this embodiment includes:

The image acquisition module 100 is used to acquire the silk screen image of the chip to be tested.

The identification module 200 is used to use ResNet neural network to identify the silk screen image of the chip under test, and output the silk screen information of the chip under test.

The reading and writing function test method reading module 300 includes a database 310, in which a reading and writing function testing method with a chip model tag is preset.

The read-write function test method reading module 300 is configured to read the read-write function test method matching the silk-screen information from the database 310 according to the silk-screen information.

The ATE equipment 400 is used to test the read and write functions of the chip under test according to the received read and write function test methods.

The conveyor belt is used to sequentially convey the chip to be tested through the image acquisition module 100 and the ATE equipment 400 under the action of a power mechanism.

In a specific implementation process, the identification module 200 is equipped with a ResNet neural network called in the MicroPython language, and the image acquisition module 100, the identification module 200, the reading and writing function test method reading module 300 and the ATE device 400 are equipped with a MicroPython language. Language-invoked wireless information transfer protocol.

In this embodiment, a test pattern is preset in the ATE device 400 for testing and verifying the read and write functions of the chip under test.

Wherein, the test pattern includes one or more of a "0" pattern, a writing all "1" pattern and a reading all "1" pattern, a walking pattern, and a checkerboard pattern.

Further, after the recognition module 200 completes the recognition and outputs the silk screen information of the chip to be tested, the recognized silk screen information is transmitted to the read and write function test method reading module 300 . Among them, the silk screen information includes the chip model.

The reading and writing function test method reading module 300 reads the reading and writing function testing method that matches the silk screen information from the database 310 according to the received silk screen information. Specifically, the reading and writing function test method reading module 300 retrieves the reading and writing function testing method with the chip model tag from the preset database 310 according to the chip model in the silk screen information, and transmits it to the ATE equipment 400 Perform reading and writing function tests.

In a specific implementation process, the ATE equipment 400 uses the J750-EX series test machine, which performs the read and write function test on the chip under test according to the received read and write function test method. Set the working power supply, input level, output level, reference level and load current value applied to the chip under test; set the power-on sequence of the chip under test; set the control signal, address signal and data of the chip under test Data format, timing, channel and control register allocation of signals.

After completing the connection and setting of the chip under test, the ATE device 400 sequentially calls the preset test pattern, writes data to the chip under test, reads the output data of the chip under test, and then transfers the output data of the chip under test. The output data is compared and verified with the corresponding expected readout data. If the comparison is consistent, it is judged that the read and write function of the chip under test is normal; otherwise, it is judged that the read and write function of the chip under test is abnormal.

In an optional embodiment, the system further includes an electrostatic shielding cover, which is used to cover the ATE equipment 400 and the periphery of the chip under test when the chip under test is transferred to the ATE equipment 400 position.

The additional electrostatic shielding cover in this embodiment is used to reduce various failures caused by static electricity during the testing process of DRAM memory unit chips.

In another optional embodiment, the system also includes a transmission control module, which is connected to the ATE equipment 400 and the power mechanism; the transmission control module controls the start and stop of the conveyor belt by controlling the start and stop of the power mechanism. and transmission speed.

When the conveyor belt conveys the chip under test to the ATE equipment 400 position, the conveyor control module controls the conveyor belt to stop working.

After the ATE device 400 completes the read and write function test, the ATE device 400 sends a test result signal to the transmission control module. The transmission control module controls the conveyor belt to transmit the chip under test to the first classification port or the second classification according to the test result signal. mouth.

A first classification box and a second classification box are provided on one side of the first classification port and the second classification port, respectively used to classify the current batch of DRAM memory unit chips that pass the read and write function test and those that do not pass the read and write function test. Storage.

Furthermore, in this embodiment, the ATE equipment 400 performs statistics on the normal rate of reading and writing function tests of the current batch of DRAM memory unit chips, which facilitates the staff's statistics and analysis work.

Example 3

This embodiment proposes a fully automatic DRAM storage unit reading and writing function testing system, which includes a memory and a processor, and the memory stores a computer program.

When the processor executes the computer program, the steps of the fully automatic DRAM storage unit read and write function testing method described in Embodiment 1 are implemented.

Furthermore, this embodiment also proposes a fully automatic DRAM storage unit reading and writing function testing system, which includes a storage medium on which a computer program is stored.

When the computer program is executed by the processor, the steps of the fully automatic DRAM storage unit read and write function testing method described in Embodiment 1 are implemented.

The same or similar numbers correspond to the same or similar parts;

The terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limitations to this patent;

Obviously, the above-mentioned embodiments of the present invention are only examples to clearly illustrate the present invention, and are not intended to limit the implementation of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. An exhaustive list of all implementations is neither necessary nor possible. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

A fully automatic DRAM storage unit read and write function testing method, which is characterized by including the following steps:

Collect the silk screen image of the chip under test, use ResNet neural network to identify the silk screen image, and obtain the silk screen information;

According to the silk screen information, read the read and write function test method matching the screen screen information from the preset database, and transmit the read and write function test method to the ATE equipment;

The ATE device is electrically connected to the chip under test, and the ATE device performs a read and write function test on the chip under test according to the received read and write function test method.
The fully automatic DRAM storage unit read and write function testing method according to claim 1, characterized in that the step of the ATE device testing the read and write function of the chip under test according to the received read and write function test method includes:

The ATE equipment separately sets the values of the working power supply, input level, output level, reference level and load current applied to the chip under test according to the received read and write function test method; sets the power-on sequence of the chip under test ;Set the data format, timing, channel and control register allocation of the control signal, address signal and data signal of the chip under test;

Call the preset test patterns in sequence, write data to the chip under test, and read the output data of the chip under test;

The output data of the chip under test is compared and verified with the corresponding expected readout data. If the comparison is consistent, it is judged that the read and write function of the chip under test is normal; otherwise, it is judged that the read and write function of the chip under test is abnormal.
The fully automatic DRAM storage unit reading and writing function testing method according to claim 2, characterized in that the preset test patterns include a "0" pattern, a writing all "1" pattern, a reading all "1" pattern, a walking pattern, One or more of the checkerboard patterns.
The fully automatic DRAM storage unit read and write function testing method according to claim 2, further comprising the following steps: classifying the chips to be tested based on comparison and verification, and transporting the chips judged to have normal read and write functions through a conveyor belt After reaching the first classification, the chips judged to have abnormal reading and writing functions are transported to the second classification through the conveyor belt, and the normal rate of the chips is counted.
The fully automatic DRAM storage unit reading and writing function testing method according to any one of claims 1 to 4, characterized in that, according to the silk screen information, reading and writing data matching the silk screen information from a preset database The steps of the functional testing method include:

The silk screen information includes the chip model;

According to the chip model in the silk screen information, the read and write function test method with the chip model label is retrieved from the preset database and transmitted to the ATE equipment.
A fully automatic DRAM storage unit read and write function testing system, characterized by applying the method described in any one of claims 1 to 5; wherein the system includes:

Image acquisition module, used to collect silk screen images of the chip under test;

The identification module is used to use ResNet neural network to identify the silk screen image of the chip under test and output the silk screen information of the chip under test;

A read-write function test method reading module, which includes a database in which a read-write function test method with a chip model label is preset;

The reading and writing function test method reading module is used to read the reading and writing function testing method matching the silk screen information from the database according to the silk screen information;

ATE equipment is used to test the read and write functions of the chip under test according to the received read and write function test methods;

A conveyor belt is used to sequentially transport the chip to be tested through the image acquisition module and ATE equipment under the action of a power mechanism.
The fully automatic DRAM storage unit read and write function test system according to claim 6, characterized in that the system further includes an electrostatic shielding cover, and the electrostatic shielding cover is used to cover the chip when the chip to be tested is transferred to the ATE equipment location. Located on the periphery of the ATE equipment and the chip under test.
The fully automatic DRAM storage unit read and write function test system according to claim 6, characterized in that the system further includes a transmission control module, the transmission control module is connected to the ATE equipment and the power mechanism; the transmission control module The module controls the start, stop and transmission speed of the conveyor belt by controlling the start and stop of the power mechanism;

When the conveyor belt transmits the chip under test to the ATE equipment location, the transmission control module controls the conveyor belt to stop working;

After the ATE device completes the read and write function test, the ATE device sends a test result signal to the transmission control module. The transmission control module controls the conveyor belt to transmit the chip under test to the first classification port or the second classification port according to the test result signal.
The fully automatic DRAM storage unit read and write function testing system according to claim 6, characterized in that the ATE equipment is preset with a test pattern for testing and verifying the read and write function of the chip under test; the test pattern includes One or more of "0" graphics, writing all "1" and reading all "1" graphics, walking graphics, and checkerboard graphics.
A fully automatic DRAM storage unit reading and writing function testing system, including a memory and a processor, the memory stores a computer program, and is characterized in that when the processor executes the computer program, any one of claims 1 to 5 is realized. The steps of the fully automatic DRAM storage unit read and write function testing method described in the item.