WO2023225772A1 - Procédé et système entièrement automatiques pour tester des fonctions de lecture et d'écriture d'une cellule de stockage dram - Google Patents

Procédé et système entièrement automatiques pour tester des fonctions de lecture et d'écriture d'une cellule de stockage dram Download PDF

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WO2023225772A1
WO2023225772A1 PCT/CN2022/094352 CN2022094352W WO2023225772A1 WO 2023225772 A1 WO2023225772 A1 WO 2023225772A1 CN 2022094352 W CN2022094352 W CN 2022094352W WO 2023225772 A1 WO2023225772 A1 WO 2023225772A1
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Prior art keywords
read
write function
test
under test
chip
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PCT/CN2022/094352
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English (en)
Chinese (zh)
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WO2023225772A9 (fr
Inventor
陈焕君
牟炳叡
王自鑫
胡炳翔
杨锐佳
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中山大学
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Priority to PCT/CN2022/094352 priority Critical patent/WO2023225772A1/fr
Publication of WO2023225772A1 publication Critical patent/WO2023225772A1/fr
Publication of WO2023225772A9 publication Critical patent/WO2023225772A9/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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  • the present invention relates to the technical field of integrated circuit testing, and more specifically, to a fully automatic DRAM storage unit read and write function testing method and system.
  • DRAM storage unit read and write function testing is usually based on the fault model of the DRAM storage unit.
  • Common fault models mainly include: (1) Fixed unit-based fault model; (2) Memory test fault model based on bridge defects; (3) ) Memory test fault model based on correlation defects; (4) Data storage fault model, etc.
  • the failure modes shown by these fault models mainly include: (1) hard failure or soft effect fixed as "1"/"0"; (2) open circuit or short circuit failure; (3) address decoder failure; (4) Graphics sensitivity failure: The memory cannot work reliably when testing certain graphics.
  • test staff are committed to automating the test process and propose using ATE (Automatic Test Equipment, integrated circuit automatic test machine) to test the chip by setting the device operating power supply, input level, output level, reference level, and load.
  • ATE Automatic Test Equipment, integrated circuit automatic test machine
  • the value of the current sets the power-on sequence of the device, sets the data format, timing, channel and control register allocation of the device's address signal, control signal and data signal, and performs full chip erasure and verification, single sector respectively Erase and verification, write status register verification, read chip ID verification, full chip memory unit read and write function verification, write protection verification, DC parameter verification and AC parameter verification.
  • this method still requires the full participation of test staff, and there are still problems with low efficiency and high error probability in testing the read and write functions of DRAM memory cells.
  • the present invention provides a fully automatic DRAM storage unit read and write function test method and system to overcome the shortcomings of low efficiency and high error probability in the current DRAM storage unit read and write function testing work.
  • a fully automatic DRAM storage unit read and write function testing method including the following steps:
  • the silk screen information read the read and write function test method matching the screen screen information from the preset database, and transmit the read and write function test method to the ATE equipment;
  • the ATE device is electrically connected to the chip under test, and the ATE device performs a read and write function test on the chip under test according to the received read and write function test method.
  • the step of the ATE device testing the read and write function of the chip under test according to the received read and write function test method includes: the ATE device respectively sets the values applied to the chip under test according to the received read and write function test method. Values of working power supply, input level, output level, reference level and load current; set the power-on sequence of the chip under test; set the data format, timing and channel of the control signal, address signal and data signal of the chip under test and the allocation of control registers; call the preset test patterns in sequence, write data to the chip under test, and read the output data of the chip under test; compare the output data of the chip under test with the corresponding expected readout data Comparison and verification are performed. If the comparison is consistent, it is judged that the read and write functions of the chip under test are normal; otherwise, it is judged that the read and write functions of the chip under test are abnormal.
  • the preset test pattern includes one or more of a "0" pattern, a writing all “1” reading all “1” pattern, a walking pattern, and a checkerboard pattern.
  • the method also includes the following steps: classifying the chips to be tested based on comparison and verification, transporting the chips judged to have normal reading and writing functions to the first classification through a conveyor belt, and transporting the chips judged to have abnormal reading and writing functions to the first classification through a conveyor belt
  • the second classification is to make statistics on the normal rate of the chip.
  • the step of reading the reading and writing function test method matching the silk screen information from a preset database includes: the silk screen information includes a chip model; according to the chip in the silk screen information model, retrieve the reading and writing function test method with the chip model tag from the preset database, and transmit it to the ATE equipment.
  • the present invention also proposes a fully automatic DRAM storage unit read and write function testing system, applying the method proposed in any of the above technical solutions.
  • the system of the present invention includes an image acquisition module, an identification module, a reading module for reading and writing function test methods, ATE equipment, a conveyor belt and a power mechanism.
  • the image acquisition module is used to collect the silk screen image of the chip under test;
  • the recognition module is used to use ResNet neural network to identify the silk screen image of the chip under test, and output the silk screen information of the chip under test;
  • the read and write function test method reading module includes A database, in which a reading and writing function test method with a chip model tag is preset; the reading module of the reading and writing function testing method is used to read from the database the data matching the silk screen information according to the silk screen information.
  • the reading and writing function test method; the ATE equipment is used to test the reading and writing function of the chip under test according to the received reading and writing function testing method;
  • the conveyor belt is used to sequentially transport the chip under test through the image acquisition module and ATE under the action of the power mechanism equipment.
  • the system further includes an electrostatic shielding cover.
  • the electrostatic shielding cover is used to cover the periphery of the ATE equipment and the chip to be tested when the chip to be tested is transferred to the location of the ATE equipment.
  • the system also includes a transmission control module, which is connected to the ATE equipment and the power mechanism; the transmission control module controls the start and stop of the conveyor belt and the transmission speed by controlling the start and stop of the power mechanism;
  • the transmission control module controls the conveyor belt to stop working;
  • the ATE equipment completes the read and write function test, the ATE equipment sends a test result signal to the transmission control module, and the transmission control module The module controls the conveyor belt to transport the chip under test to the first classification port or the second classification port according to the test result signal.
  • the ATE equipment is preset with test patterns for testing and verifying the reading and writing functions of the chip under test; the test patterns include a "0" pattern, a write all "1” pattern, a read all "1” pattern, and a walking pattern. One or more of graphics and checkerboard graphics.
  • the present invention also proposes a fully automatic DRAM storage unit read and write function test system, including a memory and a processor.
  • the memory stores a computer program.
  • the processor executes the computer program, any of the above technical solutions can be implemented.
  • the steps of the proposed fully automatic DRAM memory cell read and write function testing method are described.
  • the present invention also proposes a storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the steps of the fully automatic DRAM storage unit read and write function testing method proposed in any of the above technical solutions are implemented.
  • the present invention uses ResNet neural network to identify the silk screen image of the DRAM memory unit chip to be tested, and reads and calls the corresponding read and write functions from the database based on the identification results.
  • Functional test method and then use ATE equipment to test the read and write function of the chip under test according to the received read and write function test method, to realize the automation of the read and write function test of the DRAM storage unit, effectively improve the efficiency of the read and write function test, and at the same time ensure a high The reading and writing function test accuracy rate.
  • Figure 1 is a flow chart of a fully automatic DRAM memory unit read and write function testing method according to an embodiment of the present invention.
  • FIG. 2 is a flow chart for testing the read and write functions of the ATE equipment according to the embodiment of the present invention.
  • Figure 3 is an architectural diagram of a fully automatic DRAM memory unit read and write function test system according to an embodiment of the present invention.
  • This embodiment proposes a fully automatic DRAM storage unit read and write function testing method. As shown in Figure 1, it is a flow chart of the fully automatic DRAM storage unit read and write function testing method in this embodiment.
  • This embodiment proposes a fully automatic DRAM storage unit read and write function test method, which includes the following steps:
  • S1 Collect the silk screen image of the chip to be tested, and use the ResNet neural network to identify the silk screen image to obtain the silk screen information.
  • the ATE device 400 performs a read and write function test on the chip under test according to the received read and write function test method.
  • DRAM memory unit chips to be tested are placed on a conveyor belt and pass through the OpenMV camera and the J750-EX series ATE equipment 400 in sequence.
  • the OpenMV camera collects the silk screen image of the chip to be tested, and identifies the silk screen image through the trained ResNet neural network called in the MicroPython language to obtain the silk screen information, and retrieves the DRAM storage unit chip to be tested corresponding to the silk screen information. Read and write function test methods, and send them to the ATE device 400 through the wireless transmission protocol.
  • the conveyor belt transports the DRAM memory unit chip to be tested to the position of the ATE equipment 400.
  • the ATE equipment 400 is electrically connected to the chip to be tested. At this time, the ATE equipment 400 performs a read and write function test on the chip to be tested according to the received read and write function test method.
  • J750-EX is a very large scale integrated circuit (VLSI) test system with rich and powerful testing resources that can be used to meet the testing needs of the new generation of VLSI storage products.
  • VLSI very large scale integrated circuit
  • the ResNet neural network is used to identify the silk screen image of the DRAM memory unit chip to be tested, and the corresponding read and write function test method is read from the database 310 according to the identification result, and then the ATE device 400 is used according to the received
  • the read and write function test method tests the read and write function of the chip under test to realize the automation of the read and write function test of the DRAM memory unit, effectively improves the efficiency of the read and write function test, and at the same time ensures a high read and write function test accuracy.
  • the step of the ATE device 400 performing the read and write function test on the chip under test according to the received read and write function test method includes:
  • the ATE equipment 400 sets respectively according to the received reading and writing function test method:
  • S3.2 Call the preset test patterns in sequence, write data to the chip under test, and read the output data of the chip under test.
  • FIG. 2 it is a flow chart for testing the read and write functions of the ATE device 400 in this embodiment.
  • Common failure modes include: (1) hard failure or soft effect fixed to "1"/"0"; (2) open circuit or short circuit failure; (3) address decoder failure; (4) graphics sensitivity failure.
  • test patterns used include a “0” pattern (writeall_00_readall_00.pat), a write all “1” read all “1” pattern (writeall_ff_readall_ff.pat), a walking pattern (walking.pat), and a chessboard One or more types of grid graphics (checkboard.pat).
  • the method also includes the following steps: classifying the chips to be tested based on comparison verification, transporting the chips judged to have normal reading and writing functions to the first classification through a conveyor belt, and classifying the chips judged to have read and write functions. Chips with abnormal write functions are transported to the second classification via a conveyor belt, and the normal rate of the chips is counted.
  • the chips are classified according to the read and write function test results of the DRAM memory unit chips to be tested.
  • the chip under test is directly conveyed by the first conveyor belt to the first classification box, and store it as a qualified chip; if not, the chip to be tested is transported to the second classification box by the second conveyor belt, and is stored as an unqualified chip, and the pass rate of the current read and write function test is Make statistics.
  • the silk screen information includes the chip model.
  • the step of reading the reading and writing function testing method matching the silk screen information from the preset database 310 includes: according to the chip model in the silk screen information, from the preset database 310 The reading and writing function test method with the chip model tag is retrieved from the database 310 and transmitted to the ATE equipment 400 .
  • the database 310 in this embodiment stores reading and writing function test methods corresponding to different chip models.
  • This embodiment uses ResNet neural network to identify the silk screen image of the chip under test to obtain the silk screen information with the chip model, and based on the chip under test Call up the matching read and write function test method based on the chip model to achieve high test accuracy while automating the read and write function test.
  • This embodiment proposes a fully automatic DRAM storage unit read and write function test system. As shown in Figure 3, it is an architecture diagram of the fully automatic DRAM storage unit read and write function test system of this embodiment.
  • the image acquisition module 100 is used to acquire the silk screen image of the chip to be tested.
  • the identification module 200 is used to use ResNet neural network to identify the silk screen image of the chip under test, and output the silk screen information of the chip under test.
  • the reading and writing function test method reading module 300 includes a database 310, in which a reading and writing function testing method with a chip model tag is preset.
  • the read-write function test method reading module 300 is configured to read the read-write function test method matching the silk-screen information from the database 310 according to the silk-screen information.
  • the ATE equipment 400 is used to test the read and write functions of the chip under test according to the received read and write function test methods.
  • the conveyor belt is used to sequentially convey the chip to be tested through the image acquisition module 100 and the ATE equipment 400 under the action of a power mechanism.
  • the identification module 200 is equipped with a ResNet neural network called in the MicroPython language, and the image acquisition module 100, the identification module 200, the reading and writing function test method reading module 300 and the ATE device 400 are equipped with a MicroPython language. Language-invoked wireless information transfer protocol.
  • a test pattern is preset in the ATE device 400 for testing and verifying the read and write functions of the chip under test.
  • the test pattern includes one or more of a "0" pattern, a writing all “1” pattern and a reading all “1” pattern, a walking pattern, and a checkerboard pattern.
  • the recognition module 200 completes the recognition and outputs the silk screen information of the chip to be tested
  • the recognized silk screen information is transmitted to the read and write function test method reading module 300 .
  • the silk screen information includes the chip model.
  • the reading and writing function test method reading module 300 reads the reading and writing function testing method that matches the silk screen information from the database 310 according to the received silk screen information. Specifically, the reading and writing function test method reading module 300 retrieves the reading and writing function testing method with the chip model tag from the preset database 310 according to the chip model in the silk screen information, and transmits it to the ATE equipment 400 Perform reading and writing function tests.
  • the ATE equipment 400 uses the J750-EX series test machine, which performs the read and write function test on the chip under test according to the received read and write function test method.
  • the ATE device 400 After completing the connection and setting of the chip under test, the ATE device 400 sequentially calls the preset test pattern, writes data to the chip under test, reads the output data of the chip under test, and then transfers the output data of the chip under test. The output data is compared and verified with the corresponding expected readout data. If the comparison is consistent, it is judged that the read and write function of the chip under test is normal; otherwise, it is judged that the read and write function of the chip under test is abnormal.
  • the system further includes an electrostatic shielding cover, which is used to cover the ATE equipment 400 and the periphery of the chip under test when the chip under test is transferred to the ATE equipment 400 position.
  • the additional electrostatic shielding cover in this embodiment is used to reduce various failures caused by static electricity during the testing process of DRAM memory unit chips.
  • the system also includes a transmission control module, which is connected to the ATE equipment 400 and the power mechanism; the transmission control module controls the start and stop of the conveyor belt by controlling the start and stop of the power mechanism. and transmission speed.
  • the conveyor control module controls the conveyor belt to stop working.
  • the ATE device 400 After the ATE device 400 completes the read and write function test, the ATE device 400 sends a test result signal to the transmission control module.
  • the transmission control module controls the conveyor belt to transmit the chip under test to the first classification port or the second classification according to the test result signal. mouth.
  • a first classification box and a second classification box are provided on one side of the first classification port and the second classification port, respectively used to classify the current batch of DRAM memory unit chips that pass the read and write function test and those that do not pass the read and write function test. Storage.
  • the ATE equipment 400 performs statistics on the normal rate of reading and writing function tests of the current batch of DRAM memory unit chips, which facilitates the staff's statistics and analysis work.
  • This embodiment proposes a fully automatic DRAM storage unit reading and writing function testing system, which includes a memory and a processor, and the memory stores a computer program.
  • this embodiment also proposes a fully automatic DRAM storage unit reading and writing function testing system, which includes a storage medium on which a computer program is stored.

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Abstract

La présente invention se rapporte au domaine technique du test de circuit intégré. L'invention concerne un procédé et un système entièrement automatiques pour tester des fonctions de lecture et d'écriture d'une cellule de stockage DRAM. Le procédé comprend les étapes suivantes : acquisition d'une image de sérigraphie d'une puce à tester, et mise en œuvre d'une reconnaissance sur l'image de sérigraphie au moyen d'un ResNet, de façon à obtenir des informations de sérigraphie ; lecture, selon les informations de sérigraphie et dans une base de données prédéfinie, d'un procédé de test de fonction de lecture et d'écriture qui correspond aux informations de sérigraphie, et transmission du procédé de test de fonction de lecture et d'écriture à un ATE ; et connexion électrique de l'ATE à ladite puce, et l'ATE mettant en œuvre un test de fonction de lecture et d'écriture sur ladite puce selon le procédé de test de fonction de lecture et d'écriture reçu. Dans la présente invention, l'automatisation du travail de test de fonction de lecture et d'écriture pour une cellule de stockage de DRAM est réalisée, l'efficacité du travail de test de fonction de lecture et d'écriture est efficacement augmentée, et un taux de précision relativement élevé du test de fonction de lecture et d'écriture est également assuré.
PCT/CN2022/094352 2022-05-23 2022-05-23 Procédé et système entièrement automatiques pour tester des fonctions de lecture et d'écriture d'une cellule de stockage dram WO2023225772A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050204234A1 (en) * 2004-03-12 2005-09-15 Infineon Technologies Ag Method and apparatus for the memory self-test of embedded memories in semiconductor chips
CN106847343A (zh) * 2016-12-08 2017-06-13 上海精密计量测试研究所 基于自动测试设备的mram存储器的测试方法
CN110961364A (zh) * 2019-12-18 2020-04-07 浪潮(北京)电子信息产业有限公司 一种基于fpga平台的芯片全功能自测系统及其方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050204234A1 (en) * 2004-03-12 2005-09-15 Infineon Technologies Ag Method and apparatus for the memory self-test of embedded memories in semiconductor chips
CN106847343A (zh) * 2016-12-08 2017-06-13 上海精密计量测试研究所 基于自动测试设备的mram存储器的测试方法
CN110961364A (zh) * 2019-12-18 2020-04-07 浪潮(北京)电子信息产业有限公司 一种基于fpga平台的芯片全功能自测系统及其方法

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