CN114822678A - Method and system for testing read-write function of full-automatic DRAM (dynamic random Access memory) storage unit - Google Patents
Method and system for testing read-write function of full-automatic DRAM (dynamic random Access memory) storage unit Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuit testing, and provides a method and a system for testing the read-write function of a full-automatic DRAM storage unit, wherein the method comprises the following steps: collecting a silk-screen image of a chip to be tested, and identifying the silk-screen image by adopting a ResNet neural network to obtain silk-screen information; reading a read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information, and transmitting the read-write function test method to ATE equipment; and electrically connecting the ATE equipment with the chip to be tested, and carrying out read-write function test on the chip to be tested by the ATE equipment according to the received read-write function test method. The invention realizes the automation of the test work of the read-write function of the DRAM storage unit, effectively improves the test work efficiency of the read-write function and simultaneously ensures higher test accuracy of the read-write function.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to a method and a system for testing read-write functions of a fully-automatic DRAM (dynamic random access memory) storage unit.
Background
The read-write function test of the DRAM memory unit is usually established on a fault model of the DRAM memory unit, and the common fault model mainly comprises the following steps: (1) a fault model based on a fixed unit; (2) testing a fault model based on the memory of the bridging defect; (3) testing a fault model based on the memory associated with the defect; (4) data retention failure models, and the like. The failure modes exhibited by these failure models are mainly: (1) hard failure or soft failure fixed as "1"/"0"; (2) open or short circuit failure; (3) an address decoder failure; (4) pattern sensitivity failure: in some test patterns, the memory may not work reliably, etc.
The read-write function test of the memory unit of the DRAM chip needs to invest a lot of time and manpower and material resources, and even then, the possibility of manual errors is still high. At present, Test workers aim at automation of a Test process, and provide an ATE (Automatic Test Equipment, integrated circuit Automatic tester) for testing a chip, and by setting values of a device working power supply, an input level, an output level, a reference level and a load current, setting a power-on sequence of the device, setting distribution of address signals, control signals and data signals of the device in a data format, a time sequence, a channel and a control register, respectively performing erasing and verification of a full chip, erasing and verification of a single sector, verifying a write state register, verifying a read chip ID, verifying a read-write function of a full chip storage unit, verifying a write protection, verifying a direct current parameter and verifying an alternating current parameter. However, the method still needs the whole participation of test workers, and the problems of low efficiency and high error probability still exist for the test work of the read-write function of the DRAM storage unit.
Disclosure of Invention
The invention provides a method and a system for testing the read-write function of a fully-automatic DRAM storage unit, aiming at overcoming the defects of low efficiency and high error probability of the traditional test for the read-write function of the DRAM storage unit.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a full-automatic DRAM memory cell read-write function test method comprises the following steps:
collecting a silk-screen image of a chip to be tested, and identifying the silk-screen image by adopting a ResNet neural network to obtain silk-screen information;
reading a read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information, and transmitting the read-write function test method to ATE equipment;
and electrically connecting the ATE equipment with the chip to be tested, and carrying out read-write function test on the chip to be tested by the ATE equipment according to the received read-write function test method.
As a preferred scheme, the step of performing the read-write function test on the chip to be tested by the ATE device according to the received read-write function test method includes: the ATE equipment respectively sets values of a working power supply, an input level, an output level, a reference level and a load current applied to a chip to be tested according to the received read-write function test method; setting the power-on sequence of the chip to be tested; setting the data format, the time sequence, the channel and the distribution of a control register of a control signal, an address signal and a data signal of a chip to be tested; sequentially calling a preset test pattern, writing data into a chip to be tested, and reading output data of the chip to be tested; comparing and verifying the output data of the chip to be tested with the corresponding expected read data, and if the comparison is consistent, judging that the read-write function of the chip to be tested is normal; otherwise, judging that the read-write function of the chip to be tested is abnormal.
Preferably, the preset test pattern includes one or more of a "0" pattern, a write all "1" and read all "1" pattern, a walking pattern and a checkerboard pattern.
Preferably, the method further comprises the following steps: and classifying the chips to be detected according to comparison and verification, transporting the chips judged to be normal in read-write function to a first classification through a conveyor belt, transporting the chips judged to be abnormal in read-write function to a second classification through the conveyor belt, and counting the normal rate of the chips.
As a preferred scheme, the step of reading the read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information comprises the following steps: the silk-screen information comprises the model of the chip; and calling a read-write function test method with the chip model label from a preset database according to the chip model in the silk-screen information, and transmitting the read-write function test method to ATE equipment.
Furthermore, the invention also provides a full-automatic DRAM storage unit read-write function test system, and a method provided by any of the technical schemes. The system comprises an image acquisition module, an identification module, a read-write function test method reading module, ATE equipment, a conveyor belt and a power mechanism.
The image acquisition module is used for acquiring a silk-screen image of the chip to be detected; the identification module is used for identifying the silk-screen image of the chip to be detected by adopting a ResNet neural network and outputting the silk-screen information of the chip to be detected; the read-write function test method reading module comprises a database, and a read-write function test method with a chip model label is preset in the database; the read-write function test method reading module is used for reading a read-write function test method matched with the silk-screen information from the database according to the silk-screen information; the ATE equipment is used for carrying out read-write function test on the chip to be tested according to the received read-write function test method; the conveyer belt is used for conveying the chip that awaits measuring in proper order under power unit's effect and passes through image acquisition module and ATE equipment.
As the preferred scheme, the system still includes the electrostatic shield cover, the electrostatic shield cover is used for when the chip that awaits measuring conveys to ATE equipment position, the cover is established ATE equipment and the chip periphery that awaits measuring.
As a preferred scheme, the system further comprises a transmission control module, wherein the transmission control module is connected with the ATE equipment and the power mechanism; the conveying control module controls the starting and stopping of the conveying belt and the conveying speed by controlling the starting and stopping of the power mechanism; when the conveyor belt conveys the chip to be tested to the position of the ATE equipment, the conveying control module controls the conveyor belt to stop working; and after the ATE equipment completes the read-write function test, the ATE equipment sends a test result signal to the transmission control module, and the transmission control module controls the conveyor belt to transmit the chip to be tested to the first classification port or the second classification port according to the test result signal.
As a preferred scheme, a test pattern is preset in the ATE device and used for performing read-write function test verification on a chip to be tested; the test patterns comprise one or more of 0 patterns, 1-writing and 1-reading patterns, walking patterns and checkerboard patterns.
The invention further provides a system for testing the read-write function of the full-automatic DRAM storage unit, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to realize the steps of the method for testing the read-write function of the full-automatic DRAM storage unit provided by any technical scheme.
Furthermore, the present invention also provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method for testing the read-write function of the fully automatic DRAM memory unit according to any of the above technical solutions.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that: the method and the device identify the silk-screen image of the DRAM storage unit chip to be tested by adopting the ResNet neural network, read and call the corresponding read-write function test method from the database according to the identification result, and then adopt ATE equipment to test the read-write function of the chip to be tested according to the received read-write function test method, thereby realizing the automation of the read-write function test work of the DRAM storage unit, effectively improving the read-write function test work efficiency and simultaneously ensuring higher read-write function test accuracy.
Drawings
FIG. 1 is a flow chart of a method for testing read/write functions of a fully automatic DRAM memory cell according to an embodiment of the present invention.
Fig. 2 is a flowchart of performing read/write function testing on ATE equipment according to an embodiment of the present invention.
FIG. 3 is a block diagram of a fully automatic DRAM memory cell read/write function test system according to an embodiment of the present invention.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described with reference to the drawings and the embodiments.
Example 1
The embodiment provides a method for testing read-write function of a fully automatic DRAM memory cell, and is a flowchart of the method for testing read-write function of the fully automatic DRAM memory cell of the embodiment, as shown in fig. 1.
The embodiment provides a method for testing the read-write function of a full-automatic DRAM storage unit, which comprises the following steps:
and S1, acquiring a silk-screen image of the chip to be detected, and identifying the silk-screen image by adopting a ResNet neural network to obtain silk-screen information.
And S2, reading the read-write function test method matched with the silk-screen information from a preset database 310 according to the silk-screen information, and transmitting the read-write function test method to ATE equipment 400.
And S3, electrically connecting the ATE equipment 400 with the chip to be tested, wherein the ATE equipment 400 performs read-write function test on the chip to be tested according to the received read-write function test method.
In one implementation, a number of DRAM memory cell chips to be tested are placed on a conveyor belt and passed through an OpenMV camera and J750-EX series ATE equipment 400 in sequence.
The OpenMV camera acquires a silk-screen image of a chip to be tested, identifies the silk-screen image through a ResNet neural network called by MicroPython language and used for completing training to obtain silk-screen information, calls a read-write function test method of the DRAM memory cell chip to be tested corresponding to the silk-screen information, and sends the read-write function test method to the ATE equipment 400 through a wireless transmission protocol.
The conveyor belt conveys the DRAM memory cell chip to be tested to the position of the ATE device 400, the ATE device 400 is electrically connected with the chip to be tested, and at the moment, the ATE device 400 performs read-write function test on the chip to be tested according to the received read-write function test method.
J750-EX is a very large scale integrated circuit (VLSI for short) test system, has abundant, powerful test resources, can be used for meeting the test requirement of the new generation of VLSI storage product, presume the relevant parameter of test and executive program on J750-EX, can meet the read-write test requirement of DRAM memory cell well.
In this embodiment, the screen-printed image of the DRAM memory cell chip to be tested is identified by using the ResNet neural network, and the corresponding read-write function test method is read and called from the database 310 according to the identification result, and then the read-write function test is performed on the chip to be tested by using the ATE device 400 according to the received read-write function test method, so that the automation of the read-write function test work of the DRAM memory cell is realized, the read-write function test work efficiency is effectively improved, and the higher read-write function test accuracy is ensured.
In an optional embodiment, the step of performing the read-write function test on the chip to be tested by the ATE device 400 according to the received read-write function test method includes:
s3.1, the ATE equipment 400 respectively sets the following steps according to the received read-write function test method:
(1) the values of the working power supply, the input level, the output level, the reference level and the load current applied to the chip to be tested;
(2) electrifying the chip to be tested;
(3) and distributing control signals, address signals and data signals of the chip to be tested in data format, time sequence, channel and control register.
And S3.2, calling preset test patterns in sequence, writing data into a chip to be tested, and reading output data of the chip to be tested.
S3.3, comparing and verifying the output data of the chip to be tested with the corresponding expected read data: if the comparison is consistent, judging that the read-write function of the chip to be tested is normal; otherwise, judging that the read-write function of the chip to be tested is abnormal.
Fig. 2 is a flowchart illustrating the read/write function test performed by the ATE apparatus 400 according to this embodiment.
And aiming at the fault mode shown by the common fault model of the DRAM storage unit, a read-write function test is carried out by adopting a test picture. Wherein common failure modes include: (1) hard failure or soft failure fixed as "1"/"0"; (2) open or short circuit failure; (3) an address decoder failure; (4) pattern sensitivity failure.
When the read-write function test of the full-chip memory unit is carried out on the DRAM memory unit, the above fault modes are mainly tested in a mode of setting different test patterns.
In an alternative embodiment, the test patterns used include one or more of "0" patterns (write _00_ readall _00.pat), write all "1" read all "1" patterns (write _ ff _ readall _ ff.pat), walk patterns (walking.pat), checkerboard patterns (checkboard.pat).
Further, in an optional embodiment, the method further comprises the following steps: and classifying the chips to be detected according to comparison and verification, transporting the chips judged to be normal in read-write function to a first classification through a conveyor belt, transporting the chips judged to be abnormal in read-write function to a second classification through the conveyor belt, and counting the normal rate of the chips.
In this embodiment, the chips are classified according to the read-write function test result of the DRAM memory cell chip to be tested.
In a specific implementation process, judging whether all test items pass according to the test result of the read-write function of the J750-EX DRAM chip, and classifying the test items through a double-path conveyor belt; if yes, directly conveying the chip to be tested to a first sorting box through a first conveyor belt, and storing the chip to be tested as a qualified chip; if not, the chip to be tested is conveyed to a second classification box by a second path of conveying belt to be stored as an unqualified chip, and the passing rate of the current read-write function test is counted.
Further, in an optional embodiment, the silk-screen information includes a chip model.
In this embodiment, the step of reading, from a preset database 310, a read-write function test method matched with the screen printing information according to the screen printing information includes: and calling a read-write function test method with the chip model label from a preset database 310 according to the chip model in the silk-screen information, and transmitting the read-write function test method to ATE (automatic test equipment) 400.
In this embodiment, the ResNet neural network is used to identify the silk-screen image of the chip to be tested, so as to obtain the silk-screen information with the chip model, and a matched read-write function test method is called according to the chip model of the chip to be tested, so that the read-write function test automation is realized and the higher test accuracy is ensured.
Example 2
The embodiment provides a system for testing read/write functions of a fully automatic DRAM memory cell, as shown in fig. 3, which is an architecture diagram of the system for testing read/write functions of a fully automatic DRAM memory cell of the embodiment.
The system for testing the read-write function of the fully-automatic DRAM memory unit provided by the embodiment comprises:
and the image acquisition module 100 is used for acquiring a silk-screen image of the chip to be detected.
And the identification module 200 is configured to identify the silk-screen image of the chip to be tested by using a ResNet neural network, and output silk-screen information of the chip to be tested.
The read/write function testing method reading module 300 includes a database 310, and the read/write function testing method with a chip model label is preset in the database 310.
The read-write function test method reading module 300 is configured to read, from the database 310, a read-write function test method matched with the screen printing information according to the screen printing information.
And the ATE device 400 is configured to perform read-write function testing on the chip to be tested according to the received read-write function testing method.
And the conveying belt is used for sequentially conveying the chips to be tested through the image acquisition module 100 and the ATE equipment 400 under the action of the power mechanism.
In a specific implementation process, a ResNet neural network called in the language of python is disposed inside the identification module 200, and a wireless information transmission protocol called in the language of python is disposed inside the image acquisition module 100, the identification module 200, the read-write function test method reading module 300, and the ATE device 400.
In this embodiment, the ATE device 400 is preset with a test pattern for performing read/write function test verification on the chip to be tested.
Wherein the test patterns comprise one or more of '0' patterns, all '1' writing and all '1' reading patterns, walking patterns and checkerboard patterns.
Further, after the identification module 200 identifies and outputs the screen printing information of the chip to be tested, the identified screen printing information is transmitted to the read/write function test method reading module 300. And the silk-screen information comprises the model of the chip.
The read-write function test method reading module 300 reads the read-write function test method matched with the screen printing information from the database 310 according to the received screen printing information. Specifically, the read-write function test method reading module 300 calls a read-write function test method with the chip model label from a preset database 310 according to the chip model in the screen printing information, and transmits the read-write function test method to the ATE device 400 for read-write function test.
In a specific implementation process, the ATE apparatus 400 employs a J750-EX series tester, and when performing a read-write function test on a chip to be tested according to a received read-write function test method, the ATE apparatus 400 sets values of a working power supply, an input level, an output level, a reference level, and a load current applied to the chip to be tested, respectively, according to the received read-write function test method; setting the power-on sequence of the chip to be tested; and setting the data format, the time sequence, the channel and the distribution of the control register of the control signal, the address signal and the data signal of the chip to be tested.
After the connection and setting of the chip to be tested are completed, the ATE equipment 400 calls preset test patterns in sequence, writes data into the chip to be tested, reads output data of the chip to be tested, compares the output data of the chip to be tested with corresponding expected read data for verification, and judges that the read-write function of the chip to be tested is normal if the comparison is consistent; otherwise, judging that the read-write function of the chip to be tested is abnormal.
In an alternative embodiment, the system further comprises an electrostatic shield configured to cover the periphery of the ATE apparatus 400 and the chips to be tested when the chips to be tested are transferred to the ATE apparatus 400.
The electrostatic shielding cover is additionally arranged in the embodiment and is used for reducing various faults of the DRAM storage unit chip caused by electrostatic problems in the test process.
In another alternative embodiment, the system further comprises a transfer control module, said transfer control module being connected to said ATE apparatus 400 and to the power mechanism; the conveying control module controls the starting and stopping of the conveying belt and the conveying speed by controlling the starting and stopping of the power mechanism.
When the conveyor belt conveys the chip to be tested to the position of the ATE equipment 400, the conveying control module controls the conveyor belt to stop working.
After the ATE device 400 completes the read-write function test, the ATE device 400 sends a test result signal to the transmission control module, and the transmission control module controls the transmission belt to transmit the chip to be tested to the first classification port or the second classification port according to the test result signal.
And a first sorting box and a second sorting box are arranged on one side of the first sorting port and one side of the second sorting port and are respectively used for sorting and storing the DRAM memory cell chips which pass the read-write function test and do not pass the read-write function test in the current batch.
Further, in this embodiment, the ATE device 400 performs statistics on the normal rate of the read-write function tests of the DRAM memory cell chips of the current batch, so as to facilitate statistics and analysis work of the staff.
Example 3
The embodiment provides a fully automatic DRAM memory cell read-write function test system, which comprises a memory and a processor, wherein the memory stores a computer program.
And when the processor executes the computer program, the steps of the method for testing the read-write function of the fully-automatic DRAM storage unit are realized according to the embodiment 1.
Furthermore, this embodiment further provides a fully automatic DRAM memory cell read/write function test system, which includes a storage medium having a computer program stored thereon.
The computer program, when executed by a processor, implements the steps of the method for testing read and write functions of a fully automatic DRAM memory cell of embodiment 1.
The same or similar reference numerals correspond to the same or similar parts;
the terms describing positional relationships in the drawings are for illustrative purposes only and are not to be construed as limiting the patent;
it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A full-automatic DRAM memory cell read-write function test method is characterized by comprising the following steps:
collecting a silk-screen image of a chip to be tested, and identifying the silk-screen image by adopting a ResNet neural network to obtain silk-screen information;
reading a read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information, and transmitting the read-write function test method to ATE equipment;
and electrically connecting the ATE equipment with the chip to be tested, and carrying out read-write function test on the chip to be tested by the ATE equipment according to the received read-write function test method.
2. The method for testing the read-write function of the fully automatic DRAM memory unit according to claim 1, wherein the step of the ATE device testing the read-write function of the chip to be tested according to the received read-write function test method comprises the following steps:
the ATE equipment respectively sets values of a working power supply, an input level, an output level, a reference level and a load current applied to a chip to be tested according to the received read-write function test method; setting the power-on sequence of the chip to be tested; setting the data format, the time sequence, the channel and the distribution of a control register of a control signal, an address signal and a data signal of a chip to be tested;
sequentially calling a preset test pattern, writing data into a chip to be tested, and reading output data of the chip to be tested;
comparing and verifying the output data of the chip to be tested with the corresponding expected read data, and if the comparison is consistent, judging that the read-write function of the chip to be tested is normal; otherwise, judging that the read-write function of the chip to be tested is abnormal.
3. The method as claimed in claim 2, wherein the predetermined test pattern includes one or more of "0" pattern, write all "1" and read all "1" pattern, walking pattern, and checkerboard pattern.
4. The method for testing read-write functions of a fully automatic DRAM memory cell of claim 2, further comprising the steps of: and classifying the chips to be detected according to comparison and verification, transporting the chips judged to be normal in read-write function to a first classification through a conveyor belt, transporting the chips judged to be abnormal in read-write function to a second classification through the conveyor belt, and counting the normal rate of the chips.
5. The method for testing the read-write function of the fully automatic DRAM memory unit according to any one of claims 1 to 4, wherein the step of reading the read-write function test method matched with the silk-screen information from a preset database according to the silk-screen information comprises the following steps:
the silk-screen information comprises the model of the chip;
and calling a read-write function test method with the chip model label from a preset database according to the chip model in the silk-screen information, and transmitting the read-write function test method to ATE equipment.
6. A fully automatic DRAM memory cell read-write function test system, characterized in that, the method of any claim 1-5 is applied; wherein the system comprises:
the image acquisition module is used for acquiring a silk-screen image of the chip to be detected;
the identification module is used for identifying the silk-screen image of the chip to be detected by adopting a ResNet neural network and outputting the silk-screen information of the chip to be detected;
the read-write function test method reading module comprises a database, wherein a read-write function test method with a chip model label is preset in the database;
the read-write function test method reading module is used for reading a read-write function test method matched with the silk-screen information from the database according to the silk-screen information;
the ATE equipment is used for carrying out read-write function test on the chip to be tested according to the received read-write function test method;
and the conveying belt is used for sequentially conveying the chips to be detected to pass through the image acquisition module and the ATE equipment under the action of the power mechanism.
7. The fully automatic DRAM memory cell read-write functionality test system of claim 6, further comprising an electrostatic shield for shielding the periphery of the ATE device and the chips to be tested when the chips to be tested are transferred to the ATE device location.
8. The fully automatic DRAM memory cell read-write functionality test system of claim 6, further comprising a transfer control module, said transfer control module being connected to said ATE device and power mechanism; the conveying control module controls the starting and stopping of the conveying belt and the conveying speed by controlling the starting and stopping of the power mechanism;
when the conveyor belt conveys the chip to be tested to the position of the ATE equipment, the conveying control module controls the conveyor belt to stop working;
and after the ATE equipment completes the read-write function test, the ATE equipment sends a test result signal to the transmission control module, and the transmission control module controls the conveyor belt to transmit the chip to be tested to the first classification port or the second classification port according to the test result signal.
9. The system of claim 6, wherein the ATE device is pre-configured with test patterns for performing read/write test verification on the chip under test; the test patterns comprise one or more of 0 patterns, 1-writing and 1-reading patterns, walking patterns and checkerboard patterns.
10. A full-automatic DRAM storage unit read-write function test system, which comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that the processor implements the steps of the full-automatic DRAM storage unit read-write function test method according to any one of claims 1-5 when executing the computer program.
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2022
- 2022-05-23 CN CN202210564072.3A patent/CN114822678A/en active Pending
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