!2253〇7 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於一種測試裝置，特別是指一種用於半 導體構裝元件的自動化分類測試裝置。 【先前技術】 10 15 半導體最終測試製程乃是於半導體元件構裝後，藉由 一測試設備（TESTER)測試構裝完成產品之電性功能，以保 証出廠之半導體構裝元件在功能上的完整性，並對已測試 的產品依其電性功能分類篩選，以作為半導體構裝元件不 同等級產品的評價依據。 然而，隨著科技日新月異，許多半導體晶片的功能愈 來愈多樣化，運行速度也錢攀高。現㈣試設備之功 能，已逐漸不敷該半導體晶片使用，縱算有廠商適時推出 相對應的測試設備，其價格也相當昂責，進而使得業者的 測試成本大增。 凡^π，微驗牛導體晶片的各項功 20 -----W W ό又询焚在硬體上的支援之外，還需要編寫診斷的測試軟體，以 軟體模擬該半導體晶片真㈣工作環境，確保半導體晶片 的各項功能可按照半導體元件_設計的要求工作。 但是，開發-個測試程式，f要耗f相當長的時間， +吊:個半㈣晶片_試程式從無到可穩定使用，大笑 二“年’這對產品生命週期較短的半導體晶片來說，可 p傷而且’無論測試程式編寫的 它還是無法找出部份㈣統層㈣題，⑽量產的;^體 以 4 1225307 5 晶片並非可以單獨運行，它必須是和其他的電子元件或半 導體元件相互配合’才能發揮應有的功能。也正因為如 此，其他配合元件的不可控因子太多，測試程式無法一一 考慮到該半導體晶片在系統級（System Level)3t境層次所 面6¾的問題。 10 田》亥項半導體晶片上的功能和事件出現某種在元件 測試過程巾從未遇到過的順序或組合時，可能就會產生使 用上的問題。如果這些問題出現太多（或者在執行重要任務 的產品中僅僅偶然出現），用戶將會認為這些產品不可靠甚 至是不穩^。也就是說’經過完整的半導體最終測試製程 測試之後，並無法完全暴露半導體晶片中系統級的相互作 用問題’進而導致經過測試之後還有誤判的結果產生。【發明内容】 15 因此’本發明之目的’是在提供—種可降低測試成 本，並節省測試時間且具有降低產品誤判率 元件之自動化測試裝置。 表 20 人.於是，本發明半導體構裝元件之自動化測試裝置，包 3·工作平台、一供料單元、一輸送單亓、错 一 别V早兀、一第一測試 早7°、一第二測試單元，及一出料單元。 该工作平台具有一第一測試區 及一第二測試區。該 (σσ ο 與該工作平台連接，可輪出複數待測試之半導體 構h件。該輪送單元架設於該卫作平台上，且是 在該工作平台上進行三度空間移動，並能將:: 枓早兀輸出之半導構裝元件運送至預定的位置。 5 該第一測試單元設置於該工作平台之第一測試區 内、，，並具有-賴彳，該測試埠可接受該輸送單元所運送 之半導體構裝元件，並對該半導體構裝元件進行基本電性 〆則式。、該第二測試單元具有至少-設置於該第二測試區内 的测試公板，每-測試公板具有—測試插座，可接受該輪 4忒置所運送已進行完基本電性測試之半導體構裝元 並對"亥半導體構裝元件進行公板測試。出料單元與該 工作平台連接設置，可供完成該公板測試之複數半導體構 裝元件置放。 本毛月之功效在於該基本電性測試可提供半導體構 扁几件之電性量測功能，而該公板測試是以發表該半導體 構裝7G件所認證之同步發表的公板，作為測試中心，取代 叩貴的測試設備’顧時簡化測試流程，以達到降低測試 成本與測試時間，並同時提高半導體測試之錯誤涵蓋率的 功效。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之較佳實施例的詳細說明中，將可清楚 的明白。 參閱圖1、2,本發明半導體構裝元件之自動化測試裝 置適用於封袭後的半導體測試製程，該半導體構裝元件 之自動化測試裝置的較佳實施例包含：一工作平台2、-供料單元3、-輪送單元4、—第—測試單元5、—第二測 試單元6，及一出料單元7。 6 1225307 一—亥工作平台2上具有一範圍較小的第一測試區21，及 3圍較大的第二測試區22。該供料單幻設置於該工作 ^台2前端，而與該工作平台2鄰接，並具有一供料匿31。 δ亥供料E 内可堆疊容置複數半導體承載盤i，而每—半 導體承載盤1上裝填有複數待測試之半導體構裝元件U。 在本較佳實施例中，該供料單元3更具有一預熱架 32，該預熱架32可以獨立提供昇溫加熱功能，在高溫測 試時，藉由該輸送單元4將該複數半導體構裝元件u移動 至該預熱架32上進行預先加熱。 忒輸送單元4架設於該工作平台2上，並具有一機器 手臂41，該機器手臂41是可程式化控制地在該工作平台 2上進行三度空間移動，以將該供料單元3輸出之半導構 裝凡件11運送至預定的位置。在本較佳實施例中，該機器 手臂41上具有二吸取頭411，該二吸取頭411可以真空吸 引的方式自該半導體承載盤1上吸取該待測試之半導體構 裝元件11，並移動運送至指定的位置。 配合參閱圖3、4，該第一測試單元5設置於該工作平 台2之第一測試區21下方，並具有一測試埠5丨。該測試 埠5 1可供一半導體構裝元件容置丨丨，並對該半導體構裝 元件11進行基本電性測試。 在此，應注意的是，該第一測試單元5之基本電性測 試是包括開路/短路測試（OPEN/SHORT TEST)，以及電源 短路測試（POWER SHORT test)。但實際實施時，也可以包 括輸出最大漏電流/輸出最小漏電流測試（I〇h/i〇l 7 1225307 TEST)、總體電流測試（GR〇ss IDD TEST)、靜態電流測試! 2253〇7. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a test device, and more particularly to an automatic classification test device for semiconductor structural components. [Previous technology] 10 15 The final test process of semiconductors is to complete the electrical functions of the product through a test device (TESTER) after the semiconductor device is assembled, so as to ensure the functional integrity of the factory-made semiconductor assembly components. The products that have been tested are classified according to their electrical functions to serve as the basis for evaluating different grades of semiconductor components. However, with the rapid development of technology, the functions of many semiconductor wafers are becoming more and more diversified, and the operating speed is also increasing. The function of the test equipment is gradually inadequate for the use of this semiconductor chip. Even if a manufacturer introduces the corresponding test equipment in a timely manner, its price is also quite heavy, which further increases the test cost of the industry. Where ^ π, the micro-testing of the various functions of the conductor chip 20 ----- WW In addition to the support on the hardware, you also need to write diagnostic test software to simulate the true work of the semiconductor chip Environment to ensure that the various functions of the semiconductor wafer can work in accordance with the requirements of the semiconductor component design. However, to develop a test program, f will take f a long time, + hanging: a half a chip_test program from nothing to stable use, laugh 2 "years" This is a short product life cycle semiconductor chip For example, it can be damaged and 'whether it is written by the test program or it cannot find some system level problems, it is not mass-produced; the chip is not able to run independently. It must be used with other electronics. Components or semiconductor components must cooperate with each other in order to play their proper function. Because of this, there are too many uncontrollable factors of other matching components, and the test program cannot consider the semiconductor chip at the system level (System Level) 3t level. Face 6¾ problems. 10 Tian "Hai Xiang semiconductor wafer function and events in a certain order or combination never encountered before the component test process, may cause problems in use. If these problems appear too Many (or only occasionally appear in products that perform important tasks), users will think these products are unreliable or even unstable ^. That is, 'the most complete semiconductor After the final test process test, the system-level interaction problem in the semiconductor wafer cannot be fully exposed, which leads to misjudgment results after the test. [Summary of the Invention] 15 Therefore, the purpose of the present invention is to provide a kind of Automated test device that reduces test cost and saves test time and has reduced product misjudgment rate. Table 20 people. So, the automatic test device for semiconductor structured components of the present invention, including 3. working platform, a feeding unit, a conveyor Single, wrong, different V early, a first test 7 °, a second test unit, and a discharge unit. The working platform has a first test area and a second test area. The (σσ ο Connected to the work platform, a plurality of semiconductor structures to be tested can be rotated. The carousel unit is set up on the satellite platform, and it can move in three degrees on the work platform, and can: ::: 早The semi-conducting structural components outputted by the unit are transported to a predetermined position. 5 The first test unit is located in the first test area of the work platform, and has- The test port can accept the semiconductor structured components transported by the transport unit, and perform a basic electrical rule for the semiconductor structured components. The second test unit has at least-a test set in the second test area. Male board, each-test male board has a test socket, which can accept the semi-conductor components that have been subjected to the basic electrical test carried by the wheel set and perform a public-plate test on the semiconductor component. The unit is connected to the work platform and can be used to place a plurality of semiconductor structured components for the public board test. The effect of this gross month is that the basic electrical test can provide the electrical measurement function of several semiconductor structures. The public board test is a public board published simultaneously with the certification of the 7G of the semiconductor structure. As a test center, it replaces expensive test equipment and simplifies the test process to reduce test costs and test time. Power to improve error coverage in semiconductor testing. [Embodiment] The foregoing and other technical contents, features, and effects of the present invention will be clearly understood in the following detailed description of preferred embodiments with reference to the drawings. Referring to FIGS. 1 and 2, the automated testing device for a semiconductor structured component of the present invention is suitable for a semiconductor test process after being sealed. A preferred embodiment of the automated testing device for a semiconductor structured component includes: a working platform 2, -feeding The unit 3, the carousel unit 4, the first test unit 5, the second test unit 6, and a discharge unit 7. 6 1225307 The 1-Ha work platform 2 has a first test area 21 with a smaller range and a second test area 22 with a larger area. The feeding list is arranged at the front end of the working platform 2 and is adjacent to the working platform 2 and has a feeding pan 31. In the δH feed E, a plurality of semiconductor carrier trays i can be stacked, and each semiconductor carrier tray 1 is filled with a plurality of semiconductor structure elements U to be tested. In this preferred embodiment, the feeding unit 3 further has a preheating rack 32, which can independently provide a heating function. During a high temperature test, the plurality of semiconductors are assembled by the transporting unit 4. The element u is moved to the preheating rack 32 to be preheated.忒 The conveying unit 4 is set up on the work platform 2 and has a robot arm 41. The robot arm 41 is programmable in a three-dimensional space on the work platform 2 to output the feeding unit 3. The semiconducting member 11 is transported to a predetermined position. In the preferred embodiment, the robot arm 41 has two pick-up heads 411. The two pick-up heads 411 can suck the semiconductor structural component 11 to be tested from the semiconductor carrier 1 in a vacuum suction manner, and move and transport them. To the specified position. With reference to Figs. 3 and 4, the first test unit 5 is disposed below the first test area 21 of the work platform 2 and has a test port 5 丨. The test port 51 can be used for accommodating a semiconductor structured component, and a basic electrical test of the semiconductor structured component 11 is performed. Here, it should be noted that the basic electrical test of the first test unit 5 includes an open / short test (OPEN / SHORT TEST) and a power short test (POWER SHORT test). But in actual implementation, it can also include output maximum leakage current / output minimum leakage current test (I〇h / i〇l 7 1225307 TEST), overall current test (GR〇ss IDD TEST), static current test
(STATIC IDD TEST)、動態電流測試（DYNAMIC IDD TEST)、輸出最小漏電流/輸出最大漏電流測試（IIL/nH TEST)、輸出高阻抗漏電流測試（IOZ TEST)、輸入高電位/ 輸入低電位測試（VIH/VIL TEST)，以及輸出高電位/輸出低 電位測試（VOH/VOLtest)等等。 舉例來說，以開路/短路測試（OPEN-SHORT TEST)而 吕其目的是為確保該第一測試單元與該半導體構裝元件 的接觸是否良好，同時檢查該半導體構裝線路内部是否有 開路或短路的情形。以作為分析該半導體構裝元件好壞的 依據。但是，因各種半導體構裝元件之產品特性不同，所 舄要的測试項目亦有不同’例如邏輯性ic與記憶類ic所 需的測試便有差異，而本較佳實施例僅是以一般邏輯性產 口口為例來作說明’而且縱算是同屬邏輯類ic，但產品不同 測試項目亦不盡相同，故實際實施時，應不以此為限。 5亥第一測试早元6設置於該工作平台2之第二測試區 22 ’並具有三測試公板61。每一測試公板61上具有一測 試插座611可供該半導體構裝元件丨丨置放，並對已經過基 本電性測試之半導體構裝元件η進行公板測試。但實際實 施時，該測試公板61的數量也可以僅有一個，或更多複 數個，其數量之增減並不限於本實施例所揭露。 值得一提的是，所謂公板即為針對該半導體構裝元件 Π之產品用途，以實際的電子元件及半導體元件，在_電 路板上模擬作出該半導體構裝元件U之工作環境，且其規 8 1225307 格是業界通用的標準。舉例來說，若該項待測試之半導體 構裳元件-個人電腦主機用之晶片组，則該 該個人電腦之主機板，將該晶片組安裝於該主機板上，並 執仃適當的程式，視其所輸出之功能是否符合預期，便可 5 直接判斷該待測之半導體封裝元件11好壞。 當然，這只是以該項待測試之半導體封裝元件u為晶 片組1C，所作的舉例說明。現階段的繪圖晶片、整合性通 訊晶片、網路卡，以及微處理器等等都可以通過開發適切 之公板，搭配相對於習知較為精巧的測試程式，來作公板 10 測試，並依品質等級加以分類。 而公板測試即為該半導體構裝元件u之產品功能測 ”式，並非單純以軟體模擬測試環境，而是以實體的電路板 進行測試，所以可大大降低該半導體構裝元件之誤測率。 換言之，通過此階段測試之半導體構裝元件可稱之為良 15 品。 該出料單元7設置於該工作平台2前端，而與該供料 單元3間隔相鄰，並具有複數分類匣71，可用以裝載該複 數經過測試公板61測試之半導體構裝元件η。每一分類 ! 71是依預先定義的測試結果排列設置。在本較佳實施 20 例中，該出料單元7是具有四個分類匣7卜由左至右分別 代表的是Pass Binl、Pass Bin2、功能測試失敗，及電性測 試失敗等四個分類匣71，經過該測試公板61測試之半導 體構裝元件11，便會被該輸送單元4依照測試結果輸送至 對應的分類匣71中。 9 1225307 在&第一較佳實施例中，該半導體構裝元件之自動化 測試裝置更包含一緩衝單元8，及一壓持單元9。該緩衝 單兀8没置於該工作平台2上，並具有複數緩衝座81，該 複數緩衝座81是可前後移動地分別對應設置於該測試埠 5 51與該三測試插座611前方，且每一緩衝座81上設有二 置放槽811，可供該半導體構裝元件u置放。 該壓持單元9對應設置於該三測試插座611與該測試 埠51上方，並具有四個壓持件91。在此，應注意的是， 該壓持件之數量是取決於該測試埠51與該測試插座611， 10 故實際實施時，不應侷限於本實施例之說明。 每一壓持件91是可上下移動地以真空吸引的方式自 孩綾衝座81上之置放槽811中吸取該半導體構裝元件 π，並將該半導體構裝元件n壓持置入該測試埠51或該 測試插座611中，以使該半導體構裝元件u可與該第一或 15 帛W A單元5 6緊⑨結合’避免因接觸不良導致測試 失敗。在該較佳實施例中，每一壓持件91具有一可昇溫 加熱的導熱塊911，可在吸取該半導體構裝元件u的過程 中，藉由該導熱塊9U持續給予加熱，以滿足需進行高溫 測試的半導體構裝元件U。 20 依據上述硬體架構，在下文中將說明本發明半導體構 裝元件之自動化測試裝置的實施方式。 參閱圖卜5,在說明前，應注意的是，以下的測試流 程是以常溫下之測试為例來作說明。 首先’進行步驟1〇，工作人員將複數裝載有待測試之 10 半^體構裝元件11的半導體承載盤卜依序堆疊置入該供 之供料s 31内，該供_31可提供昇降該半導 體承载盤1的功能，以輪出該半導體職元件u。 接著’進行步驟20，該輸送單元4之機器手臂41會 至該供料E Μ上方’並下降至適當高度，再以該： 盗手臂41上之二吸取頭411，分別吸取該半導體構裝元件 11後，移動至該第一測試區2 i内之緩衝座8 i上方，並將 該二吸取頭411所吸附之半導體構裝元㈣置人該二置放 槽811中。 接著，進行步驟30,該緩衝座81會往該堡持單元9 的方向移動’並停留在該第_測試區21内之遂持件Μ的 下方位置處。然後，該第-測試區21内之壓持件91合下 降至該緩衝座81 Λ，並以真空吸引的方式自該緩衝座曰81 15 上之置放# 811巾吸取該半導體構裝元件u。接著，該緩 衝座81會立即後退，此時，該壓持件91會將該半導體構 裝兀件11置人該測試琿51中’以使該半導體構裝元件u 可與該第-測試單元5緊密結合，避免因接觸不良導致測 試失敗。 20 而後，進行步驟40，當該半導體構裝元件u完成基 本電性測試之後’胃壓持# 91 t再度下降吸取，並將該 半導體構裝元件11自該測試埠51中脫離。同—時間，該 機器手臂41會將該緩衝座81上另一置放槽811内的半導 體構裝元件11，吸取移至該前一個置放槽内811内。 接著，進行步驟50,該緩衝座81會再度向前移動並 11 1225307 將該空的置放槽811停留在該屋持件 該:广電'_之半導體構 5(STATIC IDD TEST), dynamic current test (DYNAMIC IDD TEST), output minimum leakage current / output maximum leakage current test (IIL / nH TEST), output high impedance leakage current test (IOZ TEST), input high potential / input low potential Test (VIH / VIL TEST), and output high potential / output low potential test (VOH / VOLtest) and so on. For example, with the OPEN-SHORT TEST test, Lu aims to ensure that the first test unit is in good contact with the semiconductor component, and at the same time check whether there is an open circuit or Short circuit situation. This is used as a basis for analyzing the quality of the semiconductor component. However, due to the different product characteristics of various semiconductor components, the required test items are different. For example, the tests required for logical ic and memory ic are different, and the preferred embodiment is only a general The logical production port is taken as an example to illustrate 'and even if they belong to the same logical category ic, but different test items of the product are not the same, so in actual implementation, it should not be limited to this. The first test early yuan 6 of Haihai is set in the second test area 22 ′ of the working platform 2 and has three test male boards 61. Each test male board 61 has a test socket 611 for the semiconductor component 丨 丨, and the semiconductor component η that has passed the basic electrical test is subjected to a male board test. However, in actual implementation, the number of the test male boards 61 may also be only one or more, and the increase or decrease of the number is not limited to that disclosed in this embodiment. It is worth mentioning that the so-called public board refers to the product use of the semiconductor structured component Π, and uses the actual electronic components and semiconductor components to simulate the working environment of the semiconductor structured component U on the circuit board, and its Rule 8 1225307 is the industry standard. For example, if the semiconductor component to be tested is a chipset for a personal computer host, the motherboard of the personal computer, the chipset is mounted on the motherboard, and an appropriate program is executed, Depending on whether the output function meets expectations, 5 can directly judge the quality of the semiconductor package component 11 to be tested. Of course, this is just an example using the semiconductor package component u to be tested as the chip group 1C. At this stage, graphics chips, integrated communication chips, network cards, and microprocessors can be used to develop the appropriate public boards, with more sophisticated test programs than the conventional ones, to test the public boards. Classes of quality. The public board test is the product function test of the semiconductor component u. It does not simply simulate the test environment with software, but tests with a physical circuit board, so the false test rate of the semiconductor component can be greatly reduced. In other words, the semiconductor component that passed the test at this stage can be called a good product. The discharging unit 7 is arranged at the front end of the work platform 2 and is adjacent to the feeding unit 3 and has a plurality of sorting boxes 71. , Can be used to load the plurality of semiconductor assembly components η that have been tested by the test public board 61. Each classification! 71 is arranged according to the predefined test results. In this preferred embodiment 20, the discharge unit 7 has The four sorting boxes 7b from left to right represent Pass Binl, Pass Bin2, functional test failures, and electrical test failures. The four sorting boxes 71 are semiconductor assembly components 11 tested by the test public board 61. It will be transported by the transport unit 4 to the corresponding sorting box 71 according to the test result. 9 1225307 In the & first preferred embodiment, the automatic testing device for the semiconductor component is more packaged It includes a buffer unit 8 and a holding unit 9. The buffer unit 8 is not placed on the work platform 2 and has a plurality of buffer seats 81. The plurality of buffer seats 81 are respectively arranged in the test to be movable back and forth respectively. Port 5 51 is in front of the three test sockets 611, and each buffer seat 81 is provided with two placement slots 811 for the semiconductor structure component u to be placed. The holding unit 9 is correspondingly disposed on the three test sockets 611. Above the test port 51, there are four pressing members 91. It should be noted here that the number of the pressing members depends on the test port 51 and the test sockets 611, 10, so when it is actually implemented, It should be limited to the description of this embodiment. Each pressing member 91 can move the semiconductor structure element π from the placement groove 811 on the child punch 81 in a vacuum suction manner up and down, and the semiconductor The structural component n is pressed into the test port 51 or the test socket 611, so that the semiconductor structural component u can be tightly combined with the first or 15 帛 WA unit 5 6 'to avoid test failure due to poor contact In the preferred embodiment, each pressing member 91 has a The heat-conducting heat-conducting block 911 can be continuously heated by the heat-conducting block 9U during the process of sucking the semiconductor-constructing element u to meet the semiconductor-constructing element U that needs to be subjected to a high-temperature test. 20 According to the above-mentioned hardware architecture, In the following, an embodiment of the automatic test device for a semiconductor component according to the present invention will be described. Referring to FIG. 5, before the description, it should be noted that the following test process is described using a test at normal temperature as an example. First 'Proceed to step 10, the worker will load a plurality of semi-conductor mounting elements 10 to be tested on the semiconductor carrier plate 11 stacked in order to supply the supply s 31, the supply _31 can provide lifting the semiconductor The function of the carrier disk 1 is to rotate the semiconductor element u. Next, go to step 20, the robot arm 41 of the conveying unit 4 will go to the top of the supply E M and descend to an appropriate height, and then use: The stealing head 411 on the arm 41 to suck the semiconductor component After 11, move to the buffer seat 8 i in the first test area 2 i, and place the semiconductor structure element adsorbed by the two suction heads 411 into the two placement slots 811. Next, proceed to step 30, the buffer seat 81 will move to the direction of the holding unit 9 'and stay at a position below the holding member M in the _ test area 21. Then, the holding member 91 in the first-test area 21 is lowered to the buffer seat 81 Λ, and the vacuum mounting method is used to suck the semiconductor structure element from the place on the buffer seat 81 15 # 811. . Then, the buffer seat 81 will immediately retreat. At this time, the holding member 91 will place the semiconductor structure element 11 in the test frame 51 so that the semiconductor structure element u can communicate with the first test unit. 5 tightly combined to avoid test failure due to poor contact. 20 Then, step 40 is performed. After the semiconductor structure element u completes the basic electrical test, the 'stomach holding # 91 t' is lowered and sucked again, and the semiconductor structure element 11 is released from the test port 51. At the same time, the robot arm 41 will suck and move the semiconductor structure element 11 in the other placement slot 811 on the buffer seat 81 to the previous placement slot 811. Next, proceed to step 50, the buffer seat 81 will move forward again and 11 1225307 will leave the empty storage slot 811 in the house holder.
為811中。然後，若半導體構裝元 、、、。果為削，則進行步驟60,該輸送單元 J 會將該半導體構裝元件u移至該 m41 敗分類…。 玄出科早-7之電性測試失 若基本電性測試結果為Pass 手臂料將該半㈣鮮元件«器 10 内之其中-緩衝座81上。緊接著：4 “二測試區22 捭i-… 者§亥緩衝座81會往該屡 ^早凡9的方向移動，並停留在該第二測試區η内之麗 15 持件9i的下方位置處。然後，該麼持件91會下降至 衝座81上，並以真空吸引的方式自該緩衝座81上之置放 2 8η中吸取該半導體構裝元件u。接著，該緩衝座81 會立·即後退，、㈣，持# 91會將料導體構農元件 11堡置入該測試插座611中，以使該半導體構裝元件U 可與該測試公板61緊密結合。 20 -在此、，應注意的是，由於基本電性測試之測試時間較 短，通常為1〜2秒，而公板測試所需時間較長，通常為μ 秒以上:所以，當該半導體構裝元件u執行公板測試的同 時’該第-測試區21内之基本電性測試已完成數次，並 藉由該機器手臂41 一一移動至該第二測試區22之各個緩 衝座81上置放。 < 而後，進行步驟80，當該半導體構裝元件u完成公 板測試之後，該壓持件91會再度下降吸取，並將該半導 12 1225307 ，構裝元件11自該測試插座611中脫離。同一日夺間，該機 益手臂41會將該緩衝座81上另—置放槽811内的半導體 構裝元件1卜吸取移至該前—個置放槽811内。此時，該 緩衝座81會再度向前移動並將該空的置8 10For 811. Then, if the semiconductor structure element, ,,,. If it is cut, go to step 60, the conveying unit J will move the semiconductor component u to the m41 classification ... If the basic electrical test result is Pass, it is expected that the half of the semi-fresh component «in the device 10» is on the buffer seat 81. Immediately after: 4 "Second test area 22 捭 i -... or § Buffer seat 81 will move in the direction of the repeated ^ Zaofan 9 and stay at the position below the Li 15 holder 9i in the second test area η Then, the holding member 91 will be lowered to the punching seat 81, and the semiconductor structure component u will be sucked out from the placement 2 8η on the buffering seat 81 by vacuum suction. Then, the buffering seat 81 will Immediately retreat, ㈣, holding # 91 will put the material conductor structure element 11 into the test socket 611, so that the semiconductor structure element U can be tightly combined with the test male board 61. 20-Here It should be noted that due to the short test time of the basic electrical test, usually 1 ~ 2 seconds, and the test time of the public board is longer, usually more than μ seconds: Therefore, when the semiconductor component u While the public board test is being performed, 'the basic electrical test in the first-test area 21 has been completed several times, and the robot arm 41 is moved one by one to each of the buffer seats 81 of the second test area 22 and placed. < Then, step 80 is performed. After the semiconductor component u has completed the public board test, the holding 91 will drop and suck again, and the semiconducting 12 1225307 and the structural element 11 will be detached from the test socket 611. On the same day, the machine arm 41 will place the buffer seat 81 on another—into the slot 811. The semiconductor structure component 1 is sucked and moved into the first-placement slot 811. At this time, the buffer seat 81 will move forward again and the empty place 8 10
壓持件91的下方，以使該一可將該經過 之半導體構裝元件u’置入該置放槽811中 '然後，依該 半導體構裝it件U之測試結果，藉由該輸送單元4之機器 手臂4Uf經過公板測試之半導體構裂元件u移至該出料 單元7之對應的分類£71中，以完成測試流程。X 15 上述的測試流程是以常溫測試，如欲進行高溫測試， 則於該輸送單元4至該供料!£ 31吸取該㈣體構裝元件 U之後，先將複數半導體構裝元件u移置於該預熱架Μ 上，藉由該預熱架32之獨立昇溫加熱功能進行預熱。之 後其餘的程序與前述程序並無二異，只是在該塵持件Μ 將該半導體構裝元# U壓持的過程中，藉由每-壓持件 91上的導熱塊911持續對該半導體構裝元件U進行加 熱’以保證該半導體構裝元#11在測試當中可繼續維持在口 設定的測試溫度之下。 20 依據上述說明可知，本發明半導體構裝元件之自動化 測試裝置，確實具有下列所述之功效增進： 一、縮短測試時間： 本發明在硬體設計上結合基本電性测試與公板測 試，屏除習知的軟體模擬測試，不需如習知一般，受 限於測試設備之硬體與軟體能力而必須經過層又層： 13 1225307 試：所以可將繁複的半導體測試流程精簡。此外，更 以夕組公板測試架構，搭配該緩衝單元8與該壓持單 疋9的„又计，分散該基本電性測試速度較快，而該公 5 板測試速度較慢，所造成的待機時間，所以確實可以 縮短測試時間。 二、降低測試成本： 本發明半導體構裝元件之自動化測試裝置，以公 板作為測試中心，取代昂貴的測試設備，由於公板的 10 來源無虞，且價格相對便宜許多，並節省測試程式的 1心π間所以可有效降低業者的測試成本，提昇競 爭力。 三、提高測試錯誤涵蓋率： 測試的根本目的是為了暴露半導體構裝元件，在 15 系統級環境中的相互作用問題，本發明半導體構裝元 件11的測試方法，以基本的電性測試搭配實體的公板 進行測試’可對待測的半導體構裳元件u進行最直接 的完整測試，將隱性的誤測率完全暴露出來，以提高 測試的錯誤涵蓋率。 20 歸納上述，知識經濟的時代，創新研發之知識為最富 價值之資產，本發明半導體構裝元件之自動化測試裝置， 藉由新❹m規晝，簡化設相試架構及•，對於降低 測試時間及成本有重大的料，並大幅簡化將來各類半導 體產品的測試方法，減少測試所耗費的時間，提高測試的 錯誤涵蓋率，並完全解決前述f知技#之缺點，故確實能 14 1225307 達到本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 【囷式簡單說明】 圖1是本發明半導體構裝元件之自動化測試裝置之較 佳實施例的立體示意圖； 圖2是該較佳實施例中一輸送單元的側視示意圖； 圖3是該較佳實施例中，一壓持單元與一緩衝單元的 立體示意圖； 圖4是圖丨中移去該壓持單元的俯視示意圖；及 ―圖5是本發明半導體構裝元件之自動化測試裝置之較 佳貫施例的測試流程示意圖。 15 1225307 【圖式之主要元件代表符號說明】 1 ·… 半導體承載盤 51 · · > 測試珲 11 * · · 半導體構裝元件 6 、· •第二測試單元 2 ·… 工作平台 61·* •測試公板 21 ·… 第一測試區 611 * •測試插座 22· · · 第二測試區 7 · · *出料單元 3 ·… 供料單元 71… •分類E 31··· 供料匣 8… * 緩衝單元 32· ♦ · 預熱架 81 .. •緩衝座 A 4 « 輸送單元 811 · •置放槽 41·· 機器手臂 9 · · •壓持單元 411 ·， 吸取頭 91 · · •壓持件 5 * * · 第一測試單元 911 · • 導熱塊The lower part of the holding member 91 is pressed so that the semiconductor mounting element u 'that can pass through can be placed in the placement slot 811'. Then, according to the test result of the semiconductor mounting device U, through the transport unit The robotic arm 4Uf of 4 has been tested with the semiconductor fracturing element u of the public board and moved to the corresponding category £ 71 of the discharging unit 7 to complete the testing process. X 15 The above test process is normal temperature test. If high temperature test is needed, after the conveying unit 4 to the supply! £ 31 After sucking the carcass structure component U, first shift the plurality of semiconductor structure components u. On the pre-heating rack M, pre-heating is performed by the independent heating and heating function of the pre-heating rack 32. After that, the rest of the procedure is no different from the foregoing procedure, except that during the process of holding the semiconductor structure element #U by the dust holding member M, the semiconductor block 911 on each holding member 91 is continuously applied to the semiconductor. The component U is heated to ensure that the semiconductor component # 11 can continue to be maintained below the test temperature set during the test. 20 According to the above description, it can be known that the automatic test device for semiconductor structured components of the present invention does have the following functions and enhancements: First, shorten the test time: The present invention combines basic electrical testing and public board testing on the hardware design. The conventional software simulation test does not need to be as common as it is. It is limited by the hardware and software capabilities of the test equipment and must go through layers: 13 1225307 Test: So the complicated semiconductor test process can be streamlined. In addition, with the test board public test structure, the buffer unit 8 and the holding unit 疋 9 are used to disperse the basic electrical test speed faster, and the public 5 board test speed is slower, resulting in Therefore, the test time can be shortened. Second, reduce the test cost: The automated test device of the semiconductor component of the present invention uses a public board as a test center to replace expensive test equipment. Since the public board has 10 sources, And the price is much cheaper, and saves 1 heart of the test program, so it can effectively reduce the test cost of the industry, and improve competitiveness. Third, improve the test error coverage: The fundamental purpose of the test is to expose the semiconductor assembly components. The interaction problem in the system level environment. The test method of the semiconductor component 11 according to the present invention is to test the basic electrical test with a physical public board. The most complete test can be performed on the semiconductor component u to be tested. The hidden false positive rate is fully exposed to improve the error coverage of the test. 20 In summary, the knowledge economy Generation, the knowledge of innovative research and development is the most valuable asset. The automatic test device for semiconductor structured components of the present invention, with the new rules, simplifies the phase test structure and •. It has significant material for reducing test time and cost. And greatly simplify the test methods of various semiconductor products in the future, reduce the time spent in testing, increase the error coverage of the test, and completely solve the disadvantages of the aforementioned know-how #, so it can indeed achieve the purpose of the present invention. 14 1225307 The above are only the preferred embodiments of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the content of the invention specification of the present invention should be It still falls within the scope of the patent of the present invention. [Brief description of the formula] FIG. 1 is a schematic perspective view of a preferred embodiment of an automated test device for a semiconductor component of the present invention; FIG. 2 is a conveying unit in the preferred embodiment 3 is a schematic perspective view of a pressing unit and a buffer unit in the preferred embodiment; FIG. 4 is a diagram 丨A schematic plan view with the holding unit removed; and-Fig. 5 is a schematic diagram of a test flow of a preferred embodiment of an automated test device for semiconductor-structured components of the present invention. 15 1225307 [Description of the main components of the drawings] 1 · … Semiconductor carrier 51 · · > Test 珲 11 * · · Semiconductor mounting element 6 · · · Second test unit 2 ·… Work platform 61 · * • Test male board 21 ·… First test area 611 * • Test Socket 22 · · · Second test area 7 · · * Withdrawal unit 3 · ... With feed unit 71… • Category E 31 ··· With feeder 8… * Buffer unit 32 · ♦ · Preheating rack 81 .. • • Buffer seat A 4 «Conveying unit 811 · • Placement slot 41 · · Robot arm 9 · · • Holder unit 411 ·, Suction head 91 · · • Holder 5 * * · First test unit 911 · • Thermal block
1616