1234662 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於一種測試方法，特別是指一種半導體 構裝元件的測試方法。 【先前技術】 芩閱圖1，一般來說一個完整的積體電路（IC)製造流 程，概可包括初期的積體電路設計（IC Design)l〇與晶圓製 造（Wafer Fabdcation)ll，中期的晶圓測試（Wafer 10 151234662 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a test method, and particularly to a test method for a semiconductor component. [Previous Technology] Review Figure 1. Generally speaking, a complete integrated circuit (IC) manufacturing process can include an initial integrated circuit design (IC Design) 10 and wafer manufacturing (Wafer Fabdcation) ll, medium-term Wafer test (Wafer 10 15
Sortmg)12 與封裝（Assembly & packaging)13，及後期的最 終測試（Final Test)Μ 與產品出貨（Shipment)15。 在積體電路日益微小化的同時，上述積體電路的製 程’在每曰一個製程階段都相當重要。其中，該封裝測試製 % 14乃疋積體電路（Ic)於封裝後，用以測試 帽生功能，以保註出…能上的完整性，並 =的產品依其電性功能分類（即分Bin)，以作為IC不同 4級產品的評價依據。 試以確保產品能正常運作 > 數進仃 ? 運作，用於測試之系統設備將根據 口口不同之測試項目而載入 裝型態而有所不同，^ 式，且視不同之: ^ 為確保半導體構裝成品的功能性及 疋性，構裝成品之諸項功能的性質檢驗尤為重要：及: 目前封裝後的半導體測試流程做一介:尤為重要，以下】Sortmg) 12 and Assembly & packaging13, and Final TestM and Shipment15. At the same time that integrated circuits are becoming more and more miniaturized, the above-mentioned process of integrated circuits is very important at each stage of the process. Among them, the package test system% 14 is the integrated circuit (Ic) after packaging, used to test the capping function to ensure the integrity of the ..., and = products are classified according to their electrical functions (ie Divided into Bin), as the basis for the evaluation of different IC grade 4 products. Try to ensure that the product can work normally.> Operation. The system equipment used for testing will be loaded according to different test items and installation types. ^ Type, and depending on the difference: ^ is To ensure the functionality and robustness of the finished semiconductor assembly products, it is particularly important to check the properties of the finished assembly functions: and: The current semiconductor testing process after packaging is introduced: it is particularly important, the following]
必須先了解半導㈣裝元㈣ 使在所賦予最糟的環境定義下，保證半導體J 20 1234662 (根據最初設計的功能）能正常的工作。而測試所考慮的 事項必須包含完成半導體元件測試的目標以及考慮成本 效益的測試。 參閱圖2，為目前封裝後的半導體測試流程，以邏輯 5 性產品而言，現階段的標準流程步驟如下，首先，在步驟 20中，是先預備好要上線測試的待測1C，將從上游廠商 送來的包箱内拆封，並——放在標準容器内，以利在上測 試設備（Tester )時，分類機（Handler )可以將待測1C定 位，而使其内的自動化機械裝置可自動上料與下料。 10 其次，在步驟21中，當備妥測試環境（包括測試系統、It is necessary to understand the semiconductor device to ensure that the semiconductor J 20 1234662 (according to the originally designed function) can work normally under the worst environmental definition. The test considerations must include the goal of completing semiconductor component testing and cost-effective testing. Refer to Figure 2. This is the current semiconductor testing process after packaging. For logic 5 products, the standard process steps at this stage are as follows. First, in step 20, the test 1C to be tested is prepared. The package sent by the upstream manufacturer is unpacked and placed in a standard container to facilitate the testing equipment (Tester). The classifier (Handler) can locate the 1C to be tested and make the automated machinery inside it. The device can load and unload automatically. 10 Second, in step 21, when the test environment (including the test system,
測試程式、分類機，以及連接介面）之後，進行產品的最終 測試（Final Testing，FT)，此階段之測試包含DC測試、AC 測試，及FC測試。DC測試一般包括開路/短路測試、輸 出最大漏電流/輸出最小漏電流測試等等。AC測試，主要 15 是量測1C元件的TIMING或是CLOCK參數特性，例如tD0E (OE/Low to Data Valid)。在此，應注意的是，有許多AC 測試只用於產品設計的參考及特性分析，在生產測試時， 不一定需要完全量測TIMING參數。而功能測試（FC TESTING)，gp在功能測試之前先將產品的DC參數設定 20 〔如VDD、VIH、VIL、VOH，及VOL〕再加上特定的時 序參數（TIMING SPEC)。然後以一連串的測試樣本（TEST PATTERN)根據TIMING SPEC輸入到待測1C中，並逐一 比較輸出是否為預期的高低電位狀態（HIGH/LOW STATE)。 1234662 在進行隶終產品測試時，必須搭配昂貴的測試設備 (Tester)，以其優越的硬體能力以及高速的運行速度，在極 短的時間内完成上述所有的測試。一般而言，每一個待側 IC通常需要6-7秒的測試時間，而此階段之收費也是以秒 計費，且所費不貲。 接著，進行步驟22，將通過步驟21的待測ic進行系 統級測試（System Level Testing，SLT)。-般而言，系統級 測試即是利用一測試公板，該測試公板是以發表該半導體 構裝το件所認證之同步發表的公板作為測試中心，將複數 通過該取樣抽測之半導體封裝元件進行公板測試。在進行 步驟22的系統級測試時，每—個待側1(：：所耗費之測試時 間至少需# 20秒以上，故此階段之收費是以小時計算， 價格也相對便宜許多。 化接著，在步驟23巾，進行取樣抽測（又稱為QC或q 貝）此作業的目的在於將通過產品最終測試的測試品 中、，隨機抽出一定數量的半導體封裝元件，重回步驟21 的測试現％，在測試程式、測試設備、測試溫度都不變下， 看其測試結果是否與先前的測試(FT)結果相_致。若不_ 致，。則有可能是測試機台故障、測試程式有問題、測試配 件抽壞測试過程有瑕庇··等原因，假設判斷原因為小者， 則將整批測過的半導體封裝元件退回到步驟21進行重 測。原因大者，進杆牛驟 Λ V驟231，將此批待測IC Hold住， 等待=㈣、生管人員與客戶協調後再作決策。 取後，進行步驟24，對該進行系統級測試之後的Ic !234662 進行出貨的運送作業。由於最終測試是半導體IC製程的 最後一站，所以許多客戶就把測試廠當作他們的成品倉 庫以避免自身工廠的成品存放的管理，另一方面也減少 不必要的成品搬運成本，至此完成整個半導體封裝後的測 試流程。 10 15 電子產品為了要求能提供完整的電性功能，所以經過 層層的測試把關，務求將出貨之半導體封襄元件百分之百 可用地乂到客戶手中。然而，隨著科技日新月異，許多半 導體晶片的功能愈來愈強化，運行速度也不斷攀高。現有 測，設備之功能，已逐漸不敷半導體晶片使用，因此使得 二多=產品無法進行測試。這也導致許多測試廠為了要測 試更高階的產品，必須不斷投入巨資，購買極為昂貴的先 進測試設備’冀求能跟上時代與產品的快速轉變。 然:，檢驗半導體晶片的各項功能除了硬體上的支援 之二’還需要編寫診斷的測試軟體，以軟體模擬真實的工 作衣兄目的疋確保半導體晶片的各項功能可按照初期IC 2計的要求工作。但是，無論各項測試程式編寫有多麼詳 f ’它還是無法找出部份的系統層次問題。當該項半導體 片的力月b和事件出現某種在元件 到過的順序或組合時，可Mm ± 中攸未遇 τ月匕就會產生使用上的問題。如果 這些問題出現太多（或者扃勃—舌西y 哺如果 ^ τ 1次者在執仃重要任務的產品中僅僅儡 然出現），用戶將备 偟僅偶 日Μ為廷些產品不可靠甚至是不穩定。 再者，有些半導體晶片之產品生命週期較 -伤完整的測試程式需要投入許多時間與人力，通常= 20 1234662 5 10 15 產品的測試程式需要3_6個月的時間來開發，這還 大里生產時修正程式參數或除錯的時間。所以 堪用時，該項產品往往已進入銷售末期，相當不敷U 基本上’耗費在測試的時間愈久，即代表廠商 力愈低落，而上述的種種問題也是目前眾多測試業者所益 法突破的困境。況且’大量的生產測試是以時間來计費… 愈複雜的測試程式相對耗費的測試時間愈久m高成 本的測試設備，與撰寫複雜的測試程式之後，再向客戶收 取高額的測試費用’似乎已失去了藉由測試來降低半導體 製造成本的原意。 _ 【發明内容】 因此，本發明之目的，是在提供一種具有簡化測試架 構及流程，降低測試時間及成本的半導體構裝元件的測試 方法。 於疋’本發明之半導體構裝元件的測試方法，適用於 封裝後之半導體測試製程，該方法包含下列步驟·· 首先，預備複數待測試半導體構裝元件。而後，分別 對每-半導體構裝元件進行基本電性測試，篩選出通過基 本電性測試之半導體構裝元件。接著，對每一個通過基本 電性測试之半導體構裝元件進行公板測試，再一次篩選出 通過公板測試之半導體構裝元件。最後，對每一個通過公 板測试之半導體構裝元件進行最終產品測試，進一步篩選 出測試失敗之部分，以得到確實可用的半導體構裝元件。 本發明之功效在於該基本電性測試與該公板測試之 20 1234662 測試價格相對該最終產品測試便宜許多，導入基本電性測 試與公板測試可減少一半的最終產品測試時間，以達到降 低測試成本與測試時間的功效。 【實施方式】 5 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之較佳實施例的詳細說明中，將可清楚 的明白。 參閱圖3,本發明半導體構裝元件的測試方法，適用 於封裝後的半導體測試製程，該半導體構裝元件的測試方 10 法之較佳實施例包含以下步驟。 首先，進行步驟31，建構一測試環境，準備複數個待 測試的半導體構裝元件，並備妥測試環境所需的測試系 統、程式、自動化設備，及人力安排。 接著，進行步驟32，對每一個半導體構裝元件進行基 15 本的電性測試，並筛選出通過基本電性測試之半導體構裝 元件。以本較佳實施例而言，該基本電性測試是包括開路 /短路測試（OPEN/SHORT TEST)，以及電源短路測試 (POWER SHORT TEST)。但實際實施時，該基本電性測試 還可以包括下列項目：輸出最大漏電流/輸出最小漏電流測 20 試(IOH/IOL TEST)、總體電流測試(GROSS IDD TEST)、 靜態電流測試（STATIC IDD TEST)、動態電流測試 (DYNAMIC IDD TEST)、輸出最小漏電流/輸出最大漏電 流測試（IIL/IIH TEST)、輸出高阻抗漏電流測試（IOZ TEST)、輸入高電位/輸入低電位測試（VIH/VIL TEST)，及 1234662 輸出南電位/輸出低電位m式（VOH/VOL test)等等。 舉例來說，以開路/短路測試（OPEN-SHORT TEST)而 s ’其目的是確保測試設備與待測試之半導體構裝元件的 5 f觸介面是否良好，_檢查該半導體構裳元件線路内部 疋否有開路或短路的情形。由於M〇s DEvice在削 通常内建有保護二極體（PR〇TECTI〇N則_在p通道 (:CHANNEL)或N通道（N CHANNEL)，此測試就是針對 這種特性來分析該半導體構裝元件是否測試失敗在開路/ 1〇 ^路的測柄目上。由於本較佳實施例之基本電性測試僅 作DC項目的量測，所以耗費的時間相當短，通常1〜2秒 的時間便已足夠。 在此，應注意的是，因各種半導體構裝元件之產品特 性不同，所需要的測試項目亦有不同，例如邏輯IC與記 憶體所需的測試項目便有差異，而本較佳實施例僅是以一 5 々又邏輯性產品為例來作說明，而且縱算是同屬邏輯類1C， 但產品不同測試項目亦不盡相同，故實際實施時，應不以 此為限。 而後，進行步驟33，將每一個通過基本電性測試之半 導體構裝元件置入-通用標準設計的公板中，進行公板測 2〇 忒，以實際的公板直接對每一個通過基本電性測試之半導 體構I 70件進行公板測試，再一次筛選出通過公板測試之 半導體構裝元件。本較佳實施例所述之公板，是泛指針對 斜導體構裝元件的產品功能，所設計製造出一業界通用 的標準電路板。 10 1234662 舉例來說，若該項待測試之半 電腦主機用m 構衣讀為一個人 版」主機极，《適切的個人電猫之「標準 5 10 15 20 安裝於該「標準版」之主機板:為：求’將該晶片組直接 且所輸出之θ 機板上’並執行適當的程式，視 -η出之功月匕疋否#合預 半導體構裝元件好壞。 η直㈣斷⑦待測試之 當然，這只是以該項待測試之半導體封襄元件為 :Γ:::舉例說明。現階段的繪圖晶片、整合性二 =、 及微處理器等等都可以通過開發適切之 二板/配相對於習知較為精巧的測試程式，來作公板測 :，並依品質等級加以分類。況且，開發公板用的測試程 所需的時間並不長久，通常只要數星期便可完成，而 公板因製作簡單所以需求並不虞匱乏，相 …邮動軏數千萬元以上的天價，以及開發冗長繁複的= 4%式，其中的差異不言可喻。 在此，應注意的是，此階段之測試是以產品功能測試 (FC Testing)為主，所謂的Funcd〇n測試就是產品的真正功 能測試，以一連串的TEST PATTERN輸入該半導體裝元 件，並逐一比較該半導體構裝元件之輸出是否有符合預期 的高低電位狀態（HIGH/LOW STATE)。唯一不同的是，此 階段並非單純以軟體模擬測試環境，而是以實際的公板進 行測試。也由於並非模擬測試，所以該半導體構裝元件之 好壞立可判見。換言之，通過此階段測試之半導體構裝元 件即為確定可用的良品。 11 1234662 此外，由於該公板測試是針對所有的功能輸出檢驗， 所以測試的時間較長，通常需要2G #以上的時間，是整 個測試過程中最耗費時間的步驟。 正 接著，進行步驟34,對每一個通過公板測試之半導體 構裝元件進行最終產品測試(Final TeSting)，進—步筛選出 最終測試失敗的半㈣構裝元件，而其餘剩下 確實可用的半導體構裝元件。 P4 ίο 15 20 在此，應注意的是，此階段之測試是以ac測試⑽ Testing)為主，這裡的AC測試是指針對該半導體構裝元件 的時序、時鐘頻率（Timing、cl〇ck)來作測試，由於公板測 ^無法完成該半導體構裝元件的AC_Timing以及⑽心 測试’所以在公板測試之後，必翻以習知中最終產品測 摘AC測試，才算完成所有的測試項目。而該最終產品 測試由於不需要進行Dc與FC測試，所以可節省許多測 试時間，通常這只需要2〜3秒便可完成，這與習知的最終 產口口測试需要6〜7秒的時間，相差一半以上。 然後’進行步驟35，對該複數通過最終產品測試之半 導體構裝元件進行取樣抽測。亦即自該複數完成步驟34 :半導體構裝元件中抽出一定數量，重回相同的測試環 境’在測試程式、贼設備與測試溫度都不變的情況下， 檢驗其測試結果是否與之前的測試結果一致，以作為繼續 下一測試流程的依據。 、在本較佳實_巾，該㈣35所代表的意義是為避 免進行測4日守，因電子產品不可抗拒的電子或電力因素， 12 1234662 而導致誤測現象產生，所以多一道取樣的檢查關卡，可以 增加產品測試的穩定度。此時，便可保証出廠的半導體構 裝元件在功能與穩定度上的完整性。 當然，步驟35並非一定要作，端視客戶是否有此需 求，本較佳實施例是以有執行取樣抽測的流程，來作揭 路’故實際實施時，不應以此為限。 最後，進行步驟36，將前述通過取樣測試之半導體構 裝件運送出貨。針對客戶的要求，測試廠可以提供所謂 的「Door to Door」的服務，即幫助客戶將測試完成品送 至客戶指定的地方（包括客戶的產品買家），有些客戶指 的地點在海外者，便需要考慮船期的安排，如果在國内 者，則要考慮貨運的安排事宜。由於出貨運送的管理並非 本發明之重點所在，故於此不再詳加敘述。上述步驟進行 至此，便完成了封裝後的半導體構裝元件之測試流程。 同樣地，步驟36也並非固定流程，端視客戶是否有 此需求，本較佳實施例是以有執行出貨運送的完整流程， 來作揭露，故實際實施時，也可以不包含步驟36，不應侷 限於本實施例所揭露。 配合參閱圖4，一般測試程式的測試項目基本上都包 括DC、AC，以及FC三大測試主項，該半導體構裝元件 必須在每一項皆測試通過才能算是良品。而本發明中步驟 32之基本電性測試與步驟33之公板測試，可以先完成該 半導體構裝元件的DC與FC測試，且單純的DC測試 (Open/Short & Power Short Testing )所需的硬體設備並不 13 !234662 需要太南槽，而勃并+ 丁 ^驟33所需的測試公板也相對便宜， 所以剩下需要佶用5ll & & 】車父南檔測試設備的AC測試部份，便 不需要耗費太長的測試時間。 5 古依據以上的說明，將本發明與習知的封裝後半導體測 *、弋作比車又，可知本發明誠具許多功效增進之處， 細說明如下： 一、簡化測試流程。 10 由於本發明先以簡單的基本電性測試，篩選出電 性測试失敗之半導體構裝元件，再以實體的公板測試 取代習知的軟體模擬測試，可直接測出真正的半導體 冓A元件在真實工作環境下的運作情形，所以不需要 如習知一般，受限於測試設備之硬體與軟體能力而必 須經過完整的Dc、AC，以及Fc測試，所以確實可 以將繁複的半導體測試流程精簡。 15 二、 縮短最終測試時間。 20 、、只上所述，由於習知的最終產品測試（FT)必須跑 完測試程式所定義的所有測試項目，通常這需要花費 6〜7秒的時間，而本發明以基本電性測試配合公板測 弋了以取代習知隶終產品測試中的DC與FC測試 部份，所以在最終測試時，僅須針對Ac_Timing與 Clock的σ卩伤進行測試，通常這只需要用到2〜3秒的 時間，故能有效的縮短產品最終測試時間。 三、 降低測試成本。 由於產品最終測試（FT)必須搭配昂貴的測試設備 14 1234662 (Tester)，所以在收費方面是以秒計費，而本發明之基 本電性測試與公板測試，可以先完成該半導體構裝元 件的DC # FC測試，剩下需要使用到較高槽測試設 備的AC測試部份，僅需耗費相對習知不到一半的測 試時間，所以能降低測試成本。此外，對於測試業者 來說，由於不再需要投入高額的費用購買昂貴先進的 測試設備，以及大幅縮短了測試所耗費的時間，所以 可有效地降低業者的測試成本。而相對於客戶來說， 亦因為不需耗費人力成本開發測試軟體，所以可節省 ίο 15 20 開發、除錯，及調整程式參數的時間，所以確實能達 到降低成本的目的。 四、獲得精確的測試良率。 本發明半導體構裝元件的測試方法，是以基本的 電性測試流程胸&實體的公用電路板進行測試，可對 待/則的半‘體構裝元件進行最直接的完整測試，將隱 性的1C誤測率完全暴露出來’並回饋提供給上游之 丄C設計業者精確的測試良率。 知識經濟的時代，創新研發之知識為最富價值之^ 產，本發明半導體構裝元件的測試方法，藉由新的測試央 畫’簡化設計職架構及流程，對於降低測試時間及成4 有重大的影響，並大幅簡化將來各類半導體產品的測試2 法，減少測試所耗費的時間，提高測試的錯誤涵蓋率。 曰歸納上述，我國目前在半導體產業上的IC封娜 排名世界第—，技術與美國、日本，以及韓國並fs 15 1234662 5 10 15 20 而我國產學界致力於半導體領域的研究成績，也— 二世人刮目相看，而享譽全球。在m◦三年全世 界雨六大封裝測試公司，我國就佔有前幾名，台灣百分之 十：加工出口區廠商都從事與ic封裝測試有關的產 ^其群聚的效應十分龐大。在這樣的前提下，若我們只 疋故V自冑’而不嘗試著突破瓶頸與開發新的測試方法， 則目前的領導地位終會被超越，而通過本發明半導體構裝 兀件的K方法’主要係將基本電性測試結合系統級測試 (System Level Test)的觀念’導人目前產能及測試技術以達 瓶頸的铸體測試產業中，藉由簡單實際的公板測試環境 取代目前行之有年的軟模擬測試環境，進而使得測試產品 2測試精準度提昇，且能有效降低測試成本，與縮短測試 牯間，故確實能達到本發明之目的。 淮以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發”請專利 祀圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 【圓式簡單說明】 圖1是一般積體電路製造的流程示意圖； 圖2是習知封裝後半導體構裝元件的測試流程示意 圖3是本發明半導體構裝元件的測試方法的較佳實施 例的測試流程示意圖；及 圖4是一方塊示意圖，說明基本電性測試與公板測 16 1234662 試，可取代DC與FC測試，而AC測試部份則由最終測試 來完成。 17 1234662 【圖式之主要元件代表符號說明】 31〜36。 步驟 18After testing the program, classifier, and connection interface), final testing (FT) of the product is performed. The tests at this stage include DC test, AC test, and FC test. DC test generally includes open / short test, output maximum leakage current / output minimum leakage current test, etc. AC test, the main 15 is to measure the TIMING or CLOCK parameter characteristics of 1C components, such as tD0E (OE / Low to Data Valid). Here, it should be noted that there are many AC tests that are only used for reference of product design and characteristic analysis. In production testing, it is not necessary to fully measure the TIMING parameters. For functional testing (FC TESTING), gp sets the DC parameters of the product 20 [such as VDD, VIH, VIL, VOH, and VOL] before adding the functional timing parameters (TIMING SPEC). Then input a series of test samples (TEST PATTERN) into the 1C under test according to the TIMING SPEC, and compare one by one whether the output is the expected high / low potential state (HIGH / LOW STATE). 1234662 When carrying out final product testing, it must be equipped with expensive test equipment, with its superior hardware capabilities and high-speed operating speed, to complete all the above tests in a very short time. Generally speaking, each standby IC usually requires 6-7 seconds of test time, and the charge at this stage is also charged in seconds, which is not expensive. Next, step 22 is performed, and a system level test (SLT) is performed through the ic to be tested in step 21. -In general, the system level test is to use a test public board, which uses the published public board certified by the semiconductor structure το as a test center, and passes a plurality of semiconductor packages that pass the sampling test. Components are tested on a public board. When performing the system-level test in step 22, each of the standby 1 (:: test times spent at least # 20 seconds or more, so the charge at this stage is calculated in hours, and the price is relatively cheaper. Then, in Step 23: Sampling and sampling (also known as QC or Q shell) The purpose of this operation is to randomly extract a certain number of semiconductor packaging components from the test products that pass the final test of the product, and return to the test of step 21% When the test program, test equipment, and test temperature are unchanged, see if the test results are consistent with the previous test (FT) results. If not, it may be that the test machine is faulty and the test program has There are problems, such as flaws in the testing process of the test accessories. If it is judged that the cause is small, the entire batch of tested semiconductor package components will be returned to step 21 for retesting. Λ V step 231, hold this batch of ICs to be tested, wait for = ㈣, the production management staff and the customer to coordinate and then make a decision. After taking it, go to step 24, and ship the Ic! 234662 after system-level testing. Luck Since the final test is the last stop of the semiconductor IC manufacturing process, many customers use the test plant as their finished product warehouse to avoid the management of finished product storage in their own factories, on the other hand, it also reduces unnecessary finished product handling costs. At this point, the entire testing process after the semiconductor package is completed. 10 15 In order to provide complete electrical functions for electronic products, we have to go through layers of testing to ensure that 100% of the semiconductor package components shipped are available to customers. With the rapid development of science and technology, the functions of many semiconductor wafers are becoming more and more intensive, and the operating speed is also increasing. The existing testing and equipment functions have gradually become inadequate for the use of semiconductor wafers, which makes Erduo = products unable to be tested. This also leads to In order to test higher-level products, many test factories must continuously invest huge sums of money to purchase extremely expensive advanced test equipment 'to keep up with the rapid changes of the times and products. However: Examining the functions of semiconductor wafers in addition to hardware Support on the second 'need to write diagnostic test software Using software to simulate real work, I want to make sure that the various functions of the semiconductor chip can work according to the requirements of the initial IC 2. However, no matter how detailed each test program is written, it 'can't find out some system levels. Problem. When the force b and the event of the semiconductor chip appear in a certain order or combination of components, Mm ± Zhongyou has not encountered τ month dagger will cause problems in use. If these problems appear too much (Or 扃 扃-西西 y If ^ τ 1 times only appears in products that perform important tasks), users will prepare only occasionally as some products are unreliable or even unstable. Furthermore The life cycle of some semiconductor wafer products is relatively long-a complete test program requires a lot of time and labor, usually = 20 1234662 5 10 15 The test program of the product takes 3_6 months to develop, which also corrects the program parameters during production Or debug time. Therefore, when it is ready for use, the product often has reached the end of sales. It is quite inadequate. Basically, the longer the time spent in testing, the lower the manufacturer ’s power. The above-mentioned problems are also the breakthroughs of many test operators. Dilemma. Moreover, "a large number of production tests are charged by time ... The more complex the test program, the longer the test time, the higher the cost of the test equipment, and after writing the complex test program, the customer will be charged a high test fee." The original intent to reduce semiconductor manufacturing costs through testing has been lost. _ [Summary of the Invention] Therefore, an object of the present invention is to provide a method for testing a semiconductor component having a simplified test structure and process, and reduced test time and cost. The method for testing a semiconductor device according to the present invention is applicable to a semiconductor test process after packaging. The method includes the following steps. First, prepare a plurality of semiconductor device components to be tested. Then, basic electrical tests are performed on each semiconductor component, and the semiconductor components that pass the basic electrical test are screened. Next, a public board test is performed on each of the semiconductor fabricated components that passed the basic electrical test, and the semiconductor fabricated components that passed the male panel test are screened again. Finally, the final product test is performed on each semiconductor component that passed the board test, and the failed part is further screened to obtain a truly usable semiconductor component. The effect of the present invention is that the basic electrical test and the public board test 20 1234662 test price is much cheaper than the final product test. The introduction of the basic electrical test and the public board test can reduce the final product test time by half, so as to reduce the test. Cost and effectiveness of test time. [Embodiment] 5 The foregoing and other technical contents, features, and effects of the present invention will be clearly understood in the following detailed description of preferred embodiments with reference to the drawings. Referring to FIG. 3, a method for testing a semiconductor device according to the present invention is applicable to a semiconductor testing process after packaging. A preferred embodiment of the method for testing a semiconductor device includes the following steps. First, proceed to step 31, construct a test environment, prepare a plurality of semiconductor components to be tested, and prepare test systems, programs, automation equipment, and manpower arrangements required by the test environment. Next, step 32 is performed to perform a basic electrical test on each semiconductor component, and a semiconductor component that has passed the basic electrical test is selected. In the preferred embodiment, the basic electrical test includes an OPEN / SHORT TEST and a POWER SHORT TEST. However, in actual implementation, the basic electrical test can also include the following items: output maximum leakage current / output minimum leakage current test 20 (IOH / IOL TEST), overall current test (GROSS IDD TEST), static current test (STATIC IDD TEST), dynamic current test (DYNAMIC IDD TEST), output minimum leakage current / output maximum leakage current test (IIL / IIH TEST), output high impedance leakage current test (IOZ TEST), input high potential / input low potential test (VIH / VIL TEST), and 1234662 output south potential / output low potential m-type (VOH / VOL test) and so on. For example, the OPEN-SHORT TEST test is used to ensure that the 5 f contact interface between the test equipment and the semiconductor component under test is good. _ Check the inside of the semiconductor component circuit. Whether there is an open or short circuit. Because Mos DEvice usually has a built-in protection diode (PRoTECTION) in p-channel (: CHANNEL) or N-channel (N CHANNEL), this test is to analyze the semiconductor structure for this characteristic. Whether the test of the installed component fails on the open / 10 ^ test handle. Since the basic electrical test of this preferred embodiment is only for DC project measurement, the time consumed is relatively short, usually 1 to 2 seconds. Time is enough. Here, it should be noted that due to the different product characteristics of various semiconductor components, the test items required are different. For example, the test items required for logic IC and memory are different. The preferred embodiment is only described by using a 5々 logical product as an example, and even if it belongs to the same logical category 1C, but the different test items of the product are not the same, so it should not be limited in actual implementation. Then, proceed to step 33, place each semiconductor component that has passed the basic electrical test into a common board of common standard design, and perform a public board test of 20 忒, and pass the basic board directly to each of them. Electrical test half 70 pieces of body structure I were tested on the public board, and once again the semiconductor components that passed the public board test were screened. The public board described in this preferred embodiment is a product function of a generic pointer to diagonal conductor structured components. Manufactured a standard circuit board commonly used in the industry. 10 1234662 For example, if the half of the computer host to be tested is read as a human version with a m-type suit, the "standard 5 10 15 20 for a suitable personal electric cat" Installed on the "standard version" motherboard: To find 'the chipset directly and output on the θ board' and execute the appropriate program, depending on -η 出 之 月 月 疋 疋 No # 合 预 countless semiconductor structure The installed components are good or bad. Of course, this is only to be tested. Of course, this is only based on the semiconductor package component to be tested: Γ ::: An example. The current stage of the drawing chip, integration, and micro processing. Devices, etc. can be used for public board testing by developing appropriate two boards / matching test programs that are more sophisticated than conventional ones, and classify them according to quality levels. Moreover, the time required to develop a test process for public boards Not long, usually just count It can be completed in a week, and the public board is not in short supply due to its simple production. Compared to the post price of tens of millions of yuan, and the development of a long and complicated = 4% formula, the difference is self-evident. It should be noted that the testing at this stage is mainly based on product testing (FC Testing). The so-called Funcdon test is the true function test of the product. A series of TEST PATTERN is used to input the semiconductor components and compare them one by one. Whether the output of the semiconductor component meets the expected high / low potential state. The only difference is that at this stage, the test environment is not simply simulated by software, but the actual public board is used for testing. Since it is not a simulation test, the quality of the semiconductor component can be judged immediately. In other words, a semiconductor fabrication component that passes the test at this stage is determined to be a good product. 11 1234662 In addition, because this public board test is for all functional output tests, the test takes a long time, usually requiring more than 2G #, which is the most time-consuming step in the entire test process. Next, go to step 34, perform a final product test (Final TeSting) on each semiconductor component that passed the public board test, and further screen out the half-package components that failed the final test, and the remaining ones that are actually available Semiconductor fabrication components. P4 ίο 15 20 Here, it should be noted that the test at this stage is mainly ac test ⑽ Testing). The AC test here refers to the timing and clock frequency (Timing, cloc) of the semiconductor component. For the test, because the public board test cannot complete the AC_Timing and core test of the semiconductor component, so after the public board test, the final product test AC test must be turned to the conventional product test before all tests are completed. project. The final product test can save a lot of test time because it does not require Dc and FC test. Usually, it only takes 2 ~ 3 seconds to complete, which is 6 ~ 7 seconds with the conventional final product test. Time difference of more than half. Then, the process proceeds to step 35, where a sampling test is performed on the plurality of semiconductor component components that passed the final product test. That is, step 34 is completed from the plural: a certain amount is extracted from the semiconductor component, and the same test environment is returned. Under the condition that the test program, thief equipment and test temperature are not changed, check whether the test result is the same as the previous test. The results are consistent as a basis for continuing the next test process. In this case, the significance of this ㈣35 is to avoid the measurement of 4 days, due to the irresistible electronic or electrical factors of the electronic product, 12 1234662, which leads to the false detection phenomenon, so an additional sampling inspection Checkpoints can increase the stability of product testing. In this case, the integrity of the function and stability of the semiconductor component manufactured at the factory can be guaranteed. Of course, step 35 is not necessarily required. Depending on whether the customer has this requirement, the preferred embodiment uses a process of performing sampling and sampling to uncover the road. Therefore, the actual implementation should not be limited to this. Finally, step 36 is performed to ship the semiconductor package that passed the sampling test. According to customer requirements, the test factory can provide so-called "Door to Door" service, that is, to help customers send the finished test products to the customers 'designated places (including customers' product buyers). Some customers refer to locations overseas. Therefore, it is necessary to consider the arrangement of shipping schedules. If you are in the country, you need to consider the arrangement of freight. Since the management of shipping is not the focus of the present invention, it will not be described in detail here. So far, the above steps are completed, and the testing process of the packaged semiconductor component is completed. Similarly, step 36 is not a fixed process. Depending on whether the customer has this requirement, this preferred embodiment is based on the complete process of performing shipping and delivery. Therefore, step 36 may not be included in actual implementation. It should not be limited to that disclosed in this embodiment. With reference to Figure 4, the test items of the general test program basically include three main test items: DC, AC, and FC. The semiconductor component must pass each test before it can be regarded as a good product. In the present invention, the basic electrical test in step 32 and the public board test in step 33 can first complete the DC and FC test of the semiconductor component, and the simple DC test (Open / Short & Power Short Testing) is required. The hardware equipment does not need 13! 234662, and the test board required by Bo ++ Ding 33 is relatively cheap, so the rest need to use 5ll & & The AC test part does not need to take too long test time. 5 Based on the above description, comparing the present invention with the conventional packaged semiconductor test *, and comparing the car with the conventional one, we can see that the present invention has many improvements in efficiency, and the details are as follows: 1. Simplify the test process. 10 Because the present invention first uses simple basic electrical tests to screen out semiconductor structural components that fail electrical tests, and then replaces the conventional software simulation test with a physical public board test, the real semiconductor can be directly measured. The operation conditions of the components in the real working environment, so it does not need to be as familiar, limited by the hardware and software capabilities of the test equipment, and must undergo a complete Dc, AC, and Fc test, so it can indeed test complex semiconductors Streamlined processes. 15 2. Shorten the final test time. 20. As mentioned above, since the conventional final product test (FT) must run through all the test items defined by the test program, it usually takes 6 to 7 seconds, and the present invention cooperates with the basic electrical test The public board test has replaced the DC and FC test parts in the conventional final product test, so in the final test, it is only necessary to test the σ damage of Ac_Timing and Clock, usually this only needs 2 ~ 3 The time in seconds can effectively shorten the final test time of the product. Third, reduce testing costs. Because the product final test (FT) must be equipped with expensive test equipment 14 1234662 (Tester), the charge is charged in seconds. The basic electrical test and public board test of the present invention can complete the semiconductor component first. DC # FC test, leaving the AC test part that requires higher slot test equipment, it only takes less than half of the test time that is relatively familiar, so it can reduce the test cost. In addition, for testers, the cost of testing can be effectively reduced because they no longer need to invest high costs to purchase expensive and advanced test equipment, and significantly reduce the time it takes to test. Compared with customers, because it does not require human labor to develop test software, it can save time for developing, debugging, and adjusting program parameters, so it can really achieve the goal of reducing costs. Get accurate test yields. The testing method of the semiconductor structure component of the present invention is based on the basic electrical test process of the chest & entity common circuit board test. The most direct and complete test of the semi-body structure component can be performed, and the hidden The 1C false test rate is fully exposed 'and feedback is provided to the upstream C design industry for accurate test yields. In the era of the knowledge economy, the knowledge of innovative research and development is the most valuable product. The test method of the semiconductor component of the present invention simplifies the design structure and process through the new test script. Significant impact, and greatly simplify the test 2 methods of various semiconductor products in the future, reduce the time spent testing, and improve the error coverage of the test. To sum up, China ’s IC industry in the semiconductor industry currently ranks No. 1 in the world, and technology and the United States, Japan, and South Korea are fs. The world is astounding and world-renowned. In the past three years, the world ’s top six packaging and testing companies have been in the top six in China, and Taiwan has 10%: manufacturers in processing export areas are engaged in IC packaging and testing related products. The effect of clustering is huge. Under such a premise, if we only try to avoid V ’s failure without trying to break through the bottleneck and develop new test methods, the current leadership position will eventually be surpassed, and the K method of the semiconductor component of the present invention will be passed. 'Mainly the concept of combining basic electrical testing with System Level Test' leads the current production capacity and testing technology to reach the bottleneck in the casting test industry, replacing the current practice with a simple and practical public board testing environment The soft simulation test environment for several years has further improved the test accuracy of the test product 2 and can effectively reduce the test cost and shorten the test interval. Therefore, the object of the present invention can be achieved. The above is only a preferred embodiment of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, the simple equivalent changes made according to the content of the "invention of patents and invention specification" and Modifications should still fall within the scope of the invention patent. [Circular brief description] Figure 1 is a schematic diagram of the general integrated circuit manufacturing process; Figure 2 is a schematic diagram of a conventional semiconductor package testing process after packaging. The test flow diagram of the preferred embodiment of the method for testing semiconductor component invented inventions; and FIG. 4 is a block diagram illustrating the basic electrical test and the public board test. The copies are completed by the final test. 17 1234662 [Description of the main symbols of the drawings] 31 ~ 36. Step 18