CN114414978A - Interconnection test fixture and interconnection test method for silicon-based component - Google Patents

Abstract

The invention discloses an interconnection test fixture and an interconnection test method of a silicon-based component, belonging to the technical field of advanced electronic packaging, wherein the interconnection test fixture of the silicon-based component comprises a vacuum adsorption hole, an X-axis limit stop, a Y-axis limit stop and a test area Z plane adjuster, so that a tested piece is three-dimensionally adjusted, the problems of clamping and compatibility of different silicon-based components are solved, the risk of fragments is avoided, and the purposes of universality and convenient use of the test fixture are achieved; the interconnection test method utilizes an isolation technology to carry out direct current and alternating current characteristic tests, reduces test errors by reducing generated current branches, and ensures the accuracy of a measurement value; the method has the advantages that the test of the micro-system component level is realized, most fault components can be detected before the functional performance test, the first pass rate of the final functional performance test is improved, the follow-up quality hidden danger and the resource waste are avoided, and the test coverage rate of the network is effectively improved.

Description

Interconnection test fixture and interconnection test method for silicon-based component

Technical Field

The invention belongs to the technical field of advanced electronic packaging, and particularly relates to an interconnection test fixture and an interconnection test method for a silicon-based component, which can be used for detecting assembly defects in the process of developing the silicon-based component.

Background

The following trends have been shown in recent years for advanced packaging technology development: firstly, a single chip develops towards multiple chips; two-dimensional (2D) to three-dimensional (3D); integrating heterogeneity and heterogeneity. The 2.5D package can realize high-density interconnection of a plurality of chips and a package substrate through a Silicon adapter plate, namely Silicon Interposer, and the 3D package can realize three-dimensional stacking of chips containing reconstructed chips through a chip-to-chip/chip-to-wafer/wafer-to-wafer bonding process. In the production process of the micro-system, the problems of poor components and parts, open circuit, short circuit, insufficient soldering and other assembly problems are main reasons for causing electrical performance faults of the micro-system and reducing assembly through rate. How to efficiently, comprehensively and accurately complete the component level test is a problem which must be solved in the production process of microsystem products.

The strategy established for testing microsystems is to divide the testing into different packaging levels, and attach importance to the testing of the micro-assembly process. There are two main types of conventional assembly defect detection methods: one uses an automatic optical detector, an X-ray detector and the like to find welding defects and wrong installation of components through an appearance information area, and the other uses a needle bed tester and the like to find possible assembly defects through an electrical performance test means. The former can not detect the problems of invisible welding defects, failure of components and the like, and the test coverage rate is low; the latter needs to make test fixture for different products, and the making and debugging cycle is long and the cost is high. Because the silicon-based component has the characteristics of diversification, thinning, miniaturization, high-density I/O contact and the like, aiming at the interconnection test of the silicon-based component, an effective test fixture and a test method are not available in the industry.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide an interconnection testing clamp and an interconnection testing method for a silicon-based component, so as to solve the problem of testing the silicon-based component with the characteristics of diversification, thinning, miniaturization, high-density I/O contact and the like in a micro system, and meet the requirements of testing and timely feedback process in a research and development stage and performing rapid quality evaluation in a batch production stage.

In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:

the invention discloses an interconnection test fixture of a silicon-based component, which comprises: the tray is provided with a test area on the tray, the test area is provided with vacuum adsorption holes, the vacuum adsorption holes are connected with a vacuum air valve, two adjacent sides of the test area are respectively provided with a Y-axis limit stop and an X-axis limit stop, the tray is also respectively provided with an X-axis limit micrometer, a test area Z plane regulator and a Y-axis limit micrometer, the test area Z plane regulator is connected with the test area, and the X-axis limit micrometer and the Y-axis limit micrometer are respectively connected with the X-axis limit stop and the Y-axis limit stop.

Preferably, the tray is provided with a Y-axis limit stop adjuster and an X-axis limit stop adjuster which are respectively used for adjusting the Y-axis limit stop and the X-axis limit stop.

Preferably, the tray is provided with a tray upper track edge and a tray lower track edge, and the tray upper track edge and the tray lower track edge are respectively located at two ends of the tray.

The invention also discloses an interconnection testing method of the silicon-based component, which comprises the following steps:

the method comprises the following steps: preparing test data;

step two: checking a test system;

step three: after the test system finishes the verification, loading a tested piece, and placing the tested piece on a test fixture; the whole body is moved into a test system by scanning the contraposition point;

step four: carrying out test setting according to the tested piece;

step five: performing test, namely performing direct current and alternating current characteristic test by adopting an isolation technology according to the set test conditions;

step six: judging the test result within a threshold value and outputting the result;

step seven: and unloading the tested piece.

Preferably, the test data in the first step includes a pin color table for debugging, computer aided design files in ODB + + format and bill of material data for silicon interposer/silicon substrate and its assembly functionality description.

Preferably, in the first step, the correctness and precision of the voltage/current/capacitance excitation and detection of the test system are verified through the calibration plate.

Preferably, the test setup in step four comprises: loading a test program, and setting test parameters, wherein the test parameters comprise a selected test item, a set test condition, a test threshold and a test contact pressure.

Preferably, in step five, the test execution specifically includes an open circuit test, a short circuit test, a contact test, a power-ground impedance test and a signal-ground impedance test.

Preferably, the test timing is selected to adopt a low-elasticity spring probe to match with a soft landing technology for testing after the chip is welded with the silicon adapter plate and before the bottom filling is carried out.

Compared with the prior art, the invention has the following beneficial effects:

the invention discloses an interconnection test fixture of a silicon-based component, which enables the upper surface of a product and the fixture to be basically horizontal through a vacuum adsorption hole, a Y-axis limit stop, an X-axis limit stop and a Z-plane regulator of a test area on the test area; fixing the product by an X-axis limit stop and a Y-axis limit stop, and confirming the position by a micrometer zero clearing function; finally, connecting a vacuum air valve to fix a product; the problems of clamping and compatibility of different silicon-based components are solved, the risk of fragments is avoided, and the purposes of universality and convenient use of the test fixture are achieved.

Furthermore, the X-axis track stop block adjuster and the Y-axis track stop block adjuster are rotated to adjust the X-axis limit stop block and the Y-axis limit stop block so as to fix the testing area.

Further, the test fixture is installed and fixed on the test device through the edge of the upper tray rail and the edge of the lower tray rail.

The invention also discloses an interconnection testing method of the silicon-based component, in order to improve the testing coverage rate of the network, the testing content covers the direct current and alternating current characteristics, the isolation technology is utilized, the testing error is reduced by reducing the generated current branches, and the accuracy of the measuring value is ensured; the test of the micro-system component level is realized, the electrical performance and the electrical connection of the assembly-welded components are tested to check the production and manufacturing defects and the component defects, most of fault components can be detected before the functional performance test, the first pass rate of the final functional performance test is improved, and the follow-up potential quality hazard and the resource waste are avoided. In addition, the invention can be directly applied to the test of different substrate assemblies such as ceramics, PCBs and the like and micromodules of different packaging levels in an extensible way, has both efficiency and sufficiency, is suitable for the micro-assembly test in the production process of a micro-system, lays a foundation for the industrialization of the micro-system, has very wide application prospect and market potential, and has important strategic significance and social benefit. The test effect is taken as an example of a tested silicon adapter plate inverted single chip assembly, the size of the silicon adapter plate is 22mm × 22mm, the number of test points, namely, bumps on the back surface of the silicon adapter plate, is 1849, the size is 200 μm, the center distance is 500 μm, and the number of networks is 530. The network test coverage rate reaches 100%, the test only takes 32 minutes and 12 seconds per particle, almost no needle mark is observed under the condition of 10 times of magnification of a microscope, and the post process is not influenced.

Furthermore, a low-elasticity spring probe is used in the test process, the contact pressure is reduced by matching with a soft landing technology, the needle mark is minimized, and the nondestructive test is realized; by combining the process flow and the steps, the test opportunity is selected after the chip is welded with the silicon adapter plate and before the bottom filling is not carried out, once the problem is found, the problem can be repaired in time, and the waste caused by the fact that the whole waste cannot be reworked is reduced.

Drawings

FIG. 1 is a schematic structural diagram of a silicon-based component packaged by a silicon interposer flip chip according to the present invention;

FIG. 2 is a schematic structural diagram of a silicon-based component packaged by a silicon-based embedded reconfigurable chip according to the present invention;

FIG. 3 is a schematic view of a test fixture of the present invention;

FIG. 4(a) is a voltage pattern diagram illustrating the open circuit test and short circuit test principles of the present invention;

FIG. 4(b) is a 2-line measurement diagram of the open circuit test and short circuit test principle of the present invention;

FIG. 4(c) is a 4-line measurement diagram of the open circuit test and short circuit test principle of the present invention;

FIG. 5(a) is a schematic diagram of a contact test of the present invention;

FIG. 5(b) is a schematic diagram of a contact test of the present invention;

FIG. 6(a) is a schematic diagram of the node impedance test of the present invention;

FIG. 6(b) is a schematic diagram of the node impedance test of the present invention;

FIG. 7 is a schematic diagram of the isolation technique of the present invention;

FIG. 8 is a flow chart illustrating interconnection testing of silicon-based components according to the present invention;

fig. 9 is a schematic structural view of a measured member.

Wherein: 1-stacking multiple chips; 2-flip chip; a 3-silicon interposer; 4-a first micro bump; 5-chip stacking of 3D TSVs; 6-silicon interposer 2.5D TSV; 7-a first bump; 8-a second bump; 9-rewiring layer; 10-thinning the chip; 11-through silicon vias; 12-a second microbump; 13-a silicon substrate; 14-X axis limit micrometer; 15-test zone Z-plane conditioner; a 16-Y axis limiting micrometer; 17-a test area; 18-Y axis limit stops; 19-X axis limit stops; 20-Y axis limit stop adjuster; 21-X axis limit stop adjuster; 22-vacuum adsorption holes; 23-the upper track edge of the pallet; 24-the tray lower track edge; 25-tray.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The invention is described in further detail below with reference to the accompanying drawings:

referring to fig. 1, a schematic diagram of a structure of a Silicon-based component with a Flip Chip package of a Silicon Interposer as a tested piece according to the present invention is shown, where 1 is a multi-Chip Stack, i.e., Die Stack, 2 is a Flip Chip Die, 3 is a Silicon Interposer, i.e., Silicon Interposer, 4 is a first Micro Bump, i.e., Micro Bump, 5 is a Chip Stack 3D TSV, 6 is a Silicon Interposer 2.5D TSV, and 7 is a first Bump, i.e., Bump. The multi-chip stacking 1 realizes vertical interconnection among chips through the micro bumps 4 and the chip stacking 3D TSV 5, one part of the micro bumps 4 of the lowest chip is led out outwards through the bumps 7 connected to the back of the silicon adapter plate 3, and the other part of the micro bumps 4 connected with the flip chip 2 realizes horizontal interconnection among the chips. The structure is applicable to silicon-based component stacking layers of which the number is more than or equal to 1, single-layer silicon adapter plate flip chips or chips of which the number is more than or equal to 1, and a plurality of chips can be arranged in 2D or stacked in 3D. The silicon adapter plate can be a TSV adapter plate containing 2.5D TSV6 or a planar silicon adapter plate containing no 2.5D TSV6, and the back surface of the silicon adapter plate can be directly provided with an Under Bump Metallurgy (UBM).

Referring to fig. 2, a schematic diagram of a Silicon-based component packaged by a Silicon-based embedded reconfigurable chip according to the present invention is shown, where 8 is a second Bump, i.e., Bump, 9 is a redistribution Layer, i.e., Re-Distribution Layer, RDL, 10 is a thinned chip, i.e., Thin Die, contact surface is upward, 11 is a Through Silicon Via, i.e., Through Silicon Via, TSV, 12 is a second Micro Bump, i.e., Micro Bump, and 13 is a Silicon Substrate, i.e., Silicon Substrate. A second bump 8, a rewiring layer 9, a thinned chip 10, a through silicon via 11 and a second micro bump 12 are arranged on the silicon substrate 13; the second bump 8 and the second micro bump 12 are respectively arranged on the front side and the back side of the silicon substrate 13, the thinned chip 10 is arranged in the center of the silicon substrate 13, the rewiring layer 9 and the through silicon via 11 are arranged around the thinned chip 10, and the pin of the thinned chip 10 can be connected to the position of the second bump 8 on the front side of the silicon substrate 13 through the rewiring layer 9 or connected to the position of the second micro bump 12 on the back side of the silicon substrate 13 through the rewiring layer 9 and the through silicon via 11. The invention includes but is not limited to the structure, is suitable for the silicon-based component stacking layer number more than or equal to 1, the number of the embedded chips of the silicon substrate is more than or equal to 1, the second salient point 8 on the front surface of the silicon substrate 13 can be a second micro salient point 12, and the second salient point 12 on the back surface can also be a second salient point 8.

Referring to fig. 3, 14 is an X-axis limit micrometer, 15 is a test area Z plane adjuster, 16 is a Y-axis limit micrometer, 17 is a test area, 18 is a Y-axis limit stopper, 19 is an X-axis limit stopper, 20 is a Y-axis limit stopper adjuster, 21 is an X-axis limit stopper adjuster, 22 is a vacuum adsorption hole, 23 is a tray upper rail edge, 24 is a tray lower rail edge, and 25 is a tray; the tray 25 is provided with a test area 17, the test area 17 is provided with vacuum adsorption holes 22, two adjacent sides of the vacuum adsorption holes 22 on the test area 17 are respectively provided with a Y-axis limit stop 18 and an X-axis limit stop 19, the tray 25 is further respectively provided with an X-axis limit micrometer 14, a test area Z plane regulator 15 and a Y-axis limit micrometer 16, the test area Z plane regulator 15 is connected with the test area 17, the X-axis limit micrometer 14 and the Y-axis limit micrometer 16 are respectively connected with the X-axis limit stop 19 and the Y-axis limit stop 18, the tray 25 is provided with a Y-axis limit stop regulator 20 and an X-axis limit stop regulator 21 which are respectively used for regulating the Y-axis limit stop 18 and the X-axis limit stop 19, and two ends of the tray 25 are respectively provided with an upper tray track side 23 and a lower tray track side 24.

The use mode is as follows: placing a product to be tested at the lower right corner of a test area 17 of the clamp, and adjusting a Z-axis plane through a test area Z-plane adjuster 15 to enable the upper surface of the product and the clamp to be basically horizontal; the X-axis track stop adjuster 21 and the Y-axis track stop adjuster 20 are rotated to fix the X-axis limit stop 19 and the Y-axis limit stop 18 in the test area 17, and the position is confirmed through the zero clearing function of the X-axis limit micrometer 14 and the Y-axis limit micrometer 16; finally, connecting a vacuum air valve to fix a product; and after the test is finished, the vacuum is closed through the air valve controller, and the product is taken, placed and replaced.

Open and short circuit tests were based on a resistance test model, using a voltage mode, as shown in fig. 4 (a). If 2-line measurement is used, the measurement results include the line group and the contact resistance, as shown in fig. 4(b), and if 4-line measurement is used, the errors introduced by the line group and the contact resistance can be removed, as shown in fig. 4 (c).

The contact test is based on a diode test model, as shown in fig. 5(a), when a voltage is applied to the P-N terminal of the diode, a conduction current is generated in the same direction, and the forward conduction voltage is measured, the conduction voltage of the silicon diode is about 500mV to 700 mV. The purpose of the contact test is to ensure that all pins of the device under test are properly connected, and that the pins are not shorted to power, ground, or each other. The principle of the contact test is shown in fig. 5(b), I bus is connected with a-Node, S bus is connected with C-Node, when a fault occurs, an abnormal voltage value can be detected, and the fault type is determined.

The node impedance test is based on a capacitive, inductive test model, as shown in fig. 6 (a). The combined inductive and capacitive resistance of a circuit is commonly referred to as reactance, and the magnitude of the reactance depends on the magnitudes of the inductive and capacitive reactance. The total impedance Z is obtained by calculating the resistance R and the reactance X, and the capacitive reactance Z_cAnd inductive reactance Z_lThe test principle is shown in fig. 6(b), and the node impedance test is divided into a signal-ground impedance test and a power-ground impedance test, the signal-ground impedance test covers the impedance between the signal network and the ground network, and the power-ground impedance test covers the impedance between the different power network and the ground network.

The isolation technique principle is shown in fig. 7. There is a distinction between single element testing and element testing in complex networks. Assuming that we want to measure a resistance R, if R is a separate element, R can be simply measured with a multimeter, if R is in a complex network, it is easy to directly measure R + Z1+ Z2, and the test results are much improved when we introduce isolation techniques. Isolation reduces test errors by reducing the number of current branches generated, the best isolation device is the ideal op-amp, and no current branches are created without voltage differences in the input path.

Referring to fig. 8, the interconnection testing method of the silicon-based component mainly includes the following steps:

1. preparing test data. The test data comprises a pin Color table Color Map for debugging, computer aided design CAD files in ODB + + format for describing the silicon adapter plate/silicon substrate and the assembly functionality thereof, a bill of material BOM and other data.

2. And (5) developing a test program. Test program development contains 7 sub-steps:

setting a test program, describing information which is not contained in a CAD file, such as the requirement of a test surface of a tested piece, such as the front surface or the back surface or the double surfaces, the height of the tested piece, which is not more than 7 mm or more than 7 mm and less than 55 mm, and selecting a test item, such as an open circuit test, a short circuit test, a contact test, an impedance test and the like;

importing a file, importing and translating an ODB + + file, and reading network information;

checking data, automatically analyzing the data to correct error data, including deleting useless information, setting device type, assembly form and assembly surface Not mounted bottom or Not mounted top by combining a bill of materials;

generating a test program, firstly determining the direction of the tested piece, then calculating the accessibility of the network, and then editing the test configuration file and generating the test program;

pre-aligning inspection, self-defining a calibration point and a debugging test point, firstly finding two points on a layout as reference points, then finding an actual test point through a camera, and then confirming a contact position and selecting a contact probe;

debugging the test items, and debugging one by one according to the selected test items in the substep I by combining the pin color table according to different networks and pin attributes;

and seventhly, confirming a test result, outputting the test result and analyzing the stability.

3. And (5) verifying the test system. The correctness and precision of the voltage/current/capacitance excitation and detection of the test system are verified through the calibration board.

4. And loading the tested piece. Placing the tested piece on a test fixture according to the test surface and the direction of the tested piece determined in the step 2; and the whole body is moved to the ideal position of the test system by scanning the contraposition point.

5. And (6) testing and setting. Loading a test program; and setting test parameters including test item selection, test condition setting, test threshold value, contact pressure testing and the like.

6. And (6) executing the test. And D, testing the direct current and alternating current characteristics by adopting an isolation technology according to the set test conditions.

7. And outputting the result. The test pass/fail depends on the decision threshold.

8. And unloading the tested piece. Unloading the tested piece and then exiting the test or preparing the next tested piece for testing.

Examples

The following describes a silicon-based component interconnection test from several aspects, such as information of a tested device, a test flow, a test technology, a test coverage and a test time, by taking an assembly test of a PoP (Package on Package) as an example.

Information of the tested piece

The tested piece is a 3-layer silicon-based assembly PoP information processing micromodule, as shown in FIG. 9, the uppermost layer is a silicon adapter plate flip 1 PowerPC processor die, the middle layer is a silicon adapter plate flip 3 DDR memory die, and the lowermost layer is a silicon adapter plate flip 2 Flash memory die.

TABLE 1 information of a measured part

Therefore, after 2 layers of the PowerPC, DDR, Flash single-layer silicon-based component and the DDR + Flash silicon-based component are stacked, the test surface is required to be a back surface, a double surface and a double surface respectively; the height of the measured piece is not more than 7 mm; and selecting the mounting surface of the device as Not mounted top according to the actual situation.

Test flow

The test strategy is formulated by comprehensively considering factors such as process realizability, testability and test coverage rate, and the micro-module test is divided into three levels: firstly, performing interconnection test on PowerPC, DDR and Flash single-layer silicon-based components; secondly, performing interconnection test after 2 layers of DDR + Flash silicon-based components are stacked; and finally, testing the functional performance of the stacked 3-layer silicon-based component. The interconnection test is mainly carried out in the assembling process, and the functional performance test after the assembling is finished does not belong to the scope of the invention.

Testing techniques

In order to ensure the completeness of the test and analyze the characteristics of the piece to be tested, the adopted test technology comprises the following steps: open circuit testing, short circuit testing, contact testing, power-ground impedance testing, and node impedance testing.

Open circuit test

The open circuit test is used for detecting the connectivity of all networks with the same name, and ensures that all power supplies and ground pins of the tested piece are correctly connected without open circuit.

Short circuit test

The short circuit test is used for detecting the isolation among different networks and ensuring that the tested piece signal, the power supply and the ground pin are not short-circuited mutually.

Contact testing

The contact test judges whether the chip is damaged or not by detecting the characteristic of the protection diode of the chip pin, and ensures that all signal pins of the tested piece are normally contacted and are not short-circuited with a power supply and the ground.

Power-ground impedance test and signal-ground impedance test

The node impedance test comprises a power supply-ground impedance test and a signal-ground impedance test, wherein the power supply-ground impedance test detects the characteristics of parasitic parameters such as capacitive impedance and inductive impedance of a power supply network relative to a ground network; the signal-ground impedance test detects the characteristics of parasitic parameters such as capacitive impedance and inductive impedance of a signal network relative to a ground network, and ensures that the process can meet the design requirements and the consistency of the monitoring and manufacturing process. The node impedance test can create reference data through standard part test or tested part learning, and the reference data is used for test judgment of other tested parts. With the increase of the number of the test samples, the reference data can be continuously corrected through big data analysis.

Test coverage and test time

On the premise of ensuring a silicon adapter plate and a chip, the interconnection test is respectively carried out on the PowerPC/DDR/Flash single-layer silicon-based component, and the network test coverage rate can reach 100%. In order to avoid the problem that the early failure escape is caused by the fact that the PowerPC processor accesses the DDR/Flash memory internal interconnection and is not easy to test, the DDR + Flash silicon-based component stacking test is preferentially carried out, and the network test coverage rate can also reach 100%. The testing is carried out before the bottom filling, so that the network full coverage is realized, the problem can be repaired in time once the problem is found in the assembling process, and the first pass rate of the functional performance testing after the assembling is greatly improved.

Table 2 test coverage and test time

In conclusion, the test fixture is designed and manufactured by combining the characteristics of thin and fragile silicon-based components and possibly different heights of chips, the problems of clamping and compatibility of different silicon-based components are solved by combining the vacuum adsorption hole 22, the X-axis limit stop 19, the Y-axis limit stop 18 and the test area Z plane adjuster 15, the fragment risk is avoided, and the purposes of universality and convenience in use of the test fixture are achieved; in order to improve the test coverage rate of the network, the test content covers the direct current and alternating current characteristics, and specifically comprises an open circuit test, a short circuit test, a contact test, a power supply-ground impedance test and a signal-ground impedance test; in the testing process, a low-elasticity spring probe is used, and the soft landing technology is matched to reduce the contact pressure, minimize the needle mark and realize nondestructive testing; by utilizing an isolation technology, the test error is reduced by reducing the generated current branches, and the accuracy of a measurement value is ensured; by combining the process flow and the steps, the test opportunity is selected after the chip is welded with the silicon adapter plate and before the bottom filling is not carried out, once the problem is found, the problem can be repaired in time, and the waste caused by the fact that the whole waste cannot be reworked is reduced. The interconnection test fixture and the interconnection test method for the silicon-based component avoid the risk of fragments, improve the test coverage rate of an interconnection line, namely a network, give consideration to efficiency and sufficiency, and are suitable for detecting the assembly defects in the process of developing the silicon-based component.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (10)

1. An interconnection test fixture for silicon-based components, comprising: tray (25), be provided with test area (17) on tray (25), be provided with vacuum adsorption hole (22) on test area (17), vacuum valve is connected in vacuum adsorption hole (22), be provided with Y axle limit stop (18) and X axle limit stop (19) respectively on the adjacent both sides of test area (17), tray (25) still is provided with X axle limit micrometer (14) respectively, test area Z plane regulator (15) and Y axle limit micrometer (16), test area Z plane regulator (15) are connected test area (17), X axle limit stop (19) and Y axle limit stop (18) are connected respectively to X axle limit micrometer (14) and Y axle limit micrometer (16).

2. The interconnection testing jig for silicon-based components according to claim 1, wherein the tray (25) is provided with a Y-axis limit stop adjuster (20) and an X-axis limit stop adjuster (21) for adjusting the Y-axis limit stop (18) and the X-axis limit stop (19), respectively.

3. The interconnection testing fixture of silicon-based components according to claim 1, wherein the tray (25) is provided with a tray upper rail edge (23) and a tray lower rail edge (24), and the tray upper rail edge (23) and the tray lower rail edge (24) are respectively located at two ends of the tray (25).

4. A method for testing interconnection of silicon-based components using the interconnection test jig of silicon-based components according to any one of claims 1 to 3, comprising:

the method comprises the following steps: placing a tested piece on a vacuum adsorption hole (22) of a test area (17), adjusting the three-dimensional position of the test area (17) through a Y-axis limit stop (18), an X-axis limit stop (19) and a test area Z plane adjuster (15), and determining the position of the tested piece through an X-axis limit micrometer (14) and a Y-axis limit micrometer (16);

step two: after the test system is verified, loading a tested piece, and integrally moving a test fixture where the tested piece is located into the test system through scanning the alignment points;

step three: carrying out test setting according to the tested piece;

step four: performing test, namely performing direct current and alternating current characteristic test by adopting an isolation technology according to the set test conditions;

step five: judging the test result within a threshold value and outputting the result;

step six: and unloading the tested piece.

5. The interconnection testing method of silicon-based components according to claim 4, wherein in step one, the Z plane adjuster (15) of the testing area keeps the upper surface of the tested piece and the fixture horizontal, and the Y axis limit stop (18) and the X axis limit stop (19) fix the testing area (17) on the X-Y plane.

6. The method of claim 4, wherein the testing setup in step four comprises: loading a test program, and setting test parameters, wherein the test parameters comprise a selected test item, a set test condition, a test threshold and a test contact pressure.

7. The interconnection testing method of silicon-based components according to claim 4, wherein in step five, the test execution specifically includes an open circuit test, a short circuit test, a contact test, a power-ground impedance test and a signal-ground impedance test.

8. The method of claim 7, wherein the timing of the testing is selected after the die is bonded to the silicon interposer and before the underfill is performed.

9. The method of claim 7, wherein the testing is performed using a low spring force probe with soft landing.

10. The method according to claim 4, wherein in step one, the calibration board is used to verify the correctness and accuracy of the voltage/current/capacitance excitation and detection of the test system.

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